JP2006129390A - Transmitting apparatus and receiving apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission device, a reception device, and a transmission system capable of low-noise and wide-band data transmission while performing stable clock reproduction.
In a multi-value transmission method, data transmission is performed in a frame structure using a mapping method using all values in a data portion and a mapping method in which a clock is multiplexed in a header portion. The symbol timing on the receiving side is reproduced only during the header period, and data is extracted from the received data portion signal and header portion signal based on the reproduced symbol timing.
[Selection] Figure 1

Description

  The present invention relates to a transmission device and a reception device, and more particularly to a transmission device and a reception device using a multilevel transmission method, and a transmission system and a vehicle including those devices.

  In recent years, the introduction of an in-vehicle LAN that enables data communication between in-vehicle devices in automobiles has become full-scale. In addition, with the increase in the number of functions of car navigation devices and the spread of ITS (Intelligent Transport Systems), the data to be transmitted on the in-vehicle LAN has also become diversified and increased in capacity, so that larger volumes of data can be transmitted at higher speeds. Realization of a transmission method that can be transferred to the network is desired.

  By the way, in the case of an in-vehicle LAN, radiation noise from a cable constituting the in-vehicle LAN may cause malfunction of the in-vehicle device, and conversely, radiation noise from the in-vehicle device adversely affects data transmission in the in-vehicle LAN. Countermeasures for these problems are being considered. For example, in an optical transmission type LAN, noise resistance is improved while preventing the generation of electromagnetic waves by connecting each node with an optical fiber cable and optically communicating with each other.

  On the other hand, a transmission system capable of high-speed data transmission exceeding 20 Mbps while reducing electrical noise and improving noise resistance while conducting electrical transmission using inexpensive cables such as twisted pair wires and coaxial cables is also devised. (For example, refer to Patent Document 1). Hereinafter, this conventional transmission system will be described.

  FIG. 9 is a block diagram showing a configuration of a conventional transmission system. The transmission apparatus 9100 includes a clock multiplex mapping unit 9104 and a DAC (Digital-to-Analog Converter) 9110. The reception device 9200 includes an ADC (Analog-to-Digital Converter) 9210, a symbol timing recovery unit 9207, and a clock multiple inverse mapping unit 9204.

  First, the operation of transmitting apparatus 9100 will be described.

  The clock multiplex mapping unit 9104 maps data of a predetermined number of bits (here, 2 bits) of the transmission data 9101 to one of a plurality of predetermined signal levels (here, 8 signal levels) for each symbol period. Is. FIG. 6 shows a mapping table (8-level clock multiplex mapping table) used in the clock multiplex mapping unit 9104, and FIG. 8 shows an example of a signal pattern mapped based on the mapping table of FIG. The signal level (current signal level) output from the clock multiplex mapping unit 9104 corresponds to the signal level of the previous symbol (previous signal level) and 2 bits input to the clock multiplex mapping unit 9104 according to the mapping table of FIG. It is determined according to transmission data 9101. For example, the signal level of the nth symbol in FIG. 8 is that the signal level of the (n−1) th symbol is −3 and the input 2-bit transmission data 9101 is “01”. +5 is determined from the mapping table. As a result, a signal having a signal level of +5 is output from the clock multiplex mapping unit 9104 as the nth symbol.

  Next, the operation of receiving apparatus 9200 will be described.

  The signal received from the transmission line 9300 is a signal in which clocks are fixedly multiplexed as shown in FIG. Symbol timing recovery section 9207 extracts the clock component from the output of ADC 9210 to recover symbol timing 9206, and outputs this symbol timing 9206 to clock multiplex inverse mapping section 9204.

The received data 9201 output from the clock multiplex mapping unit 9104 includes the signal level of the previous symbol (previous signal level) and the signal level of the symbol input from the ADC 9210 to the clock multiplex inverse mapping unit 9204 according to the mapping table of FIG. It is determined according to the current signal level. For example, in the received data 9201 corresponding to the nth symbol in FIG. 8, the signal level of the (n−1) th symbol is −3, and the signal level of the input nth symbol is +5. 6 is determined from the mapping table 6. As a result, data “01” is output from the clock multiplex inverse mapping section 9204 as the reception data 9201 corresponding to the nth symbol.
Japanese Patent No. 3502630

  However, when a mapping method in which clocks are multiplexed as shown in FIG. 6 is adopted, symbol reproduction on the reception side is facilitated, but on the other hand, there is a problem that the transmission bit rate is lower than in a mapping method in which clocks are not multiplexed. is there. For example, when a mapping method that does not multiplex clock components is used in N-value multilevel transmission, the number of transmission bits per symbol is log2 (N), but when a mapping method that multiplexes clocks is used, As can be seen from the mapping table of FIG. 6, the number of transmission bits per symbol is log2 (N) -1 bits even though N signal level numbers are used. That is, by multiplexing clocks according to the mapping table as shown in FIG. 6, the transmission bit rate is reduced at a rate of 1 bit per symbol.

  Further, when a mapping method in which clocks are multiplexed is employed, radiation noise due to a fixed clock component is generated from the transmission path as shown in FIG. In order to reduce this, high-performance external parts for noise reduction are required, and the cost of the entire transmission system is increased accordingly.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a transmission device and a reception device that can perform electric transmission in a wider band than conventional systems and can reduce radiation noise due to clock components.

  In order to solve the above problems, the present invention employs the following configuration. Reference numerals and figure numbers in parentheses indicate correspondence with the drawings in order to help understanding of the present invention, and do not limit the scope of the present invention.

  In the first invention, N-bit transmission data, which is a predetermined number of bits, is sequentially mapped to a predetermined signal level out of M signal levels, which is a predetermined number, for each predetermined symbol period. And an all-value mapping means (1103) for generating an all-value mapping signal, and N-1 bits of transmission data for any given symbol period, one of the upper half of the M signal levels. A clock multiplex mapping means (1104) for generating a clock multiplex mapping signal in which a clock component is multiplexed by alternately and sequentially mapping the signal level and any one of the lower half signal levels; and the full value mapping signal and the clock multiplex The mapping signal is alternately selected at a fixed timing based on the transmission header enable signal, and the first transmission signal is selected. A transmitting apparatus (1100) having a first selection means and (1105) for outputting Te.

  According to a second invention, in the first invention, a clock signal generating means (1106) for generating a clock signal (FIG. 3) that toggles with a maximum amplitude at the M signal levels for each fixed symbol period; Header initialization signal generating means (1107) for generating a header initialization signal (FIG. 3) that toggles with the minimum amplitude at the M signal levels for each symbol period, and an initialization control signal based on the transmission header enable signal Initialization control means (1109) for generating the first transmission signal, the second transmission means for selecting the clock signal and the header initialization signal based on the initialization control signal and outputting them as a second transmission signal (1108).

  According to a third invention, in the second invention, the second selection means determines the clock signal and the header initialization signal based on the transmission header enable signal before the output of the first transmission signal. It is characterized by being alternately selected and output at the timing (FIG. 2A).

  In a fourth aspect based on the first aspect, when the clock multiplex mapping means cuts out only the clock multiplex mapping signal from the first transmission signal and connects them, the signal level of each symbol with respect to the immediately preceding symbol is determined. A clock multiplex mapping signal is generated such that the magnitude relationship changes alternately with the symbol period (FIG. 6).

  According to a fifth invention, in the fourth invention, the clock multiplex mapping means is configured such that the clock multiplex mapping signal has a fixed signal level in at least the first and last symbols of the symbols constituting each clock multiplex mapping signal. Is generated (FIG. 7).

  In a sixth aspect based on the fifth aspect, the clock multiplex mapping means has a maximum of the M signal levels or at least the first and last symbols of the symbols constituting each clock multiplex mapping signal. A clock multiplex mapping signal that generates a minimum signal level is generated (FIG. 7).

  A seventh invention is a receiving device (1200) for receiving a signal having the same configuration as the signal output from the transmitting device of the first invention, wherein the reception timing of the clock multiplex mapping signal from the received signal And a header detection means (1208) for generating a received header enable signal indicating the detection result, and when receiving the clock multiplex mapping signal based on the received header enable signal, the timing of the symbol from the received signal The symbol timing is generated by detecting the symbol timing, and when the full-value mapping signal is received, the symbol timing is generated using the timing of the symbol detected when the clock multiplexed mapping signal was last received. Timing reproduction means (1207) and the symbol tie A full-value inverse mapping means (1203) for reversely mapping the signal level of each symbol of the received full-value mapping signal based on the symbol timing generated by the sampling reproduction means to sequentially generate N-bit received data; Based on the symbol timing generated by the symbol timing recovery means, clock multiplex inverse mapping means (in order to generate N-1 bit received data sequentially by inverse mapping the signal level of each symbol of the received clock multiplex mapping signal) 1204) and third selecting means (1205) for selecting and outputting the N-bit received data and the N-1 bit received data according to the received header enable signal.

  The eighth invention is a receiving device (1200) for receiving a signal having the same configuration as the signal output from the transmitting device of the third invention, wherein the reception timing of the clock multiplex mapping signal from the received signal And a header detection means (1208) for generating a received header enable signal indicating the detection result, and when receiving the clock multiplex mapping signal based on the received header enable signal, the timing of the symbol from the received signal The symbol timing is generated by detecting the symbol timing, and when the full-value mapping signal is received, the symbol timing is generated using the timing of the symbol detected when the clock multiplexed mapping signal was last received. Timing reproduction means (1207) and the symbol tie A full-value inverse mapping means (1203) for reversely mapping the signal level of each symbol of the received full-value mapping signal based on the symbol timing generated by the sampling reproduction means to sequentially generate N-bit received data; Based on the symbol timing generated by the symbol timing recovery means, clock multiplex inverse mapping means (in order to generate N-1 bit received data sequentially by inverse mapping the signal level of each symbol of the received clock multiplex mapping signal) 1204) and third selection means (1205) for selecting and outputting the N-bit reception data and the N-1 bit reception data according to the reception header enable signal, and the header detection means, Detecting the clock signal and the initialization signal from the received signal, By holding the reception timing and reception period of the issued initialization signal and the reception period of the detected clock signal, the clock multiplex mapping signal sequentially received after receiving the initialization signal and the clock signal A receiving apparatus is characterized by detecting reception timing.

  According to the first aspect of the invention, since the full value mapping signal and the clock multiplex mapping signal are alternately transmitted, it is possible to increase the transmission speed while stably reproducing the clock on the receiving side. Furthermore, since the period in which the clock components are fixedly multiplexed can be made local, radiation noise due to the clock components can be reduced. As a result, noise reduction parts can be reduced, which is advantageous in terms of cost.

  According to the second and third aspects of the invention, since it is possible to notify the receiving device of the header start timing and header end timing necessary for the reception processing, the hardware configuration necessary for the header detection processing in the reception device is provided. It can be simplified and is advantageous in terms of cost.

  According to the fourth aspect of the present invention, when the clock multiplex mapping signals are connected, the magnitude relationship of the signal level of each symbol with respect to the immediately preceding symbol changes alternately with the symbol period. Can be played.

  According to the fifth aspect of the invention, since the signal level of a specific symbol in the clock multiplex mapping signal can be fixed, the clock multiplex mapping signal may have a signal pattern that is inappropriate for reproducing the symbol timing in some cases. Can be avoided.

  According to the sixth aspect of the present invention, when the clock multiplex mapping signals are connected, a change from the minimum signal level to the maximum signal level or a change from the maximum signal level to the minimum signal level is periodically performed. Since it appears, the clock can be effectively reproduced on the receiving side.

  According to the seventh aspect, since a transmission signal mapped with all values can be used, a broadband transmission signal can be received. Further, since a transmission signal subjected to clock multiplex mapping can be used, stable clock reproduction can be performed.

  According to the eighth aspect of the invention, since the start timing and end timing of the clock multiplex mapping signal can be easily known from the received initialization signal and clock signal, the hardware configuration necessary for header detection processing is simplified. This is advantageous in terms of cost.

  A transmission system according to an embodiment of the present invention will be described with reference to FIG. In the present embodiment, a case where an 8-level transmission system is adopted as an example of a multi-level transmission system will be described. Of course, the present invention can also be applied to multilevel transmission systems other than the 8-level transmission system.

  The transmission apparatus 1100 includes an all value mapping unit 1103, a clock multiplexing mapping unit 1104, a first selector 1105, a clock signal generation unit 1106, a header initialization signal generation unit 1107, a second selector 1108, an initialization control unit 1109, and a DAC (Digital). -To-Analog Converter) 1110. The receiving apparatus 1200 includes an ADC (Analog-to-Digital Converter) 1210, a symbol timing reproduction unit 1207, a header detection unit 1208, an all-value inverse mapping unit 1203, a clock multiplexing inverse mapping unit 1204, and a third selector 1205. .

  A transmission-side external device (not shown in FIG. 1) connected to the transmission apparatus 1100 disables the transmission header enable 1102 and transmits 3 bits / symbol as transmission data 1101 during the transmission data transmission period. Transmission data is input to the transmission apparatus 1100 at a rate. In the header data transmission period, the transmission header enable 1102 is enabled, and the header data is input to the transmission apparatus 1100 as the transmission data 1101 at a transmission rate of 2 bits / symbol. The transmission header enable 1102 is a signal for distinguishing the transmission period of the header portion from the transmission period of the data portion, and is enabled during the transmission period of the header portion (four symbol periods in the present embodiment). Is disabled during the transmission period (252 symbol periods in the present embodiment).

  The external device on the receiving side (not shown in FIG. 1) connected to the receiving device 1200 transmits transmission data at a transmission rate of 3 bits / symbol as reception data 1201 during a period in which the reception header enable 1202 is disabled. Is received from the receiving device 1200. Further, during the period in which the reception header enable 1202 is enabled, the header data is received from the reception apparatus 1200 as the reception data 1201 at a transmission rate of 2 bits / symbol. The reception header enable 1202 is a signal for distinguishing the reception period of the header part from the reception period of the data part, and is enabled during the reception period of the header part and disabled during the reception period of the data part.

  Hereinafter, operations of the transmission device 1100 and the reception device 1200 will be described in detail.

  First, prior to data communication, initialization operations of the transmission device 1100 and the reception device 1200 are performed. Hereinafter, the initialization operation will be described with reference to FIGS. 2A and 3. 2A and 2B show an initialization sequence and a data flow of data communication, respectively, and FIG. 3 shows a signal pattern of the initialization sequence.

  First, in the period S1 in FIG. 2A, the initialization control unit 1109 of the transmission device 1100 sets the transmission header enable 1102 (the enable period thereof) to the second selector 1108 for a period until it is input a predetermined number of times (N times). The output of the clock signal generation unit 1106 is selected. The clock signal generator 1106 outputs a signal that alternately repeats the maximum signal level (+7) and the minimum signal level (−7), that is, a signal that toggles with the maximum amplitude, as in the clock signal shown in FIG. It is. The clock signal selected by the second selector 1108 is sent to the transmission line 1300 via the DAC 1110. Symbol timing recovery section 1207 of receiving apparatus 1200 recovers symbol timing 1206 using the clock signal received from the transmission path. For the reproduction of the symbol timing 1206, a phase comparison method using zero-cross detection is generally used. However, a certain period is required until the symbol timing 1206 is stabilized after the clock signal is input. Therefore, in order to secure a period necessary for the symbol timing 1206 to become stable, the number N of times that the initialization control unit 1109 counts the transmission header enable 1102 in S1 of FIG. 2A is set to a sufficient number. There is a need.

  When the initialization control unit 1109 of the transmission apparatus 1100 finishes counting the transmission header enable 1102 N times, in the period S2 in FIG. 2A, that is, the enable period of the transmission header enable 1102 (four symbol periods in the present embodiment). The second selector 1108 is made to select the output of the header initialization signal generator 1107. The header initialization signal generation unit 1107 repeats a plus-side minimum signal level (+1) and a minus-side maximum signal level (−1) alternately like the header initialization signal shown in FIG. A signal that toggles at the minimum amplitude is output. The header initialization signal selected by the second selector 1108 is sent to the transmission line 1300 via the DAC 1110. This header initialization signal is detected by the header detection unit 1208 of the reception device 1200. Various methods are conceivable as a method for distinguishing between the clock signal and the header initialization signal. Here, as an example, the header detection unit 1208 determines that the signal is the clock signal if the absolute value of the signal level is greater than 3, and the signal If the absolute value of the level is smaller than 3, it is determined that the header initialization signal. The header detection unit 1208 detects and holds the header start timing based on the received header initialization signal, and further counts the number of symbols in the header enable period (that is, the number of symbols in the header initialization signal). When the number of symbols in the header portion is predetermined between the transmission apparatus 1100 and the reception apparatus 1200 and is always fixed, the number of symbols in the header enable period may be omitted. The symbol timing reproduction unit 1207 continues to generate the symbol timing 1206 as in the period of S1.

  Subsequently, the initialization control unit 1109 of the transmission apparatus 1100 sends the clock signal generation unit to the second selector 1108 during the period S3 in FIG. 2A, that is, the disable period of the transmission header enable 1102 (252 symbol periods in this embodiment). The output of 1106 is selected. As a result, the clock signal is sent to the transmission line 1300 as in the period of S1. When detecting the clock signal, the header detection unit 1208 of the receiving device 1200 stops counting the number of symbols of the header initialization signal, and holds the count result (here, 4 symbols) as the length of the header enable period. Subsequently, the header detection unit 1208 counts the number of symbols in the header disable period (that is, the number of symbols of the clock signal). When the number of symbols in the data portion is predetermined between the transmission apparatus 1100 and the reception apparatus 1200 and is always fixed, the counting of the number of symbols in the header disable period may be omitted. The symbol timing reproduction unit 1207 continues to generate the symbol timing 1206 as in the period of S1.

  In the period of S4 in FIG. 2A, the initialization control unit 1109 of the transmission apparatus 1100 causes the second selector 1108 to select a header initialization signal in the same manner as in the period of S2, and this header initialization signal is sent to the transmission line 1300. Is done. When detecting the header initialization signal, the header detection unit 1208 of the receiving device 1200 stops counting the number of symbols of the clock signal, and holds the count result (here, 252 symbols) as the length of the header disable period. The symbol timing reproduction unit 1207 continues to generate the symbol timing 1206 as in the period of S1.

  In the period S5 in FIG. 2A, the initialization control unit 1109 of the transmission device 1100 causes the second selector 1108 to select a clock signal in the same manner as in the period S3, and this clock signal is sent to the transmission line 1300. The symbol timing reproduction unit 1207 of the receiving apparatus 1200 continues to generate the symbol timing 1206 as in the period of S1.

  When the period of S5 in FIG. 2A ends, the initialization sequence ends and data communication starts. During data communication, the initialization control unit 1109 of the transmission device 1100 causes the second selector 1108 to select the output of the first selector 1105. Hereinafter, operations of transmitting apparatus 1100 and receiving apparatus 1200 during data communication will be described with reference to FIG. 2B.

  In this embodiment, as shown in FIG. 2B, data communication is performed by repeating a data frame including a header part of 4 symbols and a data part (full value mapping data) of 252 symbols.

  First, the operation of transmitting apparatus 1100 will be described.

  In the header period (H 1 and H 2 in FIG. 2B), the transmission header enable 1102 is enabled, and in response to this, the first selector 1105 selects the output of the clock multiplex mapping unit 1104. Note that the clock multiplex mapping unit 1104 generates a signal as shown in FIG. 7 (hereinafter referred to as a clock multiplex mapping signal) based on the transmission data 1101. The detailed operation of the clock multiplex mapping unit 1104 will be described later. The clock multiplex mapping signal selected by the first selector 1105 is sent to the transmission line 1300 via the second selector 1108 and the DAC 1110 as a header portion.

  In the data period (D1 and D2 in FIG. 2B), the transmission header enable 1102 is disabled, and the first selector 1105 selects the output of the full value mapping unit 1103 in response to this. Note that the full value mapping unit 1103 generates a signal as shown in FIG. 5 (hereinafter referred to as a full value mapping signal) based on the transmission data 1101. The detailed operation of the all value mapping unit 1103 will be described later. The full value mapping signal selected by the first selector 1105 is sent as a data part to the transmission line 1300 via the second selector 1108 and the DAC 1110.

  Next, the operation of receiving apparatus 1200 will be described.

  The header detection unit 1208 outputs the reception header enable 1202 according to the header start timing held by itself. The enable period and the disable period of the reception header enable 1202 have the same length as the enable period detected in the period S2 in FIG. 2A and the disable period detected in the period S3, respectively. Accordingly, the header detection unit 1208 can output the reception header enable 1202 with the appropriate header timing and header length for the reception signal from the transmission path.

  The symbol timing recovery unit 1207 outputs the symbol timing 1206 while performing the update operation of the symbol timing based on the received signal only during the enable period of the reception header enable 1202 (that is, the reception period of the header part), and the disable period (that is, the data Is held by itself without performing the symbol timing update operation based on the received signal in a state in which the last input data inputted in the immediately preceding enable period and the timing of the symbol at that time are held. The symbol timing 1206 is output according to the current timing.

  In the header period (H 1 and H 2 in FIG. 2B), the reception header enable 1202 is enabled, and the third selector 1205 selects the output of the clock multiplex inverse mapping unit 1204 in response to this. The clock multiplex inverse mapping unit 1204 generates reception data 1201 based on the header portion of the received signal, that is, the clock multiplex mapping signal as shown in FIG. The detailed operation of the clock multiplex inverse mapping unit 1204 will be described later.

  In the data period (D1, D2 in FIG. 2B), the reception header enable 1202 is disabled, and the third selector 1205 selects the output of the full value inverse mapping unit 1203 in response to this. Note that the full value inverse mapping unit 1203 generates reception data 1201 based on the data part of the received signal, that is, the full value mapping signal as shown in FIG. The detailed operation of the all-value inverse mapping unit 1203 will be described later.

<Processing related to the data part>
Next, with reference to FIGS. 4 and 5, detailed operations of the full value mapping unit 1103 and the full value inverse mapping unit 1203 corresponding thereto will be described. FIG. 4 shows an 8-value full value mapping table, and FIG. 5 shows an example of a signal pattern in which all values are mapped according to the full value mapping table.

  Although not shown in the figure, the all value mapping unit 1103 has a function of holding the signal level of the symbol input to the DAC 1110 immediately before (hereinafter referred to as the previous signal level). Similarly, the all-value inverse mapping unit 1203 also has a function of holding the signal level (hereinafter referred to as the previous signal level) of the symbol input immediately before itself.

  As shown in FIG. 4, the signal level (hereinafter referred to as the current signal level) output from full value mapping section 1103 in transmission apparatus 1100 is determined according to the combination of the previous signal level and transmission data 1101 (3 bits). The More specifically, referring to FIG. 5, after the signal of the (n−1) -th symbol (signal level −7) is input to the DAC 1110, 3-bit data “001” is transmitted as transmission data 1101 to the full-value mapping unit 1103. When input, the previous signal level is −7 and the input data is “001”, so the current signal level is determined to be +5 from the all-value mapping table of FIG. 4, and the signal having the signal level of +5 is the nth signal. The full value mapping unit 1103 outputs the signal as a symbol signal. Similarly, for the (n + 1) th symbol, since the previous signal level is +5 and the input data is “101”, the current signal level is determined to be +3 from the full value mapping table of FIG. 4, and the signal level is +3. Is output from the full value mapping section 1103 as the signal of the (n + 1) th symbol.

  On the other hand, output data (3 bits) of full value inverse mapping section 1203 in receiving apparatus 1200 is determined according to the combination of the previous signal level and the current signal level. More specifically, with reference to FIG. 5, when the signal of the nth symbol (signal level +5) is input to the full value inverse mapping unit 1203, the previous signal level is −7 and the current signal level is +5. Therefore, the output data is determined as “001” from the all-value mapping table in FIG. 4, and the data “001” is output from the all-value inverse mapping unit 1203 as the n-th symbol data. Similarly, for the (n + 1) th symbol, since the previous signal level is +5 and the current signal level is +3, the output data is determined as “101” from the full value mapping table of FIG. Data “101” is output from the all-value inverse mapping section 1203.

<Processing related to header section>
Next, detailed operations of the clock multiplex mapping unit 1104, the corresponding clock multiplex inverse mapping unit 1204, and the symbol timing recovery unit 1207 will be described with reference to FIG. 6 and FIG. FIG. 6 shows an 8-level clock multiplex mapping table, and FIG. 7 shows an example of a signal pattern that is clock multiplex mapped in accordance with this clock multiplex mapping table.

  Although not shown, the clock multiplex mapping unit 1104 has a function of holding the signal level (previous signal level) of the symbol input immediately before to the DAC 1110. Similarly, the clock multiplexing inverse mapping unit 1204 also has a function of holding the signal level (previous signal level) of the symbol input immediately before itself.

  As shown in FIG. 6, the signal level (current signal level) output from the clock multiplex mapping unit 1104 in the transmission apparatus 1100 is the first and last symbols of the four symbols (symbols A to D) constituting the header unit. (Symbols A and D) are fixedly determined as -7 and +7, respectively. Other symbols (symbols B and D) are determined according to the combination of the previous signal level and transmission data 1101 (2 bits) according to the clock multiplex mapping table of FIG. The signal pattern mapped in accordance with the clock multiplex mapping table of FIG. 6 is a signal pattern in which plus and minus are alternately repeated in the symbol period. Therefore, the clock component can be extracted by passing the signal pattern thus obtained through an appropriate bandpass filter.

  When it is necessary to particularly distinguish data transmitted in the header part from data transmitted in the data part, the former will be referred to as header data and the latter will be referred to as full-value mapping data.

  The header part mapping method will be described more specifically with reference to FIG. First, when the transmission header enable 1102 is enabled, the clock multiplex mapping unit 1104 outputs a signal having a signal level of −7 (fixed) as a signal of the first symbol (symbol A) of the header unit. Subsequently, when 2-bit data “11” is input as header data to the clock multiplex mapping unit 1104, the previous signal level is −7 and the header data is “11”, so that the clock multiplex mapping table of FIG. The current signal level is determined to be +1, and a signal having a signal level of +1 is output from the clock multiplex mapping unit 1104 as the signal of the second symbol (symbol B) in the header portion. Similarly, for the third symbol (symbol C) in the header part, the previous signal level is +1 and the header data is “01”, so the current signal level is determined to be −5 from the clock multiplex mapping table of FIG. The signal having a signal level of −5 is output from the clock multiplex mapping unit 1104 as the signal of the third symbol in the header portion. Subsequently, the clock multiplex mapping unit 1104 outputs a signal having a signal level of +7 (fixed) as the signal of the last symbol (symbol D) in the header unit.

  When the reception header enable 1202 is enabled (that is, the reception period of the header portion), the symbol timing recovery unit 1207 of the reception device 1200 updates the symbol timing based on the input clock multiplexed header portion, 1206 is output. The symbol timing reproduction unit 1207 does not update the symbol timing during the period in which the data part is received, but updates the symbol timing only in the period in which the header part is received. Therefore, the symbol timing detection operation by the symbol timing reproduction unit 1207 is equivalent to the case where the detection of the symbol timing is continued based on the signal pattern in which the header part signal patterns sequentially input at a constant cycle are connected. The symbol timing can be appropriately reproduced from the header portion (clock multiplexed signal) that is input automatically. Since the symbol timing cannot be updated during the reception period of the data portion, the symbol timing 1206 output from the symbol timing reproduction unit 1207 may slightly deviate from the ideal timing. However, even if the symbol timing is deviated, the deviation is corrected during the reception period of the header portion, so that the deviation becomes large and communication does not fail.

  The output data (2 bits) of the clock multiplex inverse mapping unit 1204 is determined according to the combination of the previous signal level and the current signal level. More specifically, referring to FIG. 7, when the first symbol (symbol A) of the header part is input to the clock multiplex inverse mapping unit 1204, the previous signal level is -7, -5, -3, -1, Any one of +1, +3, +5, and +7 (+1 in the example of FIG. 7) and the current signal level is −7, and therefore the clock multiplex inverse mapping unit 1204 outputs undefined 2-bit data. Since the signal level of the symbol A is fixedly determined on the transmission side, the output data corresponding to the symbol A is meaningless data. Therefore, this data can be ignored in the external device on the receiving side that processes the received data 1201. When the second symbol (symbol B) of the header part is input to the clock multiplex inverse mapping unit 1204, the previous signal level is -7 and the current signal level is +1, so that the output data from the clock multiplex mapping table of FIG. Is determined to be “11”, and data “11” is output from the clock multiplex inverse mapping section 1204 as header data corresponding to the symbol B. Similarly, when the third symbol (symbol C) of the header part is input to the clock multiplex inverse mapping unit 1204, the previous signal level is +1 and the current signal level is -5, so the clock multiplex mapping table of FIG. Output data is determined as “01”, and data “01” is output from the clock multiplex inverse mapping unit 1204 as header data corresponding to the symbol C. When the last symbol (symbol D) of the header part is input to the clock multiplexing inverse mapping unit 1204, the previous signal level is any one of −7, −5, −3, and −1 (−5 in the example of FIG. 7). Thus, since the current signal level is +7, the clock multiplex inverse mapping unit 1204 outputs undefined 2-bit data. Since the signal level of the symbol D is also fixedly determined on the transmission side in the same way as the symbol A, the output data corresponding to the symbol D is also meaningless data. Therefore, this data can be ignored in the external device on the receiving side that processes the received data 1201.

  As described above, in the present embodiment, transmission of 3 bits per symbol (full value mapping data) is transmitted by adopting full value mapping in the data part, and clock multiplex mapping is adopted in the header part. Transmitting transmission data (header data) of 2 bits per symbol (excluding the first and last symbols of the header portion) while transmitting the clock component. Therefore, it is possible to achieve both stable clock reproduction on the receiving side and higher transmission speed. Further, since the clock component is multiplexed only in the header portion, radiation noise due to the clock component can be greatly reduced as compared with the conventional device of FIG. 9, and it is also suitable for use as an in-vehicle device.

  In this embodiment, as shown in FIGS. 6 and 4, a so-called differential mapping method is adopted in which the current signal level is determined in consideration of the previous signal level, but the present invention is not limited to this. . That is, a mapping method that determines the current signal level based only on transmission data regardless of the previous signal level may be employed. However, the use of the differential mapping method is advantageous in that data transmission without error is possible even if the reference voltage level of the signal level is different between the transmission side and the reception side.

  In the present embodiment, the header portion is composed of 4 symbols and the data portion is composed of 252 symbols, but the present invention is not limited to this. For example, the header part may be composed of 10 symbols. However, since the number of symbols in the header part and the data part affects the reproduction accuracy of the symbol timing, it should be set to an appropriate number in consideration of other various conditions.

  In this embodiment, data is transmitted from transmitting apparatus 1100 to receiving apparatus 1200. However, the present invention is not limited to this, and a plurality of transmitting / receiving apparatuses having both functions of transmitting apparatus 1100 and receiving apparatus 1200 are provided. It is also possible to prepare and perform data communication between these transmission / reception devices.

  In the present embodiment, as shown in FIG. 7, the signal levels of the first and last symbols of the header portion are fixed to −7 and +7, respectively. However, the present invention is not limited to this, and for these symbols, However, it is possible to superimpose header data. However, in this case, depending on the header data, there is a possibility that the signal pattern of the header portion takes only a signal level having a small absolute value such as −1 → + 1 → −1 → + 1. There is a possibility that the extraction accuracy of the clock component in 1207 is lowered. On the other hand, in this embodiment, since it is ensured that the signal having a signal level of −7, +7 is included in the header portion, the symbol timing recovery unit 1207 can always extract the clock component satisfactorily. In particular, when a plurality of header parts are connected, a large fluctuation in signal level (fluctuation from +7 to -7) always appears at each boundary part. Therefore, higher quality is achieved by using a header part with a smaller number of symbols. It is possible to reproduce the symbol timing.

  Further, in the present embodiment, the signal level of the first symbol in the header portion is set to a negative signal level, and the signal level of the last symbol is set to a positive signal level. The signal level of the first symbol may be a positive signal level (for example, +7), and the signal level of the last symbol may be a negative signal level (for example, -7). However, if the phase of the clock component (sine wave) multiplexed in two adjacent header portions via the data portion is shifted by 180 ° from each other, the symbol timing reproduction unit 1207 generates a clock from the signal obtained by joining the header portions. When extracting the components, there is a possibility that the clock components cannot be extracted well. From this point of view, the header part is configured such that when only the header part is cut out from the transmission signal and connected, the magnitude relationship of the signal level of each symbol with respect to the immediately preceding symbol changes alternately in the symbol period. Should.

  Further, in the present embodiment, the signal level of the first and last symbols of the header part is fixed as shown in FIG. 7, but the present invention is not limited to this. For example, the header part is composed of 10 symbols. The signal levels of the first three symbols in the header part are fixed to +7, -7, and +7, respectively, and the signal levels of the last three symbols are fixed to -7, +7, and -7, and the remaining four symbols You may make it determine the signal level of a symbol according to header data. Thereby, the reproduction accuracy of the symbol timing can be further improved.

  The transmission device, the reception device, and the transmission system according to the present invention are particularly useful for applications that constitute a LAN or the like provided in a vehicle or an aircraft that has a strict limitation on radiation noise and requires a broadband transmission performance.

The block diagram which shows the structure of the transmitter which concerns on one Embodiment of this invention, and a receiver Initialization sequence data flow Data flow of data communication Signal pattern during initialization sequence Example of 8-value full value mapping table applied to data part Example of signal pattern based on 8-value full value mapping table Example of 8-level clock multiplex mapping table applied to header section Example of signal pattern based on 8-level clock multiplex mapping table Example of signal pattern in conventional transmission system of FIG. Block diagram showing the configuration of a conventional transmission system Example of noise generated in a conventional transmission system

Explanation of symbols

1100 Transmission Device 1101 Transmission Data 1102 Transmission Header Enable 1103 Full Value Mapping Unit 1104 Clock Multiplexing Mapping Unit 1105 First Selector 1106 Clock Signal Generation Unit 1107 Header Initialization Signal Generation Unit 1108 Second Selector 1109 Initialization Control Unit 1110 DAC
1300 Transmission path 1200 Receiver 1201 Received data 1202 Receive header enable 1203 All value inverse mapping unit 1204 Clock multiple inverse mapping unit 1205 Third selector 1206 Symbol timing 1207 Symbol timing recovery unit 1208 Header detection unit 1210 ADC

Claims (11)

All-value mapping is performed by sequentially mapping N-bit transmission data, which is a predetermined number of bits, to a predetermined signal level among M signal levels, which is a predetermined number, for each predetermined symbol period. A full value mapping means for generating a signal;
By sequentially mapping N-1 bits of transmission data to one of the signal levels of the upper half and the signal level of the lower half of the M signal levels at regular symbol periods. Clock multiplex mapping means for generating a clock multiplex mapping signal in which clock components are multiplexed;
A transmission apparatus comprising: first selection means for alternately selecting the full value mapping signal and the clock multiplex mapping signal at a predetermined timing based on a transmission header enable signal and outputting the selected signal as a first transmission signal. Clock signal generating means for generating a clock signal that toggles with a maximum amplitude at the M signal levels for each fixed symbol period;
Header initialization signal generating means for generating a header initialization signal that toggles with a minimum amplitude at the M signal levels for each constant symbol period;
Initialization control means for generating an initialization control signal based on the transmission header enable signal;
The transmission according to claim 1, further comprising second selection means for selecting the first transmission signal, the clock signal, and the header initialization signal based on the initialization control signal and outputting the selected signal as a second transmission signal. apparatus.   The second selection means alternately outputs the clock signal and the header initialization signal at a predetermined timing based on the transmission header enable signal prior to the output of the first transmission signal. The transmission device according to claim 2.   The clock multiplex mapping means is configured such that when only the clock multiplex mapping signal is cut out from the first transmission signal and connected, the magnitude relationship of the signal level of each symbol with respect to the immediately preceding symbol changes alternately in the symbol period. The transmission apparatus according to claim 1, wherein a clock multiplex mapping signal is generated.   5. The clock multiplex mapping means generates a clock multiplex mapping signal having a fixed signal level in at least the first and last symbols of symbols constituting each clock multiplex mapping signal. The transmitting device described.   The clock multiplex mapping means is a clock multiplex mapping signal that has a maximum or minimum signal level of the M signal levels in at least the first and last symbols of the symbols constituting each clock multiplex mapping signal. The transmission apparatus according to claim 5, wherein: A receiving device for receiving a signal having the same configuration as the signal output from the transmitting device according to claim 1,
Header detection means for detecting a reception timing of the clock multiplex mapping signal from a reception signal and generating a reception header enable signal indicating the detection result;
Based on the received header enable signal, when receiving the clock multiplex mapping signal, it generates symbol timing by detecting the timing of the symbol from the received signal, and when receiving the full value mapping signal, Symbol timing recovery means for generating symbol timing using the timing of the symbol detected when the clock multiplex mapping signal was last received;
Full-value inverse mapping means for inversely mapping the signal level of each symbol of the received full-value mapping signal based on the symbol timing generated by the symbol timing reproduction means to sequentially generate N-bit received data;
Clock multiplexing inverse mapping means for inversely mapping the signal level of each symbol of the received clock multiplexed mapping signal based on the symbol timing generated by the symbol timing recovery means to sequentially generate N-1 bit received data; ,
A receiving apparatus comprising: third selecting means for selecting and outputting the N-bit received data and the N-1 bit received data according to the received header enable signal. A receiving device for receiving a signal having the same configuration as the signal output from the transmitting device according to claim 2,
Header detection means for detecting a reception timing of the clock multiplex mapping signal from a reception signal and generating a reception header enable signal indicating the detection result;
Based on the received header enable signal, when receiving the clock multiplex mapping signal, it generates symbol timing by detecting the timing of the symbol from the received signal, and when receiving the full value mapping signal, Symbol timing recovery means for generating symbol timing using the timing of the symbol detected when the clock multiplex mapping signal was last received;
Full-value inverse mapping means for inversely mapping the signal level of each symbol of the received full-value mapping signal based on the symbol timing generated by the symbol timing reproduction means to sequentially generate N-bit received data;
Clock multiplexing inverse mapping means for inversely mapping the signal level of each symbol of the received clock multiplexed mapping signal based on the symbol timing generated by the symbol timing recovery means to sequentially generate N-1 bit received data; ,
Third selection means for selecting and outputting the N-bit received data and the N-1 bit received data according to the received header enable signal;
The header detection means detects the clock signal and the initialization signal from the received signal, and holds the detected timing signal reception timing and reception period and the detected clock signal reception period. A receiving apparatus for detecting a reception timing of the clock multiplex mapping signal sequentially received after receiving the initialization signal and the clock signal.   8. A transmission system comprising: the transmission apparatus according to claim 1; a transmission path for transmitting a signal output from the transmission apparatus; and the reception apparatus according to claim 7 connected to the transmission apparatus via the transmission path. .   9. A transmission system comprising: the transmission device according to claim 2; a transmission path for transmitting a signal output from the transmission device; and the reception device according to claim 8 connected to the transmission device via the transmission path. . A vehicle comprising the transmission system according to claim 9 or 10.

Images