JP2006128149A - Heterojunction semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce or eliminate a difference in height of electrode positions in a stacking direction, suppress an increase in manufacturing steps and a decrease in productivity, and have a structure that does not cause deterioration of electrical characteristics. And a method of manufacturing the same.
A sub-collector constituting material layer, a collector constituting material layer, a base constituting material layer, an emitter constituting material layer, and an emitter cap constituting material layer are formed on a semi-insulating substrate by epitaxial growth. To do. Next, an n ⁺ type conductive region 21 is formed by ion implantation. Thereafter, the emitter cap constituent material layer 6, the emitter constituent material layer 5, the base constituent material layer 4 and the collector constituent material layer 3 are patterned into a mesa structure to form an active layer, and the emitter electrode 9 is in contact with the emitter cap layer 16. The base electrode 8 is provided in contact with the base layer 14, and the collector electrode 7 is provided on the emitter cap constituent material layer 6 of the constituent material layer other than the active layer.
[Selection] Figure 1

Description

  The present invention relates to a heterojunction semiconductor device and a manufacturing method thereof, and more particularly to an electrode structure thereof.

  In recent years, demands for higher speed and higher integration of semiconductor devices have become stronger, and expectations for heterojunction bipolar transistors (HBTs) made of Group 3-5 compound semiconductors have also increased.

  In the manufacture of HBT, for example, a sub-collector layer, a collector, etc. are typically formed on a gallium arsenide GaAs substrate or an indium phosphide InP substrate using molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD) or the like. A layer, a base layer, and an emitter layer are epitaxially grown sequentially, and this stacked body is further processed to produce an HBT.

  As described above, since the HBT has a vertical structure in which each semiconductor layer is stacked on the substrate, when an electrode is formed in contact with the semiconductor layer, at least an upper portion of the electrode formation position of the lower layer is an upper portion. It is not possible to provide a layer. Therefore, for example, as shown in Patent Document 1 to be described later, after each semiconductor layer is formed once, a part of the upper layer is removed by photolithography and wet etching or dry etching, and the above laminate is obtained. It is often patterned into a mesa structure having a stepped cross section.

  FIG. 14 is a cross-sectional view for explaining the problems of a conventional heterojunction bipolar transistor (HBT) 100 made of a laminate having a mesa structure. In order to manufacture the HBT 100, the subcollector layer 102, the collector layer 103, the base layer 104, the emitter layer 105, and the emitter cap layer 106 are formed on the semi-insulating substrate 101 by an epitaxial growth method using MBE method or MOCVD method. Sequentially formed.

  Then, after patterning the stacked body into a mesa structure having a stepped cross section by photolithography and etching, a collector electrode 107 is provided in contact with the subcollector layer 102, a base electrode 108 is provided in contact with the base layer 104, and an emitter An emitter electrode 109 is provided in contact with the cap layer 106. As the electrode material, a material capable of forming an ohmic contact with each semiconductor layer is used.

  Further, an interlayer insulating film 110 is formed on the surface of the HBT 100 so that the entire surface is flat by applying an organic film typified by polyimide or benzocyclobutene (BCB). Formed wiring. As a material of the interlayer insulating film 110, a so-called low k material having a low dielectric constant is preferable in order to reduce parasitic capacitance. The electrodes 107 to 109 and the wiring electrodes 114 to 116 on the semiconductor layer are connected through through holes 117 to 119 opened in the interlayer insulating film 110, respectively.

  The problem with the HBT 100 is that the collector layer 103 is usually very thick in order to ensure the withstand voltage performance of the semiconductor device. For example, the thickness of each layer is 50 nm for the emitter cap layer 106, 125 nm for the emitter layer 105, and 75 nm for the base layer 104, while the collector layer 103 is 500 nm and the subcollector layer 102 is 300 nm. For this reason, when the electrodes 107 to 109 are provided as described above, the height difference in the electrode position in the stacking direction is as small as 175 nm between the base electrode 108 and the emitter electrode 109, but is 750 nm between the collector electrode 107 and the emitter electrode 109. Also become.

  As in the above example, in the HBT 100, it is not uncommon for the height difference between the collector electrode 107 and the emitter electrode 109 to be about 1 μm. In a semiconductor device that is required to be miniaturized, if there is a step of about 1 μm or more between the upper part of the collector electrode and the upper part of the emitter electrode, a serious difficulty occurs in a processing process such as a wiring process.

  For example, when forming wiring via the interlayer insulating film 110, it is necessary to form through holes 117h to 119h by dry etching in the interlayer insulating film 110 at positions where the connection plugs 117 to 119 to the electrodes 107 to 109 are formed. However, if the above-described height difference exists, it is very difficult to form an appropriate through hole.

  That is, since the film thickness of the interlayer insulating film 110 to be opened differs greatly between the through hole 117h and the through holes 119h and 118h corresponding to the height difference between the collector electrode 107, the emitter electrode 109, and the base electrode 108, for example, etching When the condition is adapted to the through hole 117h, the through holes 119h and 118h are excessively etched. As a result, not only does the hole diameter vary, but problems such as abnormal etching and deposits of etching by-products occur.

  FIG. 15 is a cross-sectional view for explaining a problem in forming through holes having greatly different depths in the interlayer insulating film 110 above the HBT 100. FIG. 15 is a partially enlarged cross-sectional view of a region indicated by a dotted line in FIG. 14 and shows a state before the wiring electrodes 114 to 116 and the connection plugs 117 to 119 are formed.

The depths of the through holes 117h, 118h, and 119h are h ₁₁ , h ₁₂ , and h ₁₃ respectively, and the difference between h ₁₁ and h ₁₃ is Δh. When the through holes 117h and 119h are collectively formed, in order to complete the through hole 117h, it is necessary to form a hole having a depth of Δh even after the through hole 119h is completed. While the hole having a depth of Δh is formed downward on the through hole 117h side, the etching on the through hole 119h side is prevented by the emitter electrode 109 from being etched downward. Advances laterally. For this reason, as indicated by the dotted line in the figure, the hole diameter is increased below the through hole 119. If a high etching rate is selected to form deep through holes, the film material from which the interlayer insulating film 110 has been etched off is likely to adhere to the side surfaces of the resist mask over the through holes 117h to 119h.

  The relationship between the etching rate in the downward direction in the through hole 117h and the etching rate in the lateral direction in the through hole 119h depends on the etching method. When plasma etching, which is isotropic etching by radical reaction, is used, the speeds of both may be considered to be substantially the same. In this case, the size of the main surface of the emitter electrode 109 is normally formed with a margin on one side w in consideration of the alignment error with the through hole 119h. However, if Δh> w holds, When the hole 117h is completed, the lower portion of the through hole 119h protrudes from the main surface of the emitter electrode 109 and expands, which is inconvenient. In order not to cause such inconvenience, it is necessary that Δh <w, and considering that w is about 500 nm, Δh needs to be 500 nm or less. Although the relationship between the through holes 117h and 119h has been described here, the relationship between the through holes 117h and 118h is substantially the same.

  Note that when reactive ion etching (RIE), which is anisotropic etching by ion assist, is used, verticality, which is etching in the downward direction of the substrate, becomes high, and side etching hardly occurs. However, in this case, since etching proceeds by applying an impact with ions, the underlying layer may be damaged. Since HBT such as HBT100 uses gold as an electrode material, if RIE is used to form the through holes 117h to 119h, the gold of the electrode bombarded with ions reattaches to the side surfaces of the through holes 117h to 119h. There is a high possibility that etching will occur. In this respect, it is preferable to use isotropic etching by plasma etching rather than anisotropic etching by RIE for forming the through holes 117h to 119h.

  The above problem can be avoided if through holes having greatly different depths are formed in a separate process. However, in this case, the number of processes increases and productivity decreases.

  14 and 15, the interlayer insulating film 110 cannot absorb a large step between the electrodes 107 to 109 of the HBT 100, and the actual shape of the interlayer insulating film surface 112 is an ideal interlayer insulating film. The film surface 111 deviates from a completely flat surface and has a shape with large irregularities. For this reason, there is a high possibility that the wiring formed on the interlayer insulating film surface 112 is disconnected, and the exposure accuracy of the photoresist formed on the interlayer insulating film surface 112 in the wiring process is lowered, and the wiring according to a predetermined pattern is provided. The problem that cannot be formed occurs.

  Therefore, Patent Documents 2 to 4 to be described later propose an HBT having a structure in which the electrode formation position in the stacking direction (height direction) is changed to reduce or eliminate the height difference of the electrode position.

FIG. 16 is a cross-sectional view of the HBT 120 disclosed in Patent Document 2. As shown in FIG. In the HBT 120, an n ⁺ -type gallium arsenide layer (collector extraction layer) 122, an n-type gallium arsenide layer (collector layer) 123, and an n ⁺ -type gallium arsenide layer (base layer) 124 are formed on a semi-insulating gallium arsenide substrate 121. The n-type aluminum gallium arsenide layer (emitter layer) 125 and the n ⁺ -type gallium arsenide layer (emitter cap layer) 126 are sequentially formed by the epitaxial growth method using the MBE method or the MOCVD method.

Base electrode 128 and emitter electrode 129 are provided in contact with n ⁺ -type gallium arsenide layer (base layer) 124 and n ⁺ -type gallium arsenide layer (emitter cap layer) 126, respectively, as in HBT 100 shown in FIG. However, the formation position of the collector electrode 127 in the film thickness direction is changed. That is, after the n ⁺ -type GaAs layer (collector lead layer) 122 is exposed by etching at the position where the collector electrode 127 is formed in the surface direction of the substrate 121, n is formed on this exposed surface by an epitaxial growth method using the MBE method. ^{A +} type GaAs layer (second lead layer) 132 is formed, and a collector electrode 127 is provided thereon in contact with the newly added second lead layer 132. The thickness (height) of the second lead layer 132 is not particularly limited. For example, the thickness is set such that the upper surface is as high as the n ⁺ -type GaAs layer (base layer) 124.

In the HBT 120, although the height difference in the electrode position in the stacking direction between the collector electrode 127, the base electrode 128, and the emitter electrode 129 can be reduced or eliminated, a method of additionally forming the second extraction layer 132 is employed. Therefore, there is a problem that the number of processes increases. There is also a concern that the second extraction layer 132 having desired electrical characteristics can be epitaxially grown on the exposed surface of the n ⁺ -type GaAs layer (collector extraction layer) 122 formed by etching.

  FIG. 17 is a cross-sectional view of the HBT 140 disclosed in Patent Document 3. As shown in FIG. In the HBT 140, a sub-collector region 142 and a collector region 143 are formed on a semi-insulating substrate 141 by an ion implantation method and an epitaxial growth method, respectively, and then ion implantation is performed at the formation position of the collector electrode 147 in the surface direction of the substrate 141. The conductive region 150 having the same conductivity type as the collector region 143 and reaching the sub-collector region 142 is formed.

  After that, the base layer 144 and the emitter layer 145 are formed by epitaxial growth, a part of the emitter layer 145 is removed by etching, and the base electrode 148 and the emitter electrode 149 are provided in contact with the base layer 144 and the emitter layer 145, respectively. . Then, a part of the base layer 144 is removed by etching, and the collector electrode 147 is provided in contact with the conductive region 150. Thereafter, an insulating region 151 is formed by ion implantation, and elements are separated.

  In the HBT 140, the collector region 143 is not removed, and the collector electrode 147 is provided on the conductive region 150 obtained by modifying the collector region 143. Therefore, the electrode positions of the collector electrode 147, the base electrode 148, and the emitter electrode 149 in the stacking direction The height difference is only the thickness of the base layer 144 and the combined thickness of the base layer 144 and the emitter layer 145, and is significantly reduced. However, since the film-forming process by the epitaxial growth method is interrupted by the ion implantation process, there is a problem in that the process is not continuous and complicated and productivity is lowered. In addition, there is a concern that the base layer 144 and the emitter layer 145 may not be formed with a predetermined quality after the film formation process is resumed due to the deterioration or contamination of the surface of the epitaxial growth layer that occurs during the interruption.

  Further, since collector region 143 and conductive region 150 are in direct contact, the presence of current flowing from collector region 143 to conductive region 150 without passing through subcollector region 142 adversely affects the electrical characteristics of HBT 140 such as withstand voltage. There is also concern about the possibility of giving

FIG. 18 is a cross-sectional view of the HBT 160 disclosed in Patent Document 4. As shown in FIG. In the HBT 160, after the n ⁺ -type GaAs layer (subcollector layer) 162 and the n-type GaAs layer (collector layer) 164 are formed on the GaAs semiconductor substrate 161 by the MOCVD method, the collector electrode 173 is formed in the surface direction of the substrate 161. Si ⁺ ion implantation is performed to form a deep n ⁺ layer 165 having the same conductivity type as the collector layer 164 and reaching the subcollector layer 162.

Thereafter, a p ⁺ -type AlGaAs layer (base layer) 167 is formed on the collector layer 164 with a thin grading layer sandwiched by epitaxial growth using MBE, and patterned by selective etching. Further, an n-type AlGaAs layer (emitter layer) 168 and an n ⁺ -type GaAs layer (emitter cap layer) 169 are formed thereon by epitaxial growth using MBE, with a thin grading layer interposed therebetween. Next, Si ⁺ ion implantation is performed at the formation position of the collector electrode 167 in the surface direction of the substrate 161 to change the conductivity of the emitter layer 168 and the emitter cap layer 169, thereby extending the deep n ⁺ layer 165. Further, Be ⁺ ion implantation is performed to change the conductivity types of the emitter layer 168 and the emitter cap layer 169, and the p ⁺ layer 170 reaching the base layer 167 is formed.

Thereafter, Be ⁺ and H ⁺ ions are implanted to form an isolation layer 171, and a silicon nitride layer 172 and ohmic electrodes 173 to 175 are formed.

In the HBT 160, the deep n ⁺ layer 165 and the p ⁺ layer 170 are formed up to the top of the emitter cap layer 169 by the ion implantation method, and the ohmic electrodes 173 and 174 are formed thereon, so there is no need to form a through hole. All the ohmic electrodes 173 to 175 have the same height. Further, since the mesa structure is not formed and the emitter cap layer 169 is left flat on the top, it is easy to form the wiring after manufacturing the HBT 160.

  However, like the HBT 140 based on Patent Document 3, since the film forming process is interrupted by the ion implantation process, there is a problem in that the process is not continuous and complicated and the productivity is lowered. Further, there is a concern that the base layer 167, the emitter layer 168, and the emitter cap layer 169 may not be formed with a predetermined quality after the film formation process is resumed due to the change in the surface of the epitaxial growth layer or contamination caused during the interruption. Is also present.

Further, since the emitter cap layer 169 and the emitter layer 168 and the p ⁺ layer 170 are in direct contact, the presence of current flowing from the emitter cap layer 169 and the emitter layer 168 to the p ⁺ layer 170 without passing through the base layer 167 There is also concern that the electrical characteristics of the HBT 160 may be adversely affected, such as a decrease in amplification factor. In addition, since the deep n ⁺ layer 165 has a lower layer and an upper layer formed by two separate ion implantations, there is a risk that characteristics such as conductivity may be deteriorated due to the influence of the positional deviation between the two. is there.

JP-A-6-333935 (page 3, FIG. 2) JP-A-61-59774 (2nd and 3rd pages, FIG. 1) JP-A-5-129322 (2nd and 3rd pages, FIG. 1) JP-A-5-275634 (pages 3 and 4, FIG. 1)

  The present invention has been made in view of such a situation, and its purpose is to alleviate or eliminate the height difference of the electrode position in the stacking direction, and to suppress an increase in the manufacturing process and a decrease in productivity, Another object of the present invention is to provide a heterojunction semiconductor device having a structure that does not cause deterioration of electrical characteristics, and a method for manufacturing the same.

That is, the present invention provides a heterojunction semiconductor device in which a subcollector layer, a collector layer, a base layer, and an emitter layer are laminated on a substrate in this order.
By processing the laminated body composed of the constituent material layers that become the sub-collector layer, the collector layer, the base layer, and the emitter layer, another constituent material layer is left on the sub-collector layer,
A collector electrode is provided on and in contact with the remaining component material layer,
The present invention relates to a heterojunction semiconductor device, characterized in that a conductive region for electrically connecting the collector electrode and the subcollector layer is provided, and a method for manufacturing the heterojunction semiconductor device,
Laminating a sub-collector constituent material layer, a collector constituent material layer, a base constituent material layer, and an emitter constituent material layer in this order on the substrate;
Processing this laminate, leaving the other constituent material layer above the subcollector constituent material layer at the collector electrode formation position in the surface direction of the base;
Forming the collector electrode thereon in contact with the remaining component material layer;
The present invention relates to a method for manufacturing a heterojunction semiconductor device, including a step of forming a conductive region that electrically connects the collector electrode and the subcollector constituent material layer.

  In the heterojunction semiconductor device of the present invention, other than the active layer, by processing the stacked body in which at least the constituent material layers to be the subcollector layer, the collector layer, the base layer, and the emitter layer are stacked in this order. A constituent material layer is left on the subcollector layer, and the collector electrode is provided on and in contact with the constituent material layer. For this reason, the height difference in the electrode position in the stacking direction between the collector electrode and the emitter electrode and the base electrode provided on and in contact with the active layer other than the sub-collector layer above the sub-collector layer is: This is smaller than the conventional mesa structure example (see FIG. 14) in which the collector electrode is provided on and in contact with the subcollector constituent material layer.

  At this time, since the collector electrode is provided by using the already formed constituent material layer, the process is simplified as compared with the method of Patent Document 2 in which the second extraction layer 132 is additionally formed. Patents in which the film formation process is interrupted by the ion implantation process because all the constituent material layers necessary for forming the semiconductor device are formed at once, and then the laminated body is processed. Compared with the methods of Documents 3 and 4, the continuity of the process is maintained, the efficiency is good, and the production can be performed with a simple process and high productivity. Further, there is no alteration or contamination of the surface of the epitaxial growth layer due to interruption of the film formation process, the constituent material layer formed under the best conditions can be the active layer without deterioration, and the film quality of the active layer And the performance of the heterojunction semiconductor device is improved.

  As described above, the heterojunction semiconductor device of the present invention suppresses an increase in the manufacturing process and alleviates or eliminates the height difference of the electrode position in the stacking direction without causing a decrease in productivity and a deterioration in electrical characteristics. Can do. As a result, when an interlayer insulating film is formed on the heterojunction semiconductor device and a wiring is formed on the surface of the interlayer insulating film, it is formed on the interlayer insulating film for electrical connection between the electrode and the wiring. The depth of the through hole is well aligned. For this reason, all the through holes can be easily formed with high accuracy and the productivity is improved by reducing the number of processes. In addition, since a relatively shallow through hole only needs to be formed, an appropriate etching rate can be selected, and the film material with the interlayer insulating film etched off is prevented from adhering to the side surface of the resist mask above the through hole. it can.

  Further, since the flatness of the surface of the interlayer insulating film is improved, the possibility of disconnection of the wiring is reduced, the wiring forming process can be easily performed with high productivity, and the exposure accuracy of the photoresist in the wiring process and the wiring material layer can be improved. Etching accuracy is improved, and wiring according to a predetermined pattern can be formed on the surface of the interlayer insulating film. In this way, problems in the wiring formation process, such as wiring disconnection at steps and variations in exposure and etching, can be collectively solved, enabling further element miniaturization and reducing parasitic capacitance. It is possible to increase the gain of the power amplifier device by increasing the usable frequency band due to the above, and improving the contact failure.

  The method of manufacturing a heterojunction semiconductor device according to the present invention is a method of manufacturing a heterojunction semiconductor device that is in a front-to-back relationship with the heterojunction semiconductor device and enables the heterojunction semiconductor device to be manufactured efficiently.

  In the present invention, the collector electrode may be provided on and in contact with the emitter constituent material layer, the emitter cap constituent material layer, or the base constituent material layer. Alternatively, the collector electrode may be provided on and in contact with the collector constituent material layer.

  Further, the conductive region is formed by changing the region of the constituent material layer between the collector electrode and the subcollector layer into a highly conductive region of the same conductivity type as the subcollector layer, It is preferable that the highly conductive region reaches the subcollector layer.

  The method for forming the conductive region is not particularly limited and may be any method that can be applied to the heterojunction semiconductor device. However, since the number of steps is small and the adverse effect on the semiconductor layer is small, The injection method is most preferred. Further, according to the ion implantation method, the impurity concentration distribution in the depth direction can be controlled by adjusting the implantation energy, and the impurity concentration can be controlled by adjusting the dose amount. A conductive region 21 having the following electrical characteristics can be formed. Other methods for introducing impurities include an impurity diffusion method and the like, which can be used alone or in combination with an ion implantation method.

  The collector electrode and the conductive region are electrically connected to the collector layer only through the subcollector layer, and the conductive region and the collector layer and the base layer are insulated and separated. It is good to have. In this case, it is possible to eliminate the possibility that a current that flows from the collector layer to the conductive region without passing through the subcollector layer is generated, which adversely affects the electrical characteristics of the heterojunction semiconductor device.

  As a material for the electrode, a material that can form ohmic contact with the semiconductor layer in contact with the electrode is preferably used. The collector electrode has a three-layer structure of Ti / Pt / Au in which titanium, platinum and gold are laminated in this order, or platinum or palladium, titanium, platinum and gold are laminated in this order (Pt or Pd) / Ti. It is preferable to have a four-layer structure of / Pt / Au. With such a stacked structure, adhesion to the underlying semiconductor layer and ohmic contact can be realized.

  In the emitter electrode and / or the base electrode, when the conductive region is formed and the activation annealing process is performed after the electrode is formed, the electrode material needs to withstand the annealing process temperature, and therefore corresponds to the annealing temperature. The high melting point metal material, specifically, tungsten W or molybdenum Mo is preferable.

  The base is preferably made of a compound semiconductor, and more specifically, the base is preferably made of indium phosphide InP or gallium arsenide GaAs. Indium phosphide or gallium arsenide is a typical substrate material suitably used for a Group 3-5 compound semiconductor.

  In this case, the constituent material layer is preferably configured as a heterojunction bipolar transistor made of a compound semiconductor. At this time, the heterojunction bipolar transistor is preferably an NPN type. The NPN type has a structure excellent in high-speed operation. However, it is not limited to the NPN type, and the PNP type is preferable if importance is attached to the magnitude of the amplification factor.

  However, the function of the heterojunction semiconductor device of the present invention is not limited to the transistor. For example, even if the constituent elements are the same as those of the bipolar transistor, the function as a diode or the function as a simple resistor or capacitor is possible. It may be used.

  In the method of manufacturing a heterojunction semiconductor device according to the present invention, when the conductive region is formed through at least the base constituent material layer and the collector constituent material layer by the ion implantation, the impurity concentration of the first conductivity type of the conductive region is set. It is preferable that the impurity concentration of the second conductivity type of the base constituent material layer is at least equal to or higher.

As a specific processing order in this case, when the collector electrode is provided on the emitter cap constituent material layer,
First, the laminated body in which a sub-collector constituent material layer, a collector constituent material layer, a base constituent material layer, an emitter constituent material layer, and an emitter cap constituent material layer are laminated in this order on the base is formed.
Next, at the formation position of the collector electrode in the surface direction of the base, the ion implantation is performed from the surface of the emitter cap constituent material layer to the stacked body, and the emitter cap constituent material layer, the emitter constituent material layer, Forming the conductive region reaching the sub-collector constituent material layer in the base constituent material layer and the collector constituent material layer;
Next, in contact with the emitter cap constituent material layer, the collector electrode is formed thereon,
Next, the emitter cap constituent material layer, the emitter constituent material layer, the base constituent material layer, the collector constituent material layer, and the subcollector constituent material layer are selectively removed to form the emitter cap layer, the emitter layer Forming the base layer, the collector layer and the sub-collector layer;
It is good.

Further, when providing the collector electrode on the base constituent material layer,
First, the laminated body in which a sub-collector constituent material layer, a collector constituent material layer, a base constituent material layer, an emitter constituent material layer, and an emitter cap constituent material layer are laminated in this order on the base is formed.
Next, the emitter cap constituent material layer and the emitter constituent material layer are selectively removed to form the emitter cap layer and the emitter layer,
Next, at the position where the collector electrode is formed in the surface direction of the base, the ion implantation is performed from the surface of the base constituent material layer to the stacked body, and the base constituent material layer and the collector constituent material layer are subjected to the sub Forming the conductive region reaching the collector constituent material layer,
Next, the collector electrode is formed on and in contact with the base constituent material layer,
Next, the base constituent material layer, the collector constituent material layer, and the sub-collector constituent material layer are selectively removed to form the base layer, the collector layer, and the sub-collector layer.
It is good.

In addition, when the conductive region is formed through the collector constituent material layer in which the base constituent material layer does not exist on the upper surface by the ion implantation, the impurity concentration of the conductive region is set to 1 × 10 ¹⁹ / cm ³ or more. Good.

As a specific processing order in this case,
Forming the laminated body in which a sub-collector constituent material layer, a collector constituent material layer, a base constituent material layer, an emitter constituent material layer, and an emitter cap constituent material layer are laminated in this order on the substrate;
Next, the emitter cap constituent material layer, the emitter constituent material layer, and the base constituent material layer are selectively removed to form the emitter cap layer, the emitter layer, and the base layer,
Next, at the formation position of the collector electrode in the surface direction of the substrate, the ion implantation is performed from the surface of the collector constituting material layer to the stacked body, and the collector constituting material layer is extended to the subcollector constituting material layer. Forming said conductive region to reach,
Next, the collector electrode is formed on and in contact with the collector constituent material layer,
Next, the collector constituent material layer and the subcollector constituent material layer are selectively removed to form the collector layer and the subcollector layer.
It is good.

  In this case, before the ion implantation, the collector constituent material layer is selectively removed to reduce the thickness of the collector constituent material layer at the collector electrode formation position in the surface direction of the base. Good.

  Next, a preferred embodiment of the present invention will be described specifically and in detail with reference to the drawings.

Embodiment 1
In the first embodiment, an InP heterojunction bipolar is mainly used as an example of a method for manufacturing a heterojunction semiconductor device according to claims 1 and 2 and a heterojunction semiconductor device according to claims 19, 20, 27 and 28. A transistor and a manufacturing method thereof will be described.

  FIG. 1 is a cross-sectional view (a) showing the structure of a heterojunction bipolar transistor (HBT) 10 based on the first embodiment and a cross-sectional view (b) for explaining the necessity of electrode arrangement.

  In the HBT 10, a subcollector layer 12, a collector layer 13, a base layer 14, an emitter layer 15, and an emitter cap layer 16 are sequentially stacked on the semi-insulating substrate 1 by epitaxial growth using MBE or MOCVD. Is formed.

  Similarly to the HBT 100 shown in FIG. 14, the emitter cap layer 16 and the emitter layer 15 are patterned into a mesa structure, the emitter electrode 9 is provided in contact with the emitter cap layer 16, and the base electrode 8 is in contact with the base layer 14. Is provided. Here, when the collector electrode 7 is provided in contact with the sub-collector layer 12, a large difference in height occurs between the collector electrode 7, the base electrode 8, and the emitter electrode 9, as in the HBT 100. Therefore, it is necessary to provide the collector electrode 7 in a layer above the subcollector layer 12 as a structure that does not cause a large height difference between the electrodes.

  In the present embodiment, the collector electrode 7 is provided on the emitter cap constituent material layer 6 as one of the structures satisfying the above-described requirements (Note that, as shown in the second to fourth embodiments described later). The collector electrode 7 may be provided on the base constituent material layer 4 or the collector constituent material layer 3). As a result, the electrode arrangement structure shown in FIG. However, in the state of FIG. 1B, since the electrical connection between the collector electrode 7 and the subcollector layer 12 cannot be obtained, it does not operate as a transistor. Therefore, as shown in FIG. 1A, a conductive region 21 that electrically connects the collector electrode 7 and the subcollector layer 12 is formed.

  The formation method of the conductive region 21 is not particularly limited and may be any method that can be applied to the HBT. However, since the number of steps is small and the adverse effect on the active layers 12 to 16 is small, the ion implantation method is used. Is most preferred. In the present embodiment, it is assumed that the conductive region 21 reaching the subcollector layer 12 from the emitter cap constituent material layer 6 below the electrode 7 is formed by ion implantation before the collector electrode 7 is formed. The conductive region 21 is a semiconductor layer having the same conductivity type as that of the subcollector layer 12 and having a high impurity concentration. After the formation of the conductive region 21, the collector electrode 7 is formed.

  FIG. 2 is a cross-sectional view showing a state in which an interlayer insulating film 23 is formed on the HBT 10 so that the entire surface is flattened by a method such as applying an organic film. FIG. 2 is an enlarged cross-sectional view in a state where through holes 27 to 29 are formed in a region indicated by a dotted line in FIG. 1A, and should be compared with FIG.

  As a material for the interlayer insulating film 23, a so-called low-k material having a low dielectric constant, such as an organic film typified by polyimide or BCB, is preferable in order to reduce parasitic capacitance. Thereafter, in the wiring process, wirings not shown are formed on the surface of the interlayer insulating film 23. The electrodes 7 to 9 on the semiconductor layer and the wiring electrodes (not shown) on the interlayer insulating film 23 are connected via connection plugs formed in through holes 27 to 29 opened in the interlayer insulating film 23.

What is important here is that the collector electrode 7 is provided in contact with the emitter cap constituent material layer 6, so that the height of the electrode position in the stacking direction is the same between the collector electrode 7 and the emitter electrode 9. The difference Δh ₁₀ between the collector electrode 7 and the base electrode 8 is also only the sum of the film thicknesses of the emitter cap constituent material layer 6 and the emitter constituent material layer 5 and is sufficiently small. In the example described later, Δh ₁₀ is about 175 nm.

Therefore, when the depth of the through holes 27 to 29 formed in the interlayer insulating film 23 in correspondence to the electrodes 7-9 and h ₁ to h _3, equal to the h ₁ and h _3, h ₂ is, h ₁ And h ₃ is only about Δh ₁₀ = 175 nm. For this reason, the process of forming the through holes 27 to 29 can be performed in a batch with good productivity. At this time, when the through hole 28 is completed, the through holes 27 and 29 are already completed, and the etching in the lateral direction is somewhat progressing, but the degree is small, and the etching in the lateral direction is temporarily performed. Is about 175 nm, assuming that the film proceeds at the same speed as the downward etching. This is sufficiently within the normal margin w (about 500 nm) of the main surfaces of the collector electrode 7 and the emitter electrode 8, and there is no problem.

  The constituent material layers 2 to 6 are partially removed to form the active layers 12 to 16 having a mesa structure, but most of them are left. For this reason, the flatness of the surface 24 of the interlayer insulating film 23 formed on the top of the HBT 10 is improved, and the process of forming the wiring on the surface of the interlayer insulating film 23 can be performed very easily.

  When the collector layer 13 of the HBT 10 and the conductive region 21 are in direct contact, as pointed out with respect to the HBT 140 of Patent Document 2, the current that flows directly from the collector layer 13 to the conductive region 21 without passing through the subcollector layer 12 And there is a concern that the electrical characteristics of the HBT 10 may be adversely affected. Therefore, in the HBT 10, a separation groove 22 is provided between the collector layer 13 and the conductive region 21, so that no current flows from the collector layer 13 to the conductive region 21 without passing through the subcollector layer 12. Yes.

For example, the HBT 10 is an NPN type compound heterojunction transistor, the semi-insulating substrate 1 is an indium phosphide InP substrate, the subcollector layer 12 is an n ⁺ type indium gallium arsenide InGaAs layer, and a collector layer. Reference numeral 13 denotes an n ⁻ -type indium phosphide layer, the base layer 14 is a p ⁺ -type indium gallium arsenide layer, the emitter layer 15 is an n ⁻ -type indium phosphide layer, and the emitter cap layer 16 is an n ⁺ indium gallium arsenide layer. Is an n ⁺ -type conductive region.

  More specifically, for example, the semi-insulating substrate 1 may be an indium phosphorus substrate doped with iron Fe. In the indium gallium arsenide semiconductor layer, a gallium arsenide substrate can also be used. However, the reason why the indium phosphide substrate is used here is because the operation speed of the HBT 10 is emphasized.

  That is, in an indium gallium arsenide-based semiconductor layer, the electron mobility increases when the proportion of indium is larger than that of gallium. For high-speed operation of the HBT 10, for example, the molar ratio of indium to gallium is preferably 53:47. In this case, since the ion radius of indium is large, a gallium arsenide substrate having a lattice constant of 0.56 nm is not suitable, and an indium phosphorus substrate having a larger lattice constant of 0.58 nm is suitable. For this reason, by using an indium phosphide substrate, an epitaxially grown layer of an indium gallium arsenide semiconductor having a high operating speed can be formed with few defects. The reason for doping iron Fe is to ensure the insulation of the substrate. Note that when the proportion of indium is small, a gallium arsenide substrate can be preferably used.

The subcollector layer 12 is an n ⁺ -type indium gallium arsenide layer having an n-type impurity concentration of 1 × 10 ¹⁹ / cm ³ or more, and has a thickness of 300 nm. The collector layer 13 is an indium phosphorus layer having an n-type impurity concentration of 1 × 10 ¹⁶ / cm ³ and has a thickness of 500 nm. The base layer 14 is an indium gallium arsenide layer having a p-type impurity concentration of 1 × 10 ¹⁹ / cm ³ or more, and has a thickness of 75 nm. The emitter layer 15 is an indium phosphorus layer having an n-type impurity concentration of 1 × 10 ¹⁷ / cm ³ and has a thickness of 125 nm. The emitter cap layer 16 is an indium gallium arsenide layer having an impurity concentration of 1 × 10 ¹⁹ / cm ³ or more and has a thickness of 50 nm.

  Each of these layers is a stack of a sub-collector constituent material layer 2, a collector constituent material layer 3, a base constituent material layer 4, an emitter constituent material layer 5 and an emitter cap constituent material layer 6 formed by epitaxial growth using MBE or MOCVD. Formed by patterning the body.

  Here, the difference in film thickness, impurity concentration, and material of each layer is not particularly limited. In addition, a structure in which a thin layer or the like having a graded composition and a graded layer is inserted in order to eliminate the discontinuity of the energy band is also included in this embodiment.

  As a material of the electrodes 7 to 9, a material capable of forming an ohmic contact with a semiconductor layer in contact with each other is used. For example, a three-layer structure of Ti / Pt / Au in which titanium, platinum and gold are laminated in this order, or platinum or palladium, titanium, platinum and gold are laminated in this order (Pt or Pd) / Ti / Pt / It is preferable to have a four-layer structure of Au. With such a stacked structure, adhesion and ohmic contact with the underlying semiconductor layer can be realized.

  3 and 4 are flowcharts showing the manufacturing steps of HBT 10 based on the first embodiment.

  First, as shown in FIG. 3A, an indium phosphorus substrate doped with iron Fe is prepared as the semi-insulating substrate 1. A sub-collector constituent material layer 2, a collector constituent material layer 3, a base constituent material layer 4, an emitter constituent material layer 5, and an emitter cap constituent material layer 6 are formed thereon by epitaxial growth using MBE or MOCVD. To do.

Details of each layer are as described above. That is, the subcollector constituent material layer 2 is an n ⁺ type indium gallium arsenide layer having an n type impurity concentration of 1 × 10 ¹⁹ / cm ³ or more and has a thickness of 300 nm. The collector constituting material layer 3 is an indium phosphorus layer having an n-type impurity concentration of 1 × 10 ¹⁶ / cm ³ and has a thickness of 500 nm. The base constituent material layer 4 is an indium gallium arsenide layer having a p-type impurity concentration of 1 × 10 ¹⁹ / cm ³ or more, and has a thickness of 75 nm. The emitter constituting material layer 5 is an indium phosphorus layer having an n-type impurity concentration of 1 × 10 ¹⁷ / cm ³ and has a thickness of 125 nm. The emitter cap constituent material layer 6 is an indium gallium arsenide layer having an impurity concentration of 1 × 10 ¹⁹ / cm ³ or more, and has a thickness of 50 nm.

Next, as shown in FIG. 3B, an ion implantation method using a hard mask 51 such as silicon oxide SiO ₂ from the emitter cap constituent material layer 6 is formed on the collector electrode 7 formation region in the horizontal direction. , N ⁺ -type conductive regions 21 are formed. Since the conductive region 21 needs to reach the subcollector constituent material layer 2, high energy ion implantation is required. For example, silicon ions Si ^{+ and the} like are implanted with an energy of 300 keV or more.

  In the ion implantation with a single implantation energy, the concentration of the implanted dopant varies depending on the depth from the surface of the emitter cap constituent material layer 6 and has a maximum value at a certain depth determined by the implantation energy. A density distribution such as a normal distribution is formed. Therefore, it is desirable to perform ion implantation with a plurality of implantation energies and minimize the difference in impurity concentration of the conductive region 21 due to the difference in depth from the surface.

In particular, for a layer having p ⁺ conductivity, such as the base constituent material layer 4, the implantation energy is adjusted so that the depth at which the dopant concentration becomes maximum coincides with this layer, and it is introduced by ion implantation. The dose is determined so that the n-type impurity concentration is equal to or higher than the p-type impurity concentration present in this layer before ion implantation.

  Thus, according to the ion implantation method, the impurity concentration distribution in the depth direction can be controlled by adjusting the implantation energy, and the impurity concentration can be controlled by adjusting the dose amount. A conductive region 21 having predetermined electrical characteristics can be formed. Other methods for introducing impurities include an impurity diffusion method and the like, which can be used alone or in combination with an ion implantation method.

After the ion implantation, annealing is performed to activate the implanted dopant. For activation annealing, it is ideal to perform annealing for a short time at a high temperature such as RTA (Rapid Thermal Anneal), but it is necessary that the profile of the epitaxial layer itself is not broken by the annealing at a high temperature. Considering that the growth temperature of the epitaxial layer by MBE or MOCVD currently being performed is 500 ° C. to 600 ° C., the temperature range applied to the activation annealing is desirably 500 ° C. or less. However, if the annealing time is shortened, there is a possibility that annealing at a temperature higher than 500 ° C. can be applied. By activation annealing, the impurity concentration of the n ⁺ type conductive region 21 is set to 1 × 10 ¹⁹ / cm ³ or more.

  After the formation of the conductive region 21, as shown in FIG. 3C, the collector electrode 7 and the emitter electrode 9 are formed simultaneously. The electrodes 7 and 9 are, for example, a three-layer structure of Ti / Pt / Au in which titanium, platinum and gold are laminated in this order, or platinum or palladium, titanium, platinum and gold are laminated in this order (Pt or Pd). ) / Ti / Pt / Au. With such a stacked structure, adhesion and ohmic contact with the underlying semiconductor layer can be realized. The electrodes 7 and 9 are formed by forming the above electrode material layer, patterning the photoresist 52 thereon, and selectively etching the electrode material layer using the photoresist 52 as a mask.

  The electrodes 7 and 9 may be formed by a lift-off method. In the lift-off method, a photoresist layer is formed on the entire surface of the emitter cap constituent material layer 6 by a coating method or the like, and is patterned by photolithography and etching into a pattern that covers a region other than the region where the electrodes 7 and 9 are formed. Next, after an electrode material layer is formed on the entire surface by vacuum evaporation or the like, the photoresist layer is removed by development processing. At this time, the electrode material layer deposited on the photoresist layer is also removed, and only the electrode material layer formed in close contact with the emitter cap constituent material layer 6 is left as the electrodes 7 and 9.

  Next, as shown in FIG. 3D, a photoresist 53 is formed by patterning, and the emitter cap constituent material layer 6 and the emitter constituent material layer 5 are selectively etched using the photoresist 53 as a mask. An emitter mesa composed of the emitter cap layer 16 and the emitter layer 15 is formed, and the base constituent material layer 4 is exposed.

  Next, as shown in FIG. 4E, selective evaporation is performed using the evaporation mask 54 to form the base electrode 8. The base electrode 8 may be formed by the lift-off method described above, but rather is generally formed by the lift-off method.

  Next, as shown in FIG. 4F, a photoresist 55 is formed by patterning, and the base constituent material layer 4 and the collector constituent material layer 3 are selectively etched using the photoresist 55 as a mask. A base mesa made of the base layer 14 and a collector mesa made of the collector layer 13 are formed, and an isolation groove 22 is formed between the collector layer 13 of the HBT 10 and the conductive region 21.

  Next, as shown in FIG. 4G, a photoresist 56 is formed by patterning, and the sub-collector constituting material layer 2 is selectively etched using the photoresist 56 as a mask to form the sub-collector layer 12. A subcollector mesa is formed, and isolation (isolation) between elements is performed.

  Next, as shown in FIG. 4H, the photoresist 56 is removed. Subsequently, subsequent processes such as a wiring process are performed.

  The formation of the emitter mesa shown in FIG. 3D, the formation of the base mesa and the collector mesa and the separation groove 22 shown in FIG. 4F, and the formation of the sub-collector mesa shown in FIG. It is desirable to form by anisotropic etching by dry etching. This is because if wet etching is used to form the emitter mesa, side etching occurs and the etching may reach the conductive region 21. Therefore, it is desirable that the mesa structure formed by anisotropic etching is processed into a mesa shape in which the side wall surface of the mesa structure is perpendicular to the substrate surface. For the same reason, formation of other mesas and separation grooves 22 is preferably performed by anisotropic dry etching that is less likely to cause side etching and can be finely processed into an accurate shape.

  In the HBT 10 manufactured through the above steps, the collector electrode 7 and the emitter electrode 9 have the same height, and the process difficulty of the subsequent wiring step can be reduced as described with reference to FIG. In the HBT 100 as an example of the conventional mesa structure shown in FIG. 10, the step between the upper surface of the emitter electrode 9 and the upper surface of the collector electrode 7 is 750 nm. However, the HBT 10 of the present embodiment has no step. The level difference between the collector electrode 7 and the base electrode 8 is also very flat, about 200 nm.

  As described above, in the HBT 10 that is the heterojunction semiconductor device of the present embodiment, the collector electrode 7 is provided on and in contact with the emitter cap constituent material layer 6, so that the emitter electrode 9, the base electrode 8, and the collector are provided. The height difference in the stacking direction with the electrode 7 is smaller than that of the conventional mesa structure example (see FIG. 14).

  As a result, when the interlayer insulating film 23 for wiring is formed on the HBT 10, the depths of the through holes 27 to 29 provided for connection to the electrodes 7 to 9 are well aligned. Thus, productivity can be improved. Further, since the flatness of the surface of the interlayer insulating film 23 is improved, the productivity of the wiring forming process is improved, and the possibility that the wiring is disconnected is reduced. In addition, the exposure accuracy of the photoresist formed in the wiring process and the etching accuracy of the wiring material layer are improved, and a wiring having a predetermined pattern can be formed, thereby improving the performance of the HBT 10.

  The method for manufacturing the HBT 10 according to the present embodiment is a method in which the structure of the HBT 10 is integrated with the front and back, and the HBT 10 can be manufactured efficiently. That is, when forming the collector electrode, the constituent material layer already formed is used, so that the process is simplified. In addition, since all the constituent material layers are formed at once, they are processed, so that the continuity of the process is maintained, the efficiency is high, and the manufacturing can be performed with a simple process and high productivity. In addition, there is no alteration or contamination of the surface of the epitaxial growth layer due to interruption of the film formation process, and the constituent material layer formed under the best conditions can be used as an active layer of a semiconductor device without deterioration. And the performance of the HBT 10 is improved.

Embodiment 2
In the second embodiment, an InP heterojunction bipolar is mainly used as an example of a method for manufacturing a heterojunction semiconductor device according to claims 1 and 3 and a heterojunction semiconductor device according to claims 19, 21, 27 and 29. A transistor and a manufacturing method thereof will be described. This embodiment is different from the first embodiment mainly in that a collector electrode is provided on and in contact with a base constituent material layer. The following description will be given with emphasis on the differences from the first embodiment. In the following FIGS. 5 to 7, the semiconductor layers and electrodes having the same functions as those in the first embodiment are indicated by the same numbers as those in the first embodiment even if the shape is slightly changed (the same applies hereinafter). .)

  FIG. 5 is a cross-sectional view showing the structure of HBT 20 based on the second embodiment. In the HBT 20, as in the HBT 10, the subcollector layer 12, the collector layer 13, the base layer 14, the emitter layer 15, and the emitter cap layer 16 are formed on the semi-insulating substrate 1 by the epitaxial growth method using the MBE method or the MOCVD method. Are sequentially laminated. The emitter cap layer 16 and the emitter layer 15 are patterned into a mesa structure, the emitter electrode 9 is provided in contact with the emitter cap layer 16, and the base electrode 8 is provided in contact with the base layer 14.

  The present embodiment is different from the first embodiment in that the collector electrode 7 is provided on the base constituent material layer 4 as one of the structures satisfying the requirement that does not cause a large height difference between the electrodes. Then, similarly to the first embodiment, a conductive region 21 that electrically connects the collector electrode 7 and the subcollector layer 12 is formed.

  In this case, the height of the electrode position in the stacking direction is the same between the collector electrode 7 and the base electrode 8, and the difference between the collector electrode 7 and the emitter electrode 9 is also the difference between the emitter cap constituent material layer 6 and the emitter constituent material layer 5. It is only the sum of the film thicknesses and is sufficiently small. As described above, the difference between the present embodiment and the first embodiment is that the height of the collector electrode 7 is matched with the height of the base electrode 8 or the height of the emitter electrode 9. , Not an essential difference.

  When the collector layer 13 of the HBT 20 and the conductive region 21 are in direct contact, as pointed out with respect to the HBT 140 of Patent Document 2, the current flowing from the collector layer 13 to the conductive region 21 without passing through the subcollector layer 12 is It is feared that the electrical characteristics of the HBT 20 may be adversely affected. Therefore, also in the present embodiment, as in the first embodiment, a separation groove 22 is provided between the collector layer 13 of the HBT 20 and the conductive region 21 so that the conductive region 21 does not pass through the collector layer 13 of the HBT 20 and the subcollector layer 12. Current is not generated.

  As another difference between the present embodiment and the first embodiment, in the present embodiment, after the emitter electrode 9 is formed, the formation of the conductive region 21 and its activation annealing treatment may be performed. In this case, since the emitter electrode 9 needs to withstand the annealing temperature, it is preferable that the emitter electrode 9 be made of a high melting point metal material corresponding to the annealing temperature, specifically tungsten W or molybdenum Mo.

  FIG. 6 and FIG. 7 are flowcharts showing a manufacturing process of HBT 20 based on the second embodiment.

  First, as shown in FIG. 6A, in the same manner as in the first embodiment, an indium phosphorous substrate doped with iron Fe is prepared as the semi-insulating substrate 1, and the MBE method or the MOCVD method is used thereon. The sub-collector constituent material layer 2, the collector constituent material layer 3, the base constituent material layer 4, the emitter constituent material layer 5, and the emitter cap constituent material layer 6 are formed by the epitaxial growth method. Details of each layer are as described above, and are omitted here.

Next, as shown in FIG. 6B, an emitter electrode 9 is formed on the emitter cap constituent material layer 6. Since the electrode material of the emitter electrode 9 needs to withstand the processing temperature of the activation annealing process after ion implantation into the n ⁺ conductive region 21, a metal material having a high melting point, specifically tungsten, according to the annealing temperature. W or molybdenum Mo is used. The electrode 9 is formed by forming these electrode material layers, patterning the photoresist 61 thereon, and selectively etching the electrode material layer using the photoresist 61 as a mask.

  Next, as shown in FIG. 6C, a photoresist 62 is formed by patterning, and the emitter cap constituent material layer 6 and the emitter constituent material layer 5 are selectively etched using the photoresist 62 as a mask. An emitter mesa composed of the emitter cap layer 16 and the emitter layer 15 is formed, and the base constituent material layer 4 is exposed.

Next, as shown in FIG. 6D, from the surface of the base constituent material layer 4 to the formation region of the collector electrode 7 in the horizontal direction, by ion implantation using a hard mask 63 such as silicon oxide SiO ₂ . An n ⁺ type conductive region 21 is formed. Thereafter, annealing is performed to activate the implanted dopant. Although not described in detail because it is the same as in the first embodiment, the impurity concentration of the n ⁺ -type conductive region 21 is set to 1 × 10 ¹⁹ / cm ³ or more through the above steps.

  Next, as shown in FIG. 7E, selective deposition is performed using the deposition mask 64 to form the collector electrode 7 and the base electrode 8.

  Next, as shown in FIG. 7F, a photoresist 65 is formed by patterning, and the base constituent material layer 4 and the collector constituent material layer 3 are selectively etched using the photoresist 65 as a mask. A base mesa made of the base layer 14 and a collector mesa made of the collector layer 13 are formed, and an isolation groove 22 is formed between the collector layer 13 of the HBT 20 and the conductive region 21.

  Next, as shown in FIG. 7G, a photoresist 66 is formed by patterning, and the sub-collector constituting material layer 2 is selectively etched using the photoresist 66 as a mask to form the sub-collector layer 12. A subcollector mesa is formed, and isolation (isolation) between elements is performed.

  Next, as shown in FIG. 7H, the photoresist 66 is removed. Subsequently, subsequent processes such as a wiring process are performed.

  In the HBT 20 manufactured through the above steps, the level difference between the emitter electrode top and the collector electrode top or the base electrode top is very flat, about 200 nm, and the process difficulty of the wiring process can be reduced.

  As described in Embodiment 1, any or all of the collector electrode 7, the base electrode 8, and the emitter electrode 9 may be formed by a lift-off method.

  As described above, although the present embodiment is different in position at which the collector electrode is provided, there is essentially no difference from the first embodiment, so that the same operational effects as in the first embodiment can be obtained. Needless to say.

  That is, in the HBT 20 that is the heterojunction semiconductor device of the present embodiment, the collector electrode 7 is provided on and in contact with the emitter cap constituent material layer 6, so that the emitter electrode 9, the base electrode 8, and the collector electrode 7 are stacked. The height difference in the direction is smaller than that of the conventional mesa structure example (see FIG. 14).

  As a result, when an interlayer insulating film for wiring is formed above the HBT 20, the through holes provided for connection to the electrodes 7 to 9 are well aligned, so that the through holes can be formed in a lump. , Improve productivity. Further, since the flatness of the surface of the interlayer insulating film is improved, the productivity of the wiring forming process is improved, and the possibility that the wiring is disconnected is reduced. In addition, the exposure accuracy of the photoresist formed in the wiring process and the etching accuracy of the wiring material layer are improved, and wiring according to a predetermined pattern can be formed, so that the performance of the HBT 20 is improved.

  The method for manufacturing the HBT 20 according to the present embodiment is a method in which the structure of the HBT 20 is integrated with the front and back, and the HBT 20 can be manufactured efficiently. That is, when forming the collector electrode, the constituent material layer already formed is used, so that the process is simplified. In addition, since all the constituent material layers are formed at once, they are processed, so that the continuity of the process is maintained, the efficiency is high, and the manufacturing can be performed with a simple process and high productivity. In addition, there is no alteration or contamination of the surface of the epitaxial growth layer due to interruption of the film formation process, and the constituent material layer formed under the best conditions can be used as an active layer of a semiconductor device without deterioration. And the performance of the HBT 20 is improved.

Embodiment 3
In the third embodiment, an InP heterojunction bipolar transistor and its manufacture are mainly described as examples relating to the semiconductor device described in claims 1 and 4 and the method of manufacturing the semiconductor device described in claims 19, 22, 30 and 31. A method will be described. This embodiment is different from the first or second embodiment in that a collector electrode is mainly provided on and in contact with a collector constituent material layer. The following description will be given with emphasis on the differences from the first or second embodiment.

  FIG. 8 is a cross-sectional view showing the structure of HBT 30 based on the third embodiment. In the HBT 30, the subcollector layer 12, the collector layer 13, the base layer 14, the emitter layer 15, and the emitter cap are formed on the semi-insulating substrate 1 by the epitaxial growth method using the MBE method or the MOCVD method, similarly to the HBTs 10 and 20. The layer 16 is formed by sequentially laminating. The emitter cap layer 16 and the emitter layer 15 are patterned into a mesa structure, the emitter electrode 9 is provided in contact with the emitter cap layer 16, and the base electrode 8 is provided in contact with the base layer 14.

  In the present embodiment, the collector electrode 7 is provided on the collector constituent material layer 3 as one of the structures that satisfy the requirement not to cause a large height difference between the electrodes. Then, as in the first and second embodiments, a conductive region 21 that electrically connects collector electrode 7 and subcollector layer 12 is formed.

  In this case, the difference in height between the electrode positions in the stacking direction is the difference between the collector electrode 7 and the base electrode 8, and the difference between the collector electrode 7 and the emitter electrode 9 is the base constituent material layer as compared with the second embodiment. The film thickness increases only by 6 (75 nm in the example of the thickness of the constituent material layer described above). Therefore, with respect to the electrode position, the present embodiment is not fundamentally different from the second embodiment, and thus is not fundamentally different from the first embodiment.

  On the other hand, there are important differences in the production of HBT30. In the first and second embodiments, ion implantation is performed from above the base constituent material layer 6 having a conductivity type opposite to the conductivity type of the subcollector constituent material layer 2 (for example, p-type), so that a conductive region in the base constituent material layer 6 is obtained. It is necessary to change the conductivity type 21 to at least the same conductivity type as that of the subcollector constituting material layer 2 (for example, n-type). However, since the base constituent material layer 6 has a high impurity concentration, it is troublesome to perform this by an ion implantation method or an impurity diffusion method. In contrast, in the present embodiment, ion implantation is performed after the base constituent material layer 6 is removed from the formation position of the conductive region 21 in the surface direction of the substrate, so that the conductivity type of the base constituent material layer 6 needs to be changed. The conductive region 21 is very easily formed.

  When the collector layer 13 of the HBT 30 and the conductive region 21 are in direct contact, as pointed out with respect to the HBT 140 of Patent Document 2, a current flowing from the collector layer 13 to the conductive region 21 without passing through the subcollector layer 12 is generated. It is feared that the electric characteristics of the HBT 30 may be adversely affected. Therefore, in the present embodiment as well, in the same way as in the first and second embodiments, a separation groove 22 is provided between the collector layer 13 of the HBT 30 and the conductive region 21, and the conductive layer 13 does not pass through the subcollector layer 12 from the collector layer 13 of the HBT 30. The current flowing to the region 21 is prevented from being generated.

  Further, as another difference between the present embodiment and the first or second embodiment, in this embodiment, after the emitter electrode 9 and the base electrode 8 are formed, the formation of the conductive region 21 and its activation annealing treatment are performed. Is done. In this case, since the emitter electrode 9 and the base electrode 8 need to withstand the annealing temperature, these electrodes are made of a high melting point metal material corresponding to the annealing temperature, specifically tungsten W or molybdenum Mo. Is good.

  FIG. 9 and FIG. 10 are flowcharts showing manufacturing steps of HBT 30 based on the third embodiment. However, since the steps of FIGS. 6A to 6C are the same as those in Embodiment 2, they are not shown.

  That is, first, the subcollector constituent material layer 2, the collector constituent material layer 3, and the base structure are formed on the indium phosphorous substrate doped with iron Fe as the semi-insulating substrate 1 by the steps of FIGS. After forming the material layer 4, the emitter constituent material layer 5, and the emitter cap constituent material layer 6, and forming the emitter electrode 9 on the emitter cap constituent material layer 6, the emitter cap constituent material layer 6 and the emitter constituent material layer 5 are formed. Are selectively etched to form an emitter mesa composed of the emitter cap layer 16 and the emitter layer 15, and the base constituent material layer 4 is exposed.

  Next, as shown in FIG. 9A, selective vapor deposition is performed using the vapor deposition mask 71 to form the base electrode 8.

  Note that the material of the emitter electrode 9 and the base electrode 8 needs to withstand the processing temperature of the activation annealing process after ion implantation into the conductive region 21. For this, tungsten W or molybdenum Mo is used.

  Next, as shown in FIG. 9B, a photoresist 72 is formed by patterning, and the base constituent material layer 4 is selectively etched using the photoresist 72 as a mask to form a base mesa made of the base layer 14. Form.

Next, as shown in FIG. 9C, from the surface of the collector constituent material layer 3 to the formation region of the collector electrode 7 in the horizontal direction, by ion implantation using a hard mask 73 such as silicon oxide SiO ₂ . An n ⁺ type conductive region 21 is formed. After that, annealing is performed to activate the implanted dopant so that the impurity concentration of the n ⁺ -type conductive region 21 is 1 × 10 ¹⁹ / cm ³ or more.

  Next, as shown in FIG. 9D, selective deposition is performed using the deposition mask 74 to form the collector electrode 7.

  Next, as shown in FIG. 10E, a photoresist 75 is formed by patterning, and the collector constituent material layer 3 is selectively etched using the photoresist 75 as a mask to form a collector mesa made of the collector layer 13. At the same time, a separation groove 22 is formed between the collector layer 13 of the HBT 30 and the conductive region 21.

  Next, as shown in FIG. 10F, a photoresist 76 is formed by patterning, and the subcollector constituting material layer 2 is selectively etched using the photoresist 76 as a mask to form the subcollector layer 12. A subcollector mesa is formed, and isolation (isolation) between elements is performed.

  Next, as shown in FIG. 10G, the photoresist 76 is removed. Subsequently, subsequent processes such as a wiring process are performed.

  As described in Embodiment 1, any or all of the collector electrode 7, the base electrode 8, and the emitter electrode 9 may be formed by a lift-off method.

  As described above, in the present embodiment, since the ion implantation is performed without the base constituent material layer 6, the formation of the conductive region 21 becomes extremely easy. In other respects, although the position where the collector electrode is provided is different, there is essentially no difference from the second embodiment, and it is needless to say that the same effects as those of the second embodiment can be obtained.

  That is, in the HBT 30 that is the heterojunction semiconductor device of the present embodiment, the collector electrode is provided on and in contact with the collector constituent material layer, so that the height difference in the stacking direction of the emitter electrode, the base electrode, and the collector electrode is This is smaller than the conventional mesa structure example (see FIG. 14).

  As a result, when an interlayer insulating film for wiring is formed on the HBT 30, the through holes provided for connection to the electrodes 7 to 9 are well aligned, so that the through holes can be formed in a lump. , Improve productivity. Further, since the flatness of the surface of the interlayer insulating film is improved, the productivity of the wiring forming process is improved, and the possibility that the wiring is disconnected is reduced. Further, the exposure accuracy of the photoresist formed in the wiring process and the etching accuracy of the wiring material layer are improved, and a wiring having a predetermined pattern can be formed, so that the performance of the HBT 30 is improved.

  The method of manufacturing the HBT 30 according to the present embodiment is a method in which the structure of the HBT 30 is integrated with the front and back, and the HBT 30 can be manufactured efficiently. That is, when forming the collector electrode, the constituent material layer already formed is used, so that the process is simplified. In addition, since all the constituent material layers are formed at once, they are processed, so that the continuity of the process is maintained, the efficiency is high, and the manufacturing can be performed with a simple process and high productivity. In addition, there is no alteration or contamination of the surface of the epitaxial growth layer due to interruption of the film formation process, and the constituent material layer formed under the best conditions can be used as an active layer of a semiconductor device without deterioration. And the performance of the HBT 30 is improved.

Embodiment 4
In the fourth embodiment, an InP-based heterojunction is mainly described as an example related to a method for manufacturing a heterojunction semiconductor device according to claims 1 and 4 and a heterojunction semiconductor device according to claims 19, 22, 30, 31, and 32. A junction bipolar transistor and a manufacturing method thereof will be described. In the present embodiment, before the ion implantation, the collector constituent material layer is selectively removed, and the film thickness of the collector constituent material layer is reduced at the collector electrode formation position in the surface direction of the substrate. Only the injection is different from the third embodiment. The following description will be given with emphasis on the differences from the third embodiment.

  FIG. 11 is a cross-sectional view showing the structure of HBT 40 based on the fourth embodiment. In the HBT 40, similarly to the HBT 30, the subcollector layer 12, the collector layer 13, the base layer 14, the emitter layer 15, and the emitter cap layer 16 are formed on the semi-insulating substrate 1 by an epitaxial growth method using MBE or MOCVD. Are sequentially stacked. The emitter cap layer 16 and the emitter layer 15 are patterned into a mesa structure. The emitter electrode 9 is provided in contact with the emitter cap layer 16, and the base electrode 8 is provided in contact with the base layer 14. The HBT 40 is substantially the same as the HBT 30 except that the thickness of the collector constituting material layer 3 below the collector electrode 7 is smaller than the thickness of the collector layer 13 by Δd.

  In the present embodiment, as one structure satisfying the requirement not to cause a large difference in height between the electrode positions, the collector electrode 7 is formed on the collector constituent material layer 3 whose film thickness is reduced by Δd as described above. Provide. Then, similarly to the third embodiment, a conductive region 21 that electrically connects the collector electrode 7 and the subcollector layer 12 is formed.

  In this case, the difference between the position of the collector electrode 7 in the stacking direction and the position of the base electrode 8 and the position of the emitter electrode 9 is increased by Δd as compared with the third embodiment. Therefore, if Δd is small, the influence on the electrode position can be suppressed.

  On the other hand, since the film thickness of the collector constituent material layer 3 which forms the conductive region 21 is reduced in this way, there is an advantage that the conductive region 21 can be easily formed by ion implantation. However, Δd is set to such a size that the height difference of the electrode position does not become too large.

  FIG. 12 and FIG. 13 are flowcharts showing manufacturing steps of HBT 40 based on the fourth embodiment. However, since the steps from FIGS. 6A to 6C are the same as those in the second embodiment, they are not shown.

  That is, first, the subcollector constituent material layer 2, the collector constituent material layer 3, and the base structure are formed on the indium phosphorous substrate doped with iron Fe as the semi-insulating substrate 1 by the steps of FIGS. After forming the material layer 4, the emitter constituent material layer 5, and the emitter cap constituent material layer 6, and forming the emitter electrode 9 on the emitter cap constituent material layer 6, the emitter cap constituent material layer 6 and the emitter constituent material layer 5 are formed. Are selectively etched to form an emitter mesa composed of the emitter cap layer 16 and the emitter layer 15, and the base constituent material layer 4 is exposed.

  Next, as shown in FIG. 12A, selective vapor deposition is performed using the vapor deposition mask 81 to form the base electrode 8.

  Note that the material of the emitter electrode 9 and the base electrode 8 needs to withstand the processing temperature of the activation annealing process after ion implantation into the conductive region 21. For this, tungsten W or molybdenum Mo is used.

  Next, as shown in FIG. 12B, a photoresist 82 is formed by patterning, and the base constituent material layer 4 is selectively etched using the photoresist 72 as a mask to form a base mesa made of the base layer 14. Form. At this time, further etching is performed to remove a part of the collector base constituent material layer 3.

Next, as shown in FIG. 12C, from the surface of the collector constituent material layer 3 to the formation region of the collector electrode 7 in the horizontal direction, by ion implantation using a hard mask 83 such as silicon oxide SiO ₂ . An n ⁺ type conductive region 21 is formed. After that, annealing is performed to activate the implanted dopant so that the impurity concentration of the n ⁺ -type conductive region 21 is 1 × 10 ¹⁹ / cm ³ or more.

  Next, as illustrated in FIG. 12D, selective deposition is performed using the deposition mask 84 to form the collector electrode 7.

  Next, as shown in FIG. 13E, a photoresist 85 is formed by patterning, and the collector constituent material layer 3 is selectively etched using the photoresist 75 as a mask to form a collector mesa made of the collector layer 13. At the same time, a separation groove 22 is formed between the collector layer 13 of the HBT 40 and the conductive region 21.

  Next, as shown in FIG. 13F, a photoresist 86 is formed by patterning, and the subcollector constituting material layer 2 is selectively etched using the photoresist 76 as a mask to form the subcollector layer 12. A subcollector mesa is formed, and isolation (isolation) between elements is performed.

  Next, as shown in FIG. 13G, the photoresist 76 is removed. Subsequently, subsequent processes such as a wiring process are performed.

  As described in Embodiment 1, any or all of the collector electrode 7, the base electrode 8, and the emitter electrode 9 may be formed by a lift-off method.

  As described above, in the present embodiment, the ion implantation is performed while reducing the film thickness of the collector constituent material layer 3, so that the formation of the conductive region 21 is facilitated. In other respects, although the position where the collector electrode is provided is different by Δd, there is no difference from the third embodiment. Therefore, if Δd does not become too large, the same effect as in the third embodiment can be obtained. Needless to say.

  As mentioned above, although this invention was demonstrated based on embodiment, it cannot be overemphasized that this invention is not limited to these examples at all, and can be suitably changed in the range which does not deviate from the main point of invention.

  The heterojunction semiconductor device and the manufacturing method thereof according to the present invention are used in various electronic circuits, semiconductor devices such as heterojunction bipolar transistors (HBTs) made of a group 3-5 compound semiconductor, which realize high speed and high integration, and It is used as a manufacturing method, and can contribute to cost reduction, high performance, and high reliability.

They are sectional drawing (a) which shows the structure of HBT based on Embodiment 1 of this invention, and sectional drawing (b) for demonstrating the necessity of the electrode arrangement | positioning. It is a partial expanded sectional view which shows the state in which the through-hole was formed in HBT. It is a flowchart which shows the manufacturing process of HBT same as the above. It is a flowchart which shows the manufacturing process of HBT same as the above. It is sectional drawing which shows the structure of HBT based on Embodiment 2 of this invention. It is a flowchart which shows the manufacturing process of HBT same as the above. It is a flowchart which shows the manufacturing process of HBT same as the above. It is sectional drawing which shows the structure of HBT based on Embodiment 3 of this invention. It is a flowchart which shows the manufacturing process of HBT same as the above. It is a flowchart which shows the manufacturing process of HBT same as the above. It is sectional drawing which shows the structure of HBT based on Embodiment 4 of this invention. It is a flowchart which shows the manufacturing process of HBT same as the above. It is a flowchart which shows the manufacturing process of HBT same as the above. It is sectional drawing for demonstrating the problem of HBT which consists of a laminated body of a mesa structure. FIG. 5 is a partially enlarged cross-sectional view for explaining one of the problems in forming through holes having greatly different depths in the interlayer insulating film above the HBT. It is sectional drawing which shows the structure of HBT shown by patent document 2. FIG. It is sectional drawing which shows the structure of HBT shown by patent document 3. FIG. It is sectional drawing which shows the structure of HBT shown by patent document 4. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semi-insulating board | substrate, 2 ... Subcollector constituent material layer, 3 ... Collector constituent material layer,
4 ... Base constituent material layer, 5 ... Emitter constituent material layer, 6 ... Emitter cap constituent material layer,
7 ... Collector electrode, 8 ... Base electrode, 9 ... Emitter electrode, 10 ... HBT,
12 ... Subcollector layer, 13 ... Collector layer, 14 ... Base layer, 15 ... Emitter layer,
16 ... Emitter cap layer, 20 ... HBT, 21 ... Conductive region, 22 ... Separation groove,
23 ... Interlayer insulating film, 27 to 29 ... Through hole, 30, 40 ... HBT,
51 ... Hard mask, 52, 53, 55, 56 ... Photoresist, 54 ... Evaporation mask,
61, 62, 65, 66 ... photoresist, 63 ... hard mask, 64 ... vapor deposition mask,
71, 74 ... evaporation mask, 72, 75, 76 ... photoresist, 73 ... hard mask,
81, 84 ... deposition mask, 82, 85, 86 ... photoresist, 83 ... hard mask,
100 ... HBT, 101 ... semi-insulating substrate, 102 ... subcollector layer,
103 ... Collector layer, 104 ... Base layer, 105 ... Emitter layer,
106: Emitter cap layer, 107: Collector electrode, 108: Base electrode,
109 ... emitter electrode, 110 ... interlayer insulating film, 111 ... ideal interlayer insulating film surface,
112 ... Actual interlayer insulating film surface, 114-116 ... Wiring electrode,
117 to 119 ... connection plug, 117h to 119h ... through hole, 120 ... HBT,
121... Semi-insulating gallium arsenide substrate, 122... N ⁺ type GaAs layer (collector extraction layer),
123 ... n-type GaAs layer (collector layer), 124 ... n ⁺ -type GaAs layer (base layer),
125 ... n-type AlGaAs layer (emitter layer),
126 ... n ⁺ -type GaAs layer (emitter cap layer)
127 ... Collector electrode, 128 ... Base electrode, 129 ... Emitter electrode,
130 ... Silicon oxide film, 131 ... Wiring,
132 ... n ⁺ -type GaAs layer (second extraction layer), 140 ... HBT,
141 ... Semi-insulating substrate, 142 ... Subcollector region, 143 ... Collector region,
144 ... Base layer, 145 ... Emitter layer, 147 ... Collector electrode, 148 ... Base electrode,
149 ... emitter electrode, 150 ... conductive region, 151 ... insulating region, 160 ... HBT,
161... GaAs semiconductor substrate, 162... N ⁺ type GaAs layer (subcollector layer),
164 ... n-type GaAs layer (collector layer), 165 ... deep n ⁺ layer,
167... P ⁺ type AlGaAs layer (base layer), 168... N type AlGaAs layer (emitter layer),
169 ... n ⁺ -type GaAs cap layer (emitter cap layer), 170 ... p ⁺ layer,
171 ... Isolation layer, 172 ... Silicon nitride layer,
173 to 175 ... Ohmic electrodes

Claims (40)

In a heterojunction semiconductor device in which a subcollector layer, a collector layer, a base layer, and an emitter layer are laminated on a base in this order,
By processing the laminated body composed of the constituent material layers that become the sub-collector layer, the collector layer, the base layer, and the emitter layer, another constituent material layer is left on the sub-collector layer,
A collector electrode is provided on and in contact with the remaining component material layer,
A heterojunction semiconductor device, wherein a conductive region for electrically connecting the collector electrode and the subcollector layer is provided.   The heterojunction semiconductor device according to claim 1, wherein the collector electrode is provided on and in contact with an emitter constituent material layer or an emitter cap constituent material layer.   The heterojunction semiconductor device according to claim 1, wherein the collector electrode is provided on and in contact with the base constituent material layer.   The heterojunction semiconductor device according to claim 1, wherein the collector electrode is provided on and in contact with a collector constituent material layer.   The conductive region is formed by changing a region of the constituent material layer between the collector electrode and the subcollector layer into a highly conductive region of the same conductivity type as the subcollector layer. Item 12. The heterojunction semiconductor device according to Item 1.   The heterojunction semiconductor device according to claim 5, wherein the highly conductive region reaches the subcollector layer.   The heterojunction semiconductor device according to claim 5, wherein the highly conductive region is formed by ion implantation into the region.   The heterojunction semiconductor device according to claim 7, wherein the ion implantation is performed by silicon ion implantation.   The conductive region is formed through at least the base constituent material layer and the collector constituent material layer by the ion implantation, and the first conductive type impurity concentration of the conductive region is at least the second conductive type impurity concentration of the base constituent material layer. The heterojunction semiconductor device according to claim 7, which is the above. The conductive region is formed through a collector constituent material layer in which a base constituent material layer does not exist on an upper surface by the ion implantation, and an impurity concentration of the conductive region is 1 × 10 ¹⁹ / cm ³ or more. Heterojunction semiconductor device.   The heterojunction semiconductor device according to claim 1, wherein the collector electrode and the conductive region are electrically connected to the collector layer only through the subcollector layer.   The heterojunction semiconductor device according to claim 11, wherein the conductive region and the collector layer and the base layer are insulated and separated.   The collector electrode has a three-layer structure of Ti / Pt / Au in which titanium, platinum and gold are laminated in this order, or platinum or palladium, titanium, platinum and gold are laminated in this order (Pt or Pd) / Ti / Pt. The heterojunction semiconductor device according to claim 1, comprising a four-layer structure of / Au.   The heterojunction semiconductor device according to claim 1, wherein the emitter electrode and / or the base electrode is made of tungsten W or molybdenum Mo.   The heterojunction semiconductor device according to claim 1, wherein the substrate is made of a compound semiconductor.   16. The heterojunction semiconductor device according to claim 15, wherein the substrate of claim 1 is made of indium phosphide InP or gallium arsenide GaAs.   The heterojunction semiconductor device according to claim 15, wherein the constituent material layer is configured as a heterojunction bipolar transistor made of a compound semiconductor.   The heterojunction semiconductor device according to claim 17 configured as an NPN-type bipolar transistor. A method of manufacturing a heterojunction semiconductor device according to claim 1,
A step of laminating a sub-collector constituent material layer, a collector constituent material layer, a base constituent material layer, and an emitter constituent material layer in this order on the substrate;
Processing the laminate to leave another constituent material layer on top of the subcollector constituent material layer at the collector electrode formation position in the surface direction of the base;
Forming the collector electrode thereon in contact with the remaining component material layer;
Forming a conductive region that electrically connects the collector electrode and the sub-collector constituent material layer.   The method of manufacturing a heterojunction semiconductor device according to claim 19, wherein the collector electrode is formed on and in contact with the emitter constituent material layer or the emitter cap constituent material layer.   The method of manufacturing a heterojunction semiconductor device according to claim 19, wherein the collector electrode is formed on and in contact with the base constituent material layer.   The method of manufacturing a heterojunction semiconductor device according to claim 19, wherein the collector electrode is formed on and in contact with a collector constituent material layer.   The conductive region is formed by changing a region of the constituent material layer between the collector electrode and the subcollector layer into a highly conductive region of the same conductivity type as the subcollector layer. A method of manufacturing a heterojunction semiconductor device described in 1.   The method for manufacturing a heterojunction semiconductor device according to claim 23, wherein the highly conductive region is formed so as to reach the subcollector layer.   The method for manufacturing a heterojunction semiconductor device according to claim 23, wherein the highly conductive region is formed by ion implantation into the region.   26. The method of manufacturing a heterojunction semiconductor device according to claim 25, wherein the ion implantation is performed by silicon ion implantation.   By the ion implantation, the conductive region is formed at least through the base constituent material layer and the collector constituent material layer, and the first conductive type impurity concentration of the conductive region is set to at least the second conductive type impurity concentration of the base constituent material layer. The method for manufacturing a heterojunction semiconductor device according to claim 25, as described above. Forming the laminated body in which a sub-collector constituent material layer, a collector constituent material layer, a base constituent material layer, an emitter constituent material layer, and an emitter cap constituent material layer are laminated in this order on the substrate;
Next, at the formation position of the collector electrode in the surface direction of the base, the ion implantation is performed from the surface of the emitter cap constituent material layer to the stacked body, and the emitter cap constituent material layer, the emitter constituent material layer, Forming the conductive region reaching the sub-collector constituent material layer in the base constituent material layer and the collector constituent material layer;
Next, the collector electrode is formed on and in contact with the emitter cap constituent material layer,
Next, the emitter cap constituent material layer, the emitter constituent material layer, the base constituent material layer, the collector constituent material layer, and the subcollector constituent material layer are selectively removed to form the emitter cap layer, the emitter layer Forming the base layer, the collector layer and the sub-collector layer;
28. A method of manufacturing a heterojunction semiconductor device according to claim 27. Forming the laminated body in which a sub-collector constituent material layer, a collector constituent material layer, a base constituent material layer, an emitter constituent material layer, and an emitter cap constituent material layer are laminated in this order on the substrate;
Next, the emitter cap constituent material layer and the emitter constituent material layer are selectively removed to form the emitter cap layer and the emitter layer,
Next, at the position where the collector electrode is formed in the surface direction of the base, the ion implantation is performed from the surface of the base constituent material layer to the stacked body, and the base constituent material layer and the collector constituent material layer are subjected to the sub Forming the conductive region reaching the collector constituent material layer,
Next, the collector electrode is formed on and in contact with the base constituent material layer,
Next, the base constituent material layer, the collector constituent material layer, and the sub-collector constituent material layer are selectively removed to form the base layer, the collector layer, and the sub-collector layer.
28. A method of manufacturing a heterojunction semiconductor device according to claim 27. The conductive region is formed through a collector constituent material layer having no base constituent material layer on the upper surface by the ion implantation, and an impurity concentration of the conductive region is set to 1 × 10 ¹⁹ / cm ³ or more. A method of manufacturing a heterojunction semiconductor device. Forming the laminated body in which a sub-collector constituent material layer, a collector constituent material layer, a base constituent material layer, an emitter constituent material layer, and an emitter cap constituent material layer are laminated in this order on the substrate;
Next, the emitter cap constituent material layer, the emitter constituent material layer, and the base constituent material layer are selectively removed to form the emitter cap layer, the emitter layer, and the base layer,
Next, at the formation position of the collector electrode in the surface direction of the substrate, the ion implantation is performed from the surface of the collector constituting material layer to the stacked body, and the collector constituting material layer is extended to the subcollector constituting material layer. Forming said conductive region to reach,
Next, the collector electrode is formed on and in contact with the collector constituent material layer,
Next, the collector constituent material layer and the subcollector constituent material layer are selectively removed to form the collector layer and the subcollector layer.
A method for manufacturing a heterojunction semiconductor device according to claim 30.   32. The collector constituent material layer is selectively removed before the ion implantation to reduce the thickness of the collector constituent material layer at the collector electrode formation position in the surface direction of the substrate. A method of manufacturing the described heterojunction semiconductor device.   The constituent material layer other than the subcollector constituent material layer is selectively etched away so that the collector electrode and the conductive region are electrically connected to the collector layer only through the subcollector layer. The method for manufacturing a heterojunction semiconductor device according to claim 1, wherein the stacked body is patterned.   34. The method of manufacturing a heterojunction semiconductor device according to claim 33, wherein the conductive region is isolated from the collector layer and the base layer.   The collector electrode is a three-layer structure of Ti / Pt / Au in which titanium, platinum and gold are laminated in this order, or Pt or Pd / Ti / Pt / Au in which platinum or palladium, titanium, platinum and gold are laminated in this order. The method of manufacturing a heterojunction semiconductor device according to claim 19, wherein the heterojunction semiconductor device is formed by a four-layer structure.   20. The method of manufacturing a heterojunction semiconductor device according to claim 19, wherein the emitter electrode and / or the base electrode is formed using tungsten W or molybdenum Mo.   The method of manufacturing a heterojunction semiconductor device according to claim 19, wherein a compound semiconductor is used as the substrate.   38. The method of manufacturing a heterojunction semiconductor device according to claim 37, wherein indium phosphide InP or gallium arsenide GaAs is used as the substrate of claim 1.   38. The method of manufacturing a heterojunction semiconductor device according to claim 37, wherein the heterojunction bipolar transistor is formed of the constituent material layer made of a compound semiconductor.   40. The method of manufacturing a heterojunction semiconductor device according to claim 39, wherein an NPN bipolar transistor is manufactured.

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