JP2006120841A - Semiconductor manufacturing method - Google Patents

Abstract

A manufacturing cost for manufacturing a high-quality semiconductor crystal having a low dislocation density is suppressed.
Using a sputtering apparatus, AlN is sputtered to a thickness of 65 nm on a main surface of a sapphire substrate 1 having a thickness of c-plane as a main surface and a buffer layer having a thickness of 250 nm made of AlN. 2 was formed, and the side wall cross section of the buffer layer 2 exposed by subsequent dry etching was used as a crystal growth nucleus. During sputtering, the temperature in the sputtering apparatus (substrate temperature) was about 430 ° C. According to such a manufacturing method, since the buffer layer 2 is formed by sputtering, the crystal growth process performed using the crystal growth furnace is not separated into a plurality of processes. Alternatively, the buffer layer can be formed by sputtering. For this reason, a high-quality semiconductor crystal having a low dislocation density can be produced at a lower cost than in the past.
[Selection] Figure 1-B

Description

The present invention relates to a semiconductor manufacturing method for obtaining a semiconductor crystal by crystal growth of a group III nitride compound semiconductor.
This manufacturing method is effective in suppressing the dislocation density of the semiconductor crystal and simultaneously reducing the manufacturing cost of the semiconductor crystal.

As a method for obtaining a semiconductor crystal having a low dislocation density by promoting lateral crystal growth using a side wall cross section as an exposed surface after etching of a semiconductor layer whose upper surface is masked as a crystal growth nucleus, for example, the following patent document The methods described in No. 1 and Patent Document 2 are known. In these conventional methods, the first crystal growth process to be performed before the mask process is performed and the second crystal growth process to be performed after the etching process by the selective etching process are performed at least twice. Therefore, it is necessary to perform a semiconductor crystal growth process.
JP 2001-185493 A JP 2001-196699 A

  However, in the crystal growth process, it takes a large cost for each process, for example, in terms of time, energy, materials, etc., to prepare all the various crystal growth conditions for executing it. It is not always an advantageous method at least in terms of cost to separate the steps and repeat heating / exhausting and exhausting each time.

  For example, in the case of the above prior art, it is necessary to take out the semiconductor wafer from the crystal growth furnace in order to perform the selective etching process, and the temperature of the semiconductor wafer at that time is unavoidable. Therefore, in order to carry out the second crystal growth step, it becomes necessary to repeat the condition setting by heating or the like again, which is not necessarily reasonable in terms of productivity.

In addition, repeated heating and cooling is likely to cause warping, distortion, and defects due to stress generated between the substrate and the semiconductor layer. This is not necessarily an advantageous procedure.
The present invention has been made to solve the above-described problems, and an object of the present invention is to suppress the manufacturing cost when manufacturing a high-quality semiconductor crystal having a low dislocation density.

In order to solve the above problems, the following means are effective.
That is, according to the first means of the present invention, in a semiconductor manufacturing process for obtaining a semiconductor crystal by crystal growth of a group III nitride compound semiconductor, Al _x Ga _1-x N ( A buffer layer forming step for forming a buffer layer comprising 0 ≦ x ≦ 1) by sputtering, a mask step for laminating an amorphous mask for preventing semiconductor crystal growth on the upper surface of the buffer layer, and a sidewall of the buffer layer An etching process for selectively etching the amorphous mask and the buffer layer so that the cross section is exposed, and In _y Al _x Ga _1-xy N (0 ≦ x ≦ 1,0) And a crystal growth step for crystal growth of a semiconductor layer having a low dislocation density consisting of ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

The material for the crystal growth substrate can be arbitrarily selected from known materials. The crystal growth method may be arbitrary, and for example, MOCVD method, HVPE method, MBE method and the like can be adopted.
In addition, since the material of the amorphous mask can be arbitrarily selected from well-known materials, the material of the amorphous mask does not necessarily need to be an insulator. For example, as an insulator material, SiN, SiO ₂ , Si _x N _y , Si _x O _y , TiO ₂ , Ti _x N _y , Ti _x O _{y and the} like can be used, and even if amorphous silicon (Si) is formed. good. As the metal material, tungsten (W) or the like can be used.

Moreover, the film formation method of an amorphous mask may use arbitrary film formation methods, for example, vacuum evaporation, PECVD method, etc. can be used.
In the above etching process, the etching may be performed until the erosion site reaches the upper surface of the crystal growth substrate, or the etching is completed at a stage shallower than that, that is, when the depth reaches the middle of the buffer layer. Alternatively, the crystal growth substrate itself may be etched.

However, although these conditions depend on various conditions such as the width of the formed stripe groove and the thickness of the buffer layer, it is desirable to etch deeper than the height of the main surface of the crystal growth substrate. It is desirable.
Moreover, the etching pattern to be formed is not limited to the above-described stripe shape, for example, and may be arbitrary, for example, a convex lattice shape, a concave lattice shape, a dot shape (island shape), a pit shape (hole shape), or the like.

  The second means of the present invention is that, in the first means, the crystal growth substrate is a sapphire substrate. The main surface of the sapphire substrate, that is, the surface on which the buffer layer is first formed may be any of the a-plane, c-plane, m-plane, r-plane, and n-plane. Further, when selecting the main surface of the crystal growth substrate, as exemplified or suggested in, for example, “JP-A-11-112029” and “JP-A-2002-246697”, etc. In consideration of the piezo electric field effect, the orientation of the main surface and the crystal growth conditions associated therewith may be determined.

The third means of the present invention is to stack the buffer layer to a thickness of 20 nm or more and 1000 nm or less in the buffer layer film forming step of the first or second means.
However, the thickness of the buffer layer is more desirably set in a range of about 20 nm to 300 nm. Further, the thickness of the buffer layer is more desirably set in the range of 20 nm to 100 nm.

The fourth means of the present invention is to set the crystal growth temperature of the buffer layer to 370 ° C. or more and 470 ° C. or less in the buffer layer film forming step of any one of the first to third means. .
However, the crystal growth temperature of this buffer layer is more desirably set in a range of about 390 ° C. to 450 ° C. The crystal growth temperature of the buffer layer is more preferably set in the range of 400 ° C to 440 ° C.

The fifth means of the present invention is to laminate the above amorphous mask in a film thickness of 20 nm or more and 1000 nm or less in the mask process of any one of the first to fourth means.
However, although the thickness of this amorphous mask depends on the material used, it is more desirable to set it in the range of about 50 nm to 500 nm. The film thickness of this amorphous mask is more desirably set in the range of 100 nm to 300 nm.

According to a sixth means of the present invention, in any one of the first to fifth means, the crystal growth step is performed by MOCVD.
By the above means of the present invention, the above-mentioned problem can be effectively or rationally solved.

The effects obtained by the above-described means of the present invention are as follows.
That is, according to the first means of the present invention, the crystal growth process is not separated into a plurality of processes, or the buffer layer can be formed by sputtering, so that the dislocation density is low and the quality is high. Semiconductor crystals can be manufactured at a lower cost than in the past.

  Further, according to the second means of the present invention, the above-mentioned semiconductor layer having a low dislocation density can be crystal-grown well, and at the same time, a crystal-growth substrate can be prepared relatively inexpensively and easily.

  Further, according to the third means of the present invention, the crystal quality of the semiconductor layer having a low dislocation density can be ensured suitably or optimally. Since the thickness of the buffer layer is an average value, if the thickness of the buffer layer is too thin, a portion having no crystal growth nuclei appears on the side wall cross section of the buffer layer. The growth of the layer may be hindered or the dislocation density of the semiconductor layer may not be suppressed. If the buffer layer is too thick, the semiconductor layer having a low desired dislocation density and the crystal growth substrate cannot act in close proximity, so that the orientation information on the crystal growth substrate based on the intermolecular force is low in the dislocation density. It is difficult for the semiconductor layer to be transmitted to the semiconductor layer, and thus it is difficult to make the semiconductor layer single crystal.

  Therefore, the thickness of the buffer layer is preferably set in a range of 20 nm to 1000 nm. More desirably, it may be set in the range of about 20 nm to 300 nm. Further, the thickness of the buffer layer is more desirably set in the range of 20 nm to 100 nm.

Further, according to the fourth means of the present invention, the buffer layer can be formed with an appropriate quality substantially equivalent to the conventional buffer layer formed by crystal growth.
The crystal growth temperature of the buffer layer is more desirably set in a range of about 390 ° C. to 450 ° C. The crystal growth temperature of the buffer layer is more preferably set in the range of 400 ° C to 440 ° C.

In addition, according to the fifth means of the present invention, it is possible to reliably ensure the function of preventing the semiconductor crystal growth of the amorphous mask, and at the same time reduce the time required for the subsequent crystal growth process. Can be suppressed.
If the film thickness of this amorphous mask is too thin, the risk of unwanted crystal growth starting from the mask cannot be sufficiently eliminated. If the amorphous mask is too thick, it takes a long time for the portions forming the semiconductor layer having a low dislocation density above the mask to be connected and integrated.

  Therefore, the thickness of the amorphous mask depends on the material used, but is more preferably set in the range of about 50 nm to 500 nm. The film thickness of this amorphous mask is more desirably set in the range of 100 nm to 300 nm.

  Further, according to the sixth means of the present invention, a desired layer (a semiconductor layer or an amorphous mask having a low dislocation density) can be formed at low cost, easily, reliably, at high speed, uniformly, or with good quality. Can do.

Note that in the present specification, "Group III nitride compound semiconductor" generally, binary, ternary, or quaternary _{"Al 1-xy Ga y In x} N; 0 ≦ x ≦ 1,0 ≦ y ≦ In addition, a semiconductor having an arbitrary mixed crystal ratio represented by the general formula of 1,0 ≦ 1-xy ≦ 1 ”is included, and a semiconductor to which a p-type or n-type impurity is added is also included in these“ This is a category of “Group III nitride compound semiconductor”.

  Further, at least a part of the above group III elements (Al, Ga, In) is replaced with boron (B), thallium (Tl), or the like, or at least a part of nitrogen (N) is phosphorus (P ), Arsenic (As), antimony (Sb), bismuth (Bi), or the like.

Moreover, as said p-type impurity (acceptor), well-known p-type impurities, such as magnesium (Mg) or calcium (Ca), can be added, for example.
As the n-type impurity (donor), for example, known n-type impurities such as silicon (Si), sulfur (S), selenium (Se), tellurium (Te), or germanium (Ge) are used. Can be added.
Further, these impurities (acceptor or donor) may be added simultaneously with two or more elements, or both types (p-type and n-type) may be added simultaneously.

Hereinafter, the present invention will be described based on specific examples.
However, the embodiments of the present invention are not limited to the following examples.

  1A to 1C are schematic cross-sectional views around the crystal growth nucleus of Example 1. FIG. A method for manufacturing a semiconductor crystal for obtaining a high-quality semiconductor crystal at low cost based on the present invention will be exemplified below with reference to FIGS.

1. Buffer Layer Film Forming Step First, by using a sputtering apparatus, AlN is sputtered onto the main surface of a sapphire substrate 1 having a thickness of 500 μm with the c-plane as the main surface, whereby a 40 nm thick buffer made of AlN is formed. Layer 2 was deposited (FIG. 1-A). At this time, the temperature in the sputtering apparatus (substrate temperature) was about 430 ° C.

The other conditions when the above sputtering was performed were as follows.
[Sputtering conditions]
Sputtering gas: Ar (8 sccm) / N ₂ (10 sccm)
DC power: 0.5 [kW]
Electrode area: 100 [cm ^2]

2. Mask Step Next, an amorphous mask 3 made of a SiO ₂ film with a thickness of 200 nm was laminated on the upper surface of the buffer layer 2 by PECVD.

3. Etching Step Thereafter, dry etching was performed in the following order (a) to (c).
(A) First, a striped resist pattern was formed on the amorphous mask 3 by photolithography. The width of the stripe-shaped resist and the interval between the resists were both about 20 μm. Thereby, it is possible to form a concavo-convex cross section having a period of 40 μm as shown in FIG.

(B) Next, stripe grooves were formed by dry etching using an RIE etching apparatus as shown in FIG. This etching was performed to a depth at which the main surface of the sapphire substrate 1 forming the bottom of the stripe groove was etched. The etching depth h (FIG. 1-A) for the sapphire substrate 1 is suitably about 0 μm to several μm.
(C) Next, the resist pattern was removed.
Through the above-described steps, a laminated substrate (1, 2, 3) having the concavo-convex shape of FIG.
Here, the side wall cross section of the buffer layer 2 becomes a crystal growth nucleus in the subsequent crystal growth.

4). Crystal Growth Step By performing crystal growth using the side wall cross section of the buffer layer 2 as a crystal growth nucleus according to the MOCVD method, the semiconductor layer 4 made of GaN having a low dislocation density is formed as shown in FIGS. Crystals were grown. However, in this crystal growth process, in order to promote growth in a desired direction, the crystal growth conditions of the semiconductor layer 4 having a low dislocation density were changed in the middle as follows.

(Crystal growth conditions during non-longitudinal growth (FIG. 1-B))
Crystal growth temperature: 990 [° C]
Crystal growth rate: 0.8 [μm / min]
Crystal growth time: 50 [min]
Supply gas flow ratio (V / III ratio): 5000

(Crystal growth conditions during vertical growth (FIG. 1-C))
Crystal growth temperature: 1050 [° C.]
Crystal growth rate: 0.6 [μm / min]
Crystal growth time: 150 [min]
Supply gas flow ratio (V / III ratio): 50000

In addition, the code | symbol 5 of FIG. 1-C has shown the site | part (junction part of the growth crystal from right and left) where the dislocation is concentrated.
According to the manufacturing method of the first embodiment described above, a high-quality semiconductor crystal having a dislocation density substantially equal to a semiconductor crystal obtained by a so-called PENDEO method that has been conventionally performed (a semiconductor layer 4 made of a GaN crystal and having a low dislocation density). ) Can be obtained by a single crystal growth step. Therefore, according to the present invention, an extremely good quality semiconductor crystal can be manufactured at a lower cost than in the past.

2-A, -B, and -C are schematic cross-sectional views around the crystal growth nucleus of the second embodiment.
In Example 2, the buffer layer 2A was formed from GaN, and then an amorphous mask 3A was formed from SiN.
After that, the etching depth h from the main surface (c surface) of the sapphire substrate 1B to the lower side was about 1 μm, and the stripe groove formation period D was about 20 μm.
The semiconductor layer 4A having a low dislocation density is made of GaN.
For example, even by such a method, the semiconductor crystal having a low dislocation density (the semiconductor layer 4A having a low dislocation density in FIG. 2-C) can be manufactured at a lower cost than the conventional one by the above-described effects of the present invention.

3-A, -B, and -C are schematic cross-sectional views around the crystal growth nucleus of Example 3. FIG.
In Example 3, the buffer layer 2B was formed from Al _0.3 Ga _0.7 N, and then an amorphous mask 3B was formed from tungsten (W).
After that, the etching depth h from the main surface (c surface) of the sapphire substrate 1B to the lower side was about 2 μm, and the stripe groove formation period D was about 10 μm.
The semiconductor layer 4B having a low dislocation density is made of GaN.

However, although the semiconductor layer 4 having a low dislocation density in Example 1 described above was formed by the MOCVD method, the semiconductor layer 4B having a low dislocation density in Example 2 was formed by a well-known HVPE method.
For example, even by such a method, the semiconductor crystal having a low dislocation density (the semiconductor layer 4B having a low dislocation density in FIG. 3C) can be manufactured at a lower cost than the conventional one by the above-described effects of the present invention.

Further, in each of the above Examples 1 to 3, the semiconductor layer (4, 4A or 4B) having a low dislocation density is formed of GaN, but instead of these GaN crystals (4, 4A or 4B), it is made of AlGaN. The semiconductor crystal may be grown in the lateral direction in substantially the same manner as the crystal growth mode of FIG. 1-B, FIG. 2-B, or FIG.
Also by these methods, due to the above-described operation of the present invention, a semiconductor crystal composed of AlGaN having a low dislocation density to the extent that it is substantially comparable to the semiconductor layer 4, 4A or 4B having a low dislocation density in each of the above-described embodiments (ie, the present invention). The semiconductor layer having a low dislocation density according to the invention can be produced at a lower cost than in the prior art.

  Further, when a hexagonal or quasi-hexagonal crystal such as a sapphire substrate is used as the crystal growth substrate, for example, the a-plane or r-plane may be used as the main plane instead of the c-plane as the main plane. The present invention provides means for inducing universal actions and effects with respect to changes in these crystal growth conditions.

  The manufacturing method of the present invention is not limited to semiconductor light-emitting elements and semiconductor light-receiving elements such as LEDs and semiconductor lasers, but is very useful for manufacturing arbitrary semiconductor devices. In addition, the manufacturing method of the present invention naturally contributes to securing the quality of a semiconductor device configured using a crystal growth substrate manufactured based on the method and reducing the manufacturing cost.

Schematic cross-sectional view around the crystal growth nucleus of Example 1 Schematic sectional view around the crystal growth nucleus of Example 1 Schematic sectional view around the crystal growth nucleus of Example 1 Schematic cross-sectional view around the crystal growth nucleus of Example 2 Schematic sectional view around the crystal growth nucleus of Example 2 Schematic cross-sectional view around the crystal growth nucleus of Example 2 Schematic cross-sectional view around the crystal growth nucleus of Example 3 Schematic cross-sectional view around the crystal growth nucleus of Example 3 Schematic cross-sectional view around the crystal growth nucleus of Example 3

Explanation of symbols

1: Sapphire substrate 2: Buffer layer (AlN)
3: Amorphous mask (SiO ₂ )
4: Semiconductor layer (GaN) with low dislocation density
5: Crystal junction (high dislocation density)

Claims (6)

A semiconductor manufacturing method for obtaining a semiconductor crystal by crystal growth of a group III nitride compound semiconductor,
A buffer layer forming step of forming a buffer layer made of Al _x Ga _1-x N (0 ≦ x ≦ 1) on the main surface of the crystal growth substrate by sputtering;
A mask process of laminating an amorphous mask on the upper surface of the buffer layer to prevent semiconductor crystal growth;
An etching step of selectively etching the amorphous mask and the buffer layer so that a sidewall cross section of the buffer layer is exposed;
A crystal for crystal growth of a semiconductor layer having a low dislocation density composed of In _y Al _x Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) using the side wall cross section as a crystal growth nucleus A method for manufacturing a semiconductor, comprising a growth step. The semiconductor manufacturing method according to claim 1, wherein the crystal growth substrate is a sapphire substrate. In the buffer layer film forming step,
The method for manufacturing a semiconductor according to claim 1, wherein the buffer layer is stacked to a thickness of 20 nm to 1000 nm. In the buffer layer film forming step,
4. The method of manufacturing a semiconductor according to claim 1, wherein a crystal growth temperature of the buffer layer is set to 370 ° C. or higher and 470 ° C. or lower. In the mask process,
5. The method of manufacturing a semiconductor according to claim 1, wherein the amorphous mask is stacked to a thickness of 20 nm or more and 1000 nm or less. 6. The method of manufacturing a semiconductor according to claim 1, wherein the crystal growth step is performed by an MOCVD method.