JP2006115140A - PLL circuit, reception tuner, communication device, lock detection method for PLL circuit - Google Patents

Abstract

An object of the present invention is to provide a PLL circuit capable of detecting a lock / unlock and performing a highly accurate feedback loop control while being small and low in noise.
A PLL circuit according to the present invention includes a reference signal generator, a frequency divider, a phase comparator, a charge pump, a loop filter, a VCO, and a PLL in a locked state. A lock detector 17 for detecting whether or not there is a PLL circuit, and the charge pump 14 is configured such that its drive current varies in accordance with an input phase difference signal. The lock detector 17 is configured to detect whether or not the PLL is in a locked state by detecting a drive current fluctuation of the charge pump 14.
[Selection] Figure 2

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit which is one of circuit blocks of a reception tuner mounted on a communication device such as a portable terminal, and more particularly to a configuration and method for detecting the lock / unlock. Is.

  The PLL circuit is one of the circuit blocks of a reception tuner mounted on a communication device such as a portable terminal, and has a function of controlling channel selection of received signals.

  FIG. 5 is a block diagram showing an example of a conventional configuration of a PLL circuit, and particularly shows a configuration in which a lock detection circuit is added as means for detecting whether or not the feedback loop is in a locked state.

  As shown in the figure, a general PLL circuit 100 includes a reference signal generator 101, a variable frequency divider 102, a first phase comparator 103, a charge pump 104, a loop filter 105, voltage control, and the like. And an oscillator 106.

  On the other hand, the lock detection circuit 200 detects a phase difference between the reference signal and the divided signal (PLL feedback signal) and generates a phase difference signal, and converts the phase difference signal into a lock detection signal. A logic determination circuit 202 that performs the above operation, a smoothing circuit 203 that obtains an integrated voltage of the lock detection signal, and a comparator 204 that outputs a comparison signal between the obtained integrated voltage and a predetermined reference voltage Vcomp. If the integrated voltage is lower than the reference voltage Vcomp, the lock state is determined, and if the integrated voltage is higher, the unlock state is determined.

As for the PLL circuit having the above configuration (or a configuration similar thereto) and its lock detection circuit, various known literature inventions can be cited (for example, see Patent Documents 1 to 3).
JP-A-5-22130 JP-A-6-112817 JP-A-7-170179

  Certainly, if a lock detection circuit 200 having the above configuration is additionally provided in the PLL circuit 100, it is possible to detect lock / unlock of the PLL circuit 100 and perform highly accurate feedback loop control.

  However, in the conventional circuit configuration shown in FIG. 5, there are many circuit blocks (second phase comparator 201, logic determination circuit 202, smoothing circuit 203, and comparator 204) to be added as the lock detection device 200. In order to reduce the size and cost of communication devices and the like, there has been a problem that the increase in chip area cannot be ignored.

  Further, the conventional lock detection circuit 200 is configured to include many digital logic circuits such as the logic determination circuit 202 of FIG. Therefore, in the conventional lock detection circuit 200, the charge / discharge current and the through current generated during the operation become noise and spurious and adversely affect other circuit blocks, resulting in malfunction of the reception tuner and associated decrease in reception sensitivity of the communication terminal. There was a risk of inviting.

  In view of the above problems, the present invention provides a PLL circuit, a receiving tuner, a communication device, and a small-sized and low-noise, capable of detecting the lock / unlock and performing high-precision feedback loop control. An object of the present invention is to provide a lock detection method for a PLL circuit.

  To achieve the above object, a PLL circuit according to the present invention includes a reference signal generator that generates a reference signal having a predetermined frequency, and a voltage-controlled oscillator that generates an oscillation signal having a variable frequency according to an input voltage signal. A frequency divider that divides the oscillation signal to generate a divided signal; a phase comparator that detects a phase difference between the reference signal and the divided signal to generate a phase difference signal; and the phase difference signal A charge pump that generates a current signal according to the frequency, a loop filter that converts the current signal into a voltage signal and inputs the voltage signal to the voltage controlled oscillator, and a lock that detects whether or not the series of feedback loops are locked A charge pump, wherein the charge pump is configured to vary its drive current in response to the phase difference signal, and the lock detector includes the charge detector. By detecting the drive current fluctuation of lamp the feedback loop is configured to detect whether or not the locked state. With such a configuration, the lock / unlock can be detected and highly accurate feedback loop control can be performed while being small and low noise.

  In the PLL circuit configured as described above, the charge pump may be configured to reduce the drive current when the current signal is not output. By adopting such a configuration, it is possible to suppress waste of drive current in the charge pump, and it is possible to perform the lock detection described above in the lock detector.

  In the PLL circuit having the above-described configuration, the lock detector includes a resistor that generates a reference voltage corresponding to a drive current of the charge pump, and a comparator that generates a comparison signal between the reference voltage and a predetermined reference voltage. It is good to have a configuration comprising With such a configuration, the lock detector can be realized with a simple configuration.

  The receiving tuner according to the present invention is configured to include any of the above PLL circuits. With such a configuration, it is possible to realize an inexpensive reception tuner with high reception sensitivity.

  Moreover, the communication apparatus according to the present invention is configured to include the reception tuner configured as described above. By adopting such a configuration, it is possible to realize an inexpensive communication device with high reception sensitivity.

  The PLL circuit lock detection method according to the present invention includes a step of generating a reference signal having a predetermined frequency, a step of generating an oscillation signal of a variable frequency according to an input voltage signal, and a frequency division of the oscillation signal. Generating a divided signal; detecting a phase difference between the reference signal and the divided signal; generating a phase difference signal; generating a current signal according to the phase difference signal; The step of converting the current signal into a voltage signal to control the oscillation frequency of the oscillation signal, and detecting the fluctuation of the drive current of the charge pump according to the phase difference signal, and whether the series of feedback loops are in a locked state And a step of detecting whether or not. With such a configuration, the lock / unlock can be detected and highly accurate feedback loop control can be performed while being small and low noise.

  As described above, if the PLL circuit, the receiving tuner, the communication device, and the lock detection method for the PLL circuit according to the present invention are used, a lock detection phase comparator and a smoothing circuit can be used without adding a lock / phase. Since unlock can be detected, it is possible to reduce the chip area and reduce the size and cost of receiving tuners and communication devices. In addition, since noise generated when the lock is detected can be reduced, it is possible to eliminate malfunctions of the reception tuner and accompanying reduction in reception sensitivity of the communication terminal.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of a communication device equipped with a PLL circuit according to the present invention, and particularly shows the periphery of the reception tuner. As shown in the figure, the receiving tuner mounted on the communication device of this embodiment includes a PLL circuit 1, an antenna 2, a low noise amplifier 3, a mixer 4, and an amplifier 5.

  In the above reception tuner, the low noise amplifier 3 amplifies the high frequency signal obtained by the antenna 2 with low noise and sends it to the mixer 4. The mixer 4 mixes a low-noise amplified high-frequency signal and a local oscillation signal generated by a voltage controlled oscillator 16 (hereinafter referred to as a VCO [Voltage Controlled Oscillator] 16) of the PLL circuit 1 and sends the mixed signal to the amplifier 5. . By such mixing processing, frequency conversion from a high frequency signal to an intermediate frequency signal and selection of a desired channel component are performed. The amplifier 5 amplifies the intermediate frequency signal generated by the mixer 4 and sends it to a subsequent detection circuit (not shown).

  FIG. 2 is a block diagram showing an embodiment of the PLL circuit 1. As shown in the figure, the PLL circuit 1 according to the present embodiment divides a reference signal generator 11 that generates a reference signal having a predetermined frequency and a local oscillation signal that is fed back from the VCO 16 to generate a divided signal. The phase difference signal (phase delay signal DW, phase advance) is detected by detecting the phase difference between the reference signal generated by the variable frequency divider 12 and the reference signal generator 11 and the frequency division signal generated by the variable frequency divider 12. Signal UP), a charge pump 14 that generates a current signal corresponding to the phase difference signal input from the phase comparator 13, and a current signal obtained by the charge pump 14 is converted into a voltage signal. The loop filter 15 that is input to the VCO 16, the VCO 16 that generates a local oscillation signal having a variable frequency according to the voltage signal input from the loop filter 15, and the series of feedbacks described above. And a lock detector 17 for detecting whether or not the loop is in a locked state, and the oscillation of the VCO 16 so that the reference signal input to the phase comparator 13 and the divided signal have the same phase. The frequency is feedback-controlled.

  FIG. 3 is a circuit diagram showing a configuration example of the charge pump 14. As shown in the figure, the charge pump 14 includes P-channel field effect transistors P1 to P8, N-channel field effect transistors N1 to N7, and a constant current source I. Further, in this figure, the circuit configuration will be described by clearly showing the drive power supply terminal T1, the phase difference signal input terminals T2 and T3, and the current signal output terminal T4 of the charge pump 14. However, these do not necessarily mean external terminals, but are merely shown as indices indicating the boundary ends between the charge pump 14 and other circuit units for the convenience of explanation.

  The drive voltage VDD of the charge pump 14 is applied to the drive power supply terminal T1 from the power supply line (power supply voltage VCC) via the lock detection unit 17. The phase delay signal DW and the phase advance signal UP are input from the phase comparator 13 to the phase difference signal input terminals T2 and T3, respectively. On the other hand, the current signal output terminal T4 is connected to the input terminal of the loop filter 15, and outputs and draws in the current signal generated by the charge pump 14.

  The sources of the transistors P1, P3, and P4 and the source and drain of the transistor P2 are all connected to the drive power supply terminal T1. The drains of the transistors P1, P3 and the gates of the transistors P2, P3, P4 are all connected to the drain of the transistor N1. Each gate of the transistors P1 and N1 is connected to the phase difference signal input terminal T2. The source of the transistor N1 is connected to the drain of the transistor N2. The source of the transistor N2 is connected to the ground line. The drain of the transistor P4 is connected to the current signal output terminal T4.

  The sources of the transistors P5, P7, and P8 and the source and drain of the transistor P6 are all connected to the drive power supply terminal T1. The drains of the transistors P5 and P7 and the gates of the transistors P6, P7, and P8 are all connected to the drain of the transistor N3. Each gate of the transistors P5 and N3 is connected to the phase difference signal input terminal T3. The source of the transistor N3 is connected to the drain of the transistor N4. The source of the transistor N4 is connected to the ground line. The drain of the transistor P8 is connected to the drain of the transistor N5. The gates of the transistors N5 and N6 are connected to each other, and are also connected to the drain of the transistor N5. The drain of the transistor N6 is connected to the current signal output terminal T4. Each source of the transistors N5 and N6 is connected to the ground line.

  The drain of the transistor N7 is connected to the drive power supply terminal T1 via the constant current source I. The source of the transistor N7 is connected to the ground line. The gates of the transistors N2, N4, and N7 are connected to each other, and are also connected to the drain of the transistor N7.

  The transistors P2 and P6 are elements that function as capacitors. By inserting the elements, overshoot of the current signal obtained at the current signal output terminal T4 can be suppressed.

  The operation of the charge pump 14 configured as described above and the drive current fluctuation will be described in detail. In the following, the drive current flowing through the power supply path to the constant current source I is i0, the drive current flowing through the power supply path to the transistors P1 to P4 is i1, and the drive current flowing through the power supply path to the transistors P5 to P8. Is defined as i2.

  When the PLL circuit 1 is in the locked state, the phase delay signal DW and the phase advance signal UP from the phase comparator 13 are both at a low level. Accordingly, the transistors P1 and P5 are turned on, the transistors N1 and N3 are turned off, the currents i1 and i2 do not flow, and the total drive current of the charge pump 14 is only the current i0.

  On the other hand, when the PLL circuit 1 is in the unlocked state, one of the phase delay signal DW and the phase advance signal UP from the phase comparator 13 is at a high level. Accordingly, since either one of the currents i1 and i2 flows in addition to the current i0, the total drive current of the charge pump 14 is either (current i0 + current i1) or (current i0 + current i2).

  Therefore, the lock detector 17 can determine the lock / unlock of the PLL circuit 1 by measuring the drive current of the charge pump 14, and can generate a lock detection signal indicating the result. The lock detector 17 of the present embodiment has an ammeter inserted in the power supply line to the charge pump 14 as means for measuring the drive current of the charge pump 14 as shown in FIGS. Thus, the measured value is read to determine whether the PLL circuit 1 is locked / unlocked.

  For example, when the current i0 is 0.2 [mA], and the currents i1 and i2 are both 0.8 [mA], the lock detector 17 has an ammeter measurement value of 0.2 [mA]. The configuration may be such that the PLL circuit 1 is determined to be in the locked state, and if it is 1.0 [mA], the PLL circuit 1 is determined to be in the unlocked state. Alternatively, an appropriate threshold value (for example, 0.5 [mA]) may be set in advance, and the locked state may be determined if the measured value of the ammeter is lower than the threshold value, and the unlocked state may be determined if the measured value is higher.

  As described above, in the PLL circuit 1 of the present embodiment, the charge pump 14 is configured such that the drive current varies according to the input phase difference signal, and the lock detector 17 drives the charge pump 14. By detecting current fluctuation, it is configured to detect whether or not the feedback loop of the PLL circuit 1 is in a locked state.

  By adopting such a configuration, it is possible to detect the lock / unlock and perform high-accuracy feedback loop control without adding a phase detector for detecting lock or a smoothing circuit separately, while being small and low noise. Can be done.

  In the charge pump 14 of the present embodiment, among the configurations in which the drive current varies according to the input phase difference signal, a configuration in which the drive current is reduced particularly when the current signal is not output is employed. . With such a configuration, the charge pump 14 can suppress waste of the drive current, and the lock detector 17 can perform the lock detection described above.

  However, the circuit configuration of the charge pump 14 is not limited to this, and according to the phase difference signal input, more functionally speaking, depending on whether the PLL circuit 1 is in the locked state, Any circuit configuration may be adopted as long as the drive current varies.

  In the above embodiment, the description has been given by taking as an example a configuration in which the drive current of the charge pump 14 is directly measured by an ammeter when detecting the lock, but the circuit configuration of the lock detector 17 is limited to this. Instead, for example, as shown in FIG. 4, a resistor R that generates a reference voltage Va corresponding to the drive current of the charge pump 14 and a connection between the reference voltage Va (the resistor R and the drive power supply end of the charge pump 14). And a comparator CMP that generates a comparison signal between the voltage obtained at the node and a predetermined reference voltage Vcomp, and the comparison signal may be sent as a lock detection signal.

  For example, the power supply voltage VCC is 3 [V], the resistance value of the resistor R is 500 [Ω], and the drive current of the charge pump 14 is 0.2 [mA] when the PLL is locked and 1 [mA when unlocked. ], The reference voltage Va is 2.9 [V] when the PLL is locked and 2.5 [V] when the PLL is unlocked. Accordingly, by setting the reference voltage Vcomp as a potential between the two (for example, 2.7 [V]), it is determined that the reference voltage Va is higher than the reference voltage Vcomp, and is locked if it is lower. It becomes possible. That is, if the comparison signal obtained by the comparator CMP is a lock detection signal, the lock / unlock of the PLL circuit 1 can be determined based on the logic state. Note that the above comparison signal only needs to have a logical state that is uniquely determined according to the level of the reference voltage Va and the reference voltage Vcomp, and is a signal that is high when the PLL is locked and low when the PLL is unlocked. Alternatively, the signal may be a low level when the PLL is locked and a high level when the PLL is unlocked.

  By adopting such a configuration, the lock detector 17 can be realized with a simple configuration including the resistor R and the comparator CMP, so that the circuit is compared with the conventional lock detection circuit (see FIG. 5). It can be greatly simplified. Therefore, compared with the conventional PLL circuit, the lock / unlock can be detected and highly accurate feedback loop control can be performed while being small and low noise.

  In the above embodiment, the configuration in which the PLL circuit 1 according to the present invention is mounted as an example of the circuit block of the reception tuner mounted in a communication device such as a portable terminal has been described. The configuration of the present invention is not limited to this, and can be widely applied to PLL circuits used for any other purpose.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  The PLL circuit according to the present invention is capable of detecting the lock / unlock and performing highly accurate feedback loop control while being small and low in noise, and therefore requires a reduction in size and an improvement in communication stability. It can be said that it is suitable for mounting to a receiving tuner or a portable terminal.

These are block diagrams which show the example of 1 structure of the communication apparatus carrying the PLL circuit which concerns on this invention. FIG. 2 is a block diagram showing an embodiment of a PLL circuit 1. FIG. 3 is a circuit diagram showing a configuration example of the charge pump 14. FIG. 5 is a circuit diagram showing another configuration example of the lock detector 17. These are block diagrams which show the example of 1 conventional structure of a PLL circuit.

Explanation of symbols

Reference Signs List 1 PLL circuit 11 Reference signal generator 12 Variable frequency divider 13 Phase comparator 14 Charge pump 15 Loop filter 16 Voltage controlled oscillator (VCO)
17 Lock detector 2 Antenna 3 Low noise amplifier 4 Mixer 5 Amplifier P1 to P8 P channel field effect transistor N1 to N7 N channel field effect transistor I Constant current source T1 Drive power supply terminal T2, T3 Phase difference signal input terminal T4 Current signal output terminal R resistance CMP comparator

Claims (6)

  A reference signal generator that generates a reference signal of a predetermined frequency, a voltage-controlled oscillator that generates an oscillation signal of a variable frequency according to an input voltage signal, and a frequency-divided signal generated by dividing the oscillation signal A phase detector, a phase comparator that detects a phase difference between the reference signal and the divided signal to generate a phase difference signal, a charge pump that generates a current signal according to the phase difference signal, and the current signal A PLL circuit comprising: a loop filter that converts a voltage signal to be input to the voltage controlled oscillator; and a lock detector that detects whether or not the series of feedback loops is in a locked state, The charge pump is configured such that the drive current varies according to the phase difference signal, and the lock detector detects the change in the drive current of the charge pump and detects the feedback loop. There PLL circuit, characterized in that it is configured to detect whether or not the locked state.   The PLL circuit according to claim 1, wherein the charge pump is configured to reduce a drive current when the current signal is not output.   The lock detector includes a resistor that generates a reference voltage corresponding to a drive current of the charge pump, and a comparator that generates a comparison signal between the reference voltage and a predetermined reference voltage. The PLL circuit according to claim 1 or 2.   A receiving tuner comprising the PLL circuit according to any one of claims 1 to 3.   A communication device comprising the reception tuner according to claim 4.   Generating a reference signal having a predetermined frequency; generating a variable frequency oscillation signal according to an input voltage signal; dividing the oscillation signal to generate a divided signal; and the reference signal Detecting a phase difference between the divided signal and generating the phase difference signal, generating a current signal corresponding to the phase difference signal, converting the current signal into a voltage signal, A step of controlling an oscillation frequency, and a step of detecting whether or not the series of feedback loops are in a locked state by detecting fluctuations in the drive current of the charge pump according to the phase difference signal. A lock detection method for a PLL circuit.

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