JP2006114651A - Manufacturing method of semiconductor device - Google Patents

Abstract

A method of manufacturing a semiconductor device having a semiconductor metal alloy layer having uniform and good characteristics is provided.
A method of manufacturing a semiconductor device according to the present invention includes: (a) a step of forming a gate insulating layer 20 above a semiconductor layer 10; and (b) forming a gate electrode 22 above the gate insulating layer. (C) forming a resist layer in a predetermined region above the semiconductor layer; (d) amorphizing the surface 40 of the semiconductor layer in a region not covered with the resist layer; e) forming a metal layer 32a above the semiconductor layer; and (f) performing a heat treatment to react the amorphous semiconductor layer with the metal layer.
[Selection] Figure 4

Description

  The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method of manufacturing a semiconductor device in which a semiconductor metal alloy layer such as a silicide layer is formed in order to reduce resistance.

  2. Description of the Related Art In recent years, with the miniaturization of MOS transistors, a technique for forming a semiconductor metal alloy layer typified by a silicide layer is known in order to reduce the resistance of a source region and a drain region. In a semiconductor device having such a semiconductor metal alloy layer, a technique for forming a semiconductor metal alloy layer having uniform and good characteristics is desired in response to a demand for further improvement of characteristics.

  An object of the present invention is to provide a method of manufacturing a semiconductor device having a semiconductor metal alloy layer having uniform and good characteristics.

A method for manufacturing a semiconductor device according to the present invention includes:
(A) forming a gate insulating layer above the semiconductor layer;
(B) forming a gate electrode above the gate insulating layer;
(C) forming a resist layer in a predetermined region above the semiconductor layer;
(D) amorphizing the surface of the semiconductor layer in a region not covered with the resist layer;
(E) forming a metal layer above the semiconductor layer;
(F) The process which heat-processes in order to make the said semiconductor layer made amorphous and the said metal layer react.

  According to this aspect, since the amorphous semiconductor layer and the metal layer are reacted, a semiconductor metal alloy layer having uniform and good characteristics can be formed.

In the method for manufacturing a semiconductor device according to the present invention,
In the step (f), heat treatment can be performed at 530 ° C. to 560 ° C.

  According to the semiconductor device manufacturing method of the present invention, the semiconductor layer and the metal layer are formed by heat treatment at 530 ° C. to 560 ° C. in order to amorphize the surface of the semiconductor layer in a desired region before forming the metal layer. By reacting, a semiconductor metal alloy layer can be formed.

In the method for manufacturing a semiconductor device according to the present invention,
The semiconductor layer is a silicon layer;
In the step (f), a silicide layer can be formed by performing a heat treatment.

  According to the method for manufacturing a semiconductor device according to the present invention, the surface of the semiconductor layer in a desired region is amorphized before forming the metal layer, so that the silicide layer is formed in a self-aligned manner only in the desired region. be able to.

In the method for manufacturing a semiconductor device according to the present invention,
In the step (f),
A first silicide layer is formed in the amorphized region;
A second silicide layer is formed in a region that has not been amorphized;
After step (f)
(G) removing the unreacted metal layer and the second silicide layer;
Can further be included.

  The amorphous semiconductor layer is more likely to react with the metal layer than the crystalline region that has not been amorphized. Therefore, the second silicide layer is thinner than the first silicide layer and contains a large amount of the amorphized silicide compound, so that the selection ratio with the first silicide layer can be obtained. Therefore, the second silicide layer can be removed simultaneously with the metal layer, for example, by wet etching, and the first silicide layer can be left. Therefore, even if the second silicide layer is formed, it can be removed without increasing the number of steps.

A method for manufacturing a semiconductor device according to the present invention includes:
After step (g)
(H) a step of performing a heat treatment;
Can further be included.

In the method for manufacturing a semiconductor device according to the present invention,
In the step (d), the semiconductor layer in a region not covered with the resist layer can be made amorphous by performing ion implantation. Thereby, the semiconductor layer can be easily made amorphous.

  Hereinafter, an example of the present embodiment will be described.

1. Semiconductor Device FIG. 1 is a cross-sectional view schematically showing a semiconductor device 100 according to the present embodiment.

  The semiconductor device 100 includes a first MOS transistor 110, a second MOS transistor 120, and an element isolation region 12 formed on the semiconductor layer 10. The first MOS transistor 110 and the second MOS transistor 120 are formed on the gate insulating layer 20 formed on the semiconductor layer 10, the gate electrode 22 formed on the gate insulating layer 20, and the sidewall of the gate electrode 22. The sidewall insulating layer 24, the drain region 14, and the source region 26 are provided.

  Further, the first MOS transistor 110 has a silicide layer 32 (first silicide layer). The silicide layer 32 is formed above the source region 26, above the drain region 14, and above the gate electrode 22. On the other hand, the second MOS transistor 120 does not have a silicide layer.

  In the semiconductor device 100 according to the present embodiment, the first MOS transistor 110 and the second MOS transistor 120 are formed on the semiconductor layer 10. The first MOS transistor 110 and the second MOS transistor 120 may be formed on the semiconductor layer formed on the layer.

  In this embodiment, the semiconductor device 100 in which two transistors are formed is described as an example. However, the number of transistors may be one or two or more. It suffices to have both a region for forming a silicide layer and a region for not forming a silicide layer. As described above, a method for manufacturing a semiconductor device having both a region where a silicide layer is formed and a region where a silicide layer is not formed will be described below.

2. Semiconductor Device Manufacturing Method A semiconductor device manufacturing method according to the present embodiment will be described with reference to FIGS.

  (1) First, the semiconductor layer 10 is prepared. In this embodiment, the semiconductor layer 10 is used. Instead, an SOI substrate, a substrate on which a silicon layer is formed on sapphire, a quartz substrate, a substrate on which a silicon layer is formed on a glass substrate, or the like is used. May be. As a material of the semiconductor layer 10, for example, Si, SiGe, GaAs, InP, GaP, GaN, or the like can be used. In the present embodiment, Si is used as an example of the semiconductor layer 10.

  Next, as shown in FIG. 2, an element isolation region 12 is formed on the semiconductor layer 10. The element isolation region 12 is formed by a known method such as a LOCOS method or an STI method.

  Next, as shown in FIG. 2, an impurity of a predetermined conductivity type is introduced into the semiconductor layer 10 to adjust the threshold value, and the gate insulating layer 20 and the gate electrode 22 are formed. As the gate insulating layer 20, for example, a silicon oxide film can be formed by a thermal oxidation method. Next, a conductive layer (not shown) for the gate electrode 22 is formed on the gate insulating layer 20. As the conductive layer, for example, a polycrystalline silicon layer can be deposited to a thickness of about 200 nm. Then, the gate electrode 22 is formed by patterning this conductive layer by a known lithography and etching technique. Next, an impurity of a predetermined conductivity type is introduced into the semiconductor layer 10 for forming the LDD region.

  Next, as shown in FIG. 2, sidewall insulating layers 24 are formed on the side surfaces of the gate electrode 22. The sidewall insulating layer 24 can be formed, for example, as follows. An insulating layer (not shown) is formed over the entire surface of the semiconductor layer 10. As the insulating layer, a silicon nitride film, a silicon oxide film, or a stacked film thereof can be used. Thereafter, the sidewall insulating layer 24 can be formed on the side surface of the gate electrode 22 by performing anisotropic etching on the insulating layer.

  Next, as shown in FIG. 2, the source region 26 and the drain region 14 are formed.

  An impurity of a predetermined conductivity type is introduced into the semiconductor layer 10 by a known method in a region for forming the source region 26 and the drain region 14. Thereafter, heat treatment is performed to activate the introduced impurities.

  (2) Next, as shown in FIG. 4, an amorphous semiconductor layer 40 is formed.

  An example of a method for forming the amorphous semiconductor layer 40 will be described. First, a resist is applied on the entire surface of the semiconductor layer 10. Next, the resist is patterned by a lithography method as shown in FIG. 3 to form a resist layer R1 in a predetermined region. The predetermined region for forming the resist layer R1 is a region other than the region where the silicide layer is to be formed.

  Next, by ion-implanting the semiconductor layer 10 using the resist layer R1 as a mask, the surfaces of the semiconductor layer 10 and the gate electrode 22 are amorphized to form the amorphous semiconductor layer 40. Here, argon, germanium, silicon, arsenic, or the like is ion-implanted. After the ion implantation, the resist layer R1 is removed.

  (3) Next, as shown in FIG. 4, a metal layer 32 a is formed on the entire surface above the semiconductor layer 10. As the metal layer 32a, for example, about 20 nm of Ti is deposited by sputtering. The metal layer 32a may be Co, Ni, Mo, Pt, or Rb. Note that the metal layer 32 a is also formed above the gate electrode 22.

  In order to prevent oxidation of Ti, a titanium nitride layer may be deposited as a barrier film on the metal layer 32a by sputtering or the like.

  (4) Next, the first-stage heat treatment is performed to cause the metal layer 32a, the semiconductor layer 10, and the gate electrode 22 to undergo a silicidation reaction, thereby forming the silicide layer 32. The silicide layer 32 is made of a silicide compound such as titanium silicide, cobalt silicide, nickel silicide, and molybdenum silicide. After the first heat treatment, for example, titanium silicide of C49 crystal is formed.

  This first stage heat treatment can be performed, for example, using the RTA method at a processing temperature of 530 ° C. to 560 ° C. in a nitrogen or rare gas atmosphere for 120 seconds. In the amorphized region, the bonding between silicon atoms in the semiconductor layer 10 is weaker than that in the non-amorphized region, so that the silicidation reaction is favorably performed. On the other hand, at this processing temperature, the silicidation reaction hardly occurs even in the region where the semiconductor layer 10 is exposed in the non-amorphous region, but even if it occurs, the silicide compound Only a thin amorphous silicide layer 34 (second silicide layer) is formed.

Next, the unreacted metal layer 32a and the amorphous silicide layer 34 (second silicide layer) are removed. The unreacted metal layer 32a can be removed by wet etching using, for example, a mixed solution of NH ₄ OH, H ₂ O ₂ , and H ₂ O.

  In the step (3), when the titanium nitride layer is deposited, the titanium nitride layer is also removed at the same time.

  (5) Next, the silicide layer 32 is made more stable by performing the second stage heat treatment. The second stage heat treatment is performed, for example, at a processing temperature of 750 ° C. to 850 ° C. under a nitrogen atmosphere for 30 seconds. As a result, the titanium silicide of the C49 crystal undergoes a phase transition to the titanium silicide of the C54 crystal having a lower resistance.

  The semiconductor device 100 according to this embodiment can be formed by the above steps.

  According to the manufacturing method of the semiconductor device according to the present embodiment, the semiconductor device 100 having the silicide layer 32 can be formed. Usually, the first heat treatment is performed at 600 ° C. to 700 ° C. for silicidation reaction. However, in the method of manufacturing the semiconductor device according to the present embodiment, since the formation region of the silicide layer 32 is made amorphous in advance, even if the first heat treatment is performed at a temperature lower than 530 ° C. to 560 ° C. Layer 10 can be silicided.

  Further, according to the method of manufacturing the semiconductor device according to the present embodiment, the semiconductor device 100 including the first MOS transistor 110 having the silicide layer 32 and the second MOS transistor 120 not having the silicide layer 32. Can be formed. Usually, when manufacturing such a semiconductor device, a hard mask such as silicon oxide is used in a region where the silicide layer is not formed. However, the silicide layer may be non-uniform due to a residue after removing the hard mask. is there. Further, when the hard mask itself is formed non-uniformly, the silicide layer becomes non-uniform. Further, when removing the hard mask, etching may occur up to the sidewall insulating layer of the gate electrode. Thus, when a hard mask is used, it is difficult to form a good silicide layer.

  Therefore, according to the manufacturing method of the semiconductor device according to the present embodiment, the silicide layer 32 can be formed in a self-aligned manner only in the amorphized region, so that it is necessary to form a hard mask in the region where the silicide layer is not formed. There is no. In addition, since a resist layer is formed in a region that is not amorphous, not a hard mask, a mask forming process and a removing process are easy. Therefore, there is no problem based on the hard mask described above, and a good silicide layer can be easily formed.

3. Experimental Example The sheet resistance of the semiconductor device obtained by the manufacturing method of the present embodiment was measured.

  FIG. 6 is a diagram showing the dependence of the sheet resistance of the silicide layer on the first stage heat treatment temperature. The horizontal axis represents the first stage heat treatment temperature, and the vertical axis represents the sheet resistance (Ω / □) of the semiconductor device.

  The semiconductor device used in the experiment was obtained by depositing 150 チ タ ン titanium nitride as the barrier film and 200 チ タ ン titanium as the metal layer in the step (3). The heat treatment time for the first stage was 120 seconds, the heat treatment temperature for the second stage was 810 ° C., and the heat treatment time was 30 seconds. The sheet resistances of the semiconductor device made amorphous by ion implantation and the semiconductor device not ion-implanted were measured. It can be determined that the silicide layer is formed when the sheet resistance is less than 100Ω / □.

  According to FIG. 6, in the semiconductor device subjected to ion implantation, it is confirmed that a silicide layer is formed because the first stage heat treatment temperature is 530 ° C. or more and the sheet resistance is less than 100Ω / □. It was done. In addition, in the semiconductor device in which ion implantation was not performed, it was confirmed that a silicide layer was formed because the sheet resistance began to decrease at a temperature at which the first stage heat treatment temperature exceeded 560 ° C.

  Therefore, according to FIG. 6, the temperature range in which the silicide layer is not formed in the non-amorphized region and the silicide layer is formed in the amorphous region is 530 ° C. to 560 ° C.

  Further, when a silicide layer is formed in an amorphous region, the sheet resistance of the silicide layer is more preferably 10 Ω / □ or less, and in this embodiment, it corresponds to about 540 ° C. to about 560 ° C. To do. A silicide layer having good characteristics can be formed in this temperature range.

  The present invention is not limited to the above-described embodiment, and can be modified within the scope of the gist of the present invention.

1 is a cross-sectional view schematically showing a semiconductor device according to an embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. Sectional drawing which shows typically the manufacturing process of the semiconductor device concerning this Embodiment. The figure which shows the dependence with respect to the heat processing temperature of the 1st step | paragraph of the sheet resistance of a silicide layer.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 Semiconductor layer, 12 Element isolation region, 14 Drain region, 20 Gate insulating layer, 22 Gate electrode, 24 Side wall insulating layer, 26 Source region, 32 Silicide layer, 34 Amorphous silicide layer, 40 Amorphous semiconductor layer, 100 Semiconductor device, 110 First MOS transistor, 120 Second MOS transistor

Claims (6)

(A) forming a gate insulating layer above the semiconductor layer;
(B) forming a gate electrode above the gate insulating layer;
(C) forming a resist layer in a predetermined region above the semiconductor layer;
(D) amorphizing the surface of the semiconductor layer in a region not covered with the resist layer;
(E) forming a metal layer above the semiconductor layer;
(F) performing a heat treatment to react the amorphous semiconductor layer and the metal layer;
A method for manufacturing a semiconductor device, comprising: In claim 1,
In the step (f), a heat treatment is performed at 530 ° C. to 560 ° C. In claim 1 or 2,
The semiconductor layer is a silicon layer;
In the step (f), a silicide layer is formed by performing a heat treatment. In any one of Claims 1 thru | or 3,
In the step (f),
A first silicide layer is formed in the amorphized region;
A second silicide layer is formed in a region that has not been amorphized;
After step (f)
(G) removing the unreacted metal layer and the second silicide layer;
A method for manufacturing a semiconductor device, further comprising: In claim 4,
After step (g)
(H) a step of performing a heat treatment;
A method for manufacturing a semiconductor device, further comprising: In any of claims 1 to 5,
In the step (d), the semiconductor device is made amorphous by performing ion implantation on a semiconductor layer in a region not covered with the resist layer.

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