JP2006190988A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device which comprises an ohmic electrode having a high impurity activation rate and high electron mobility and having small contact resistance and small parasitic resistance in a contact layer. <P>SOLUTION: The semiconductor device comprises an active layer 13 formed on a substrate 11, a superlattice layer 14 formed on the active layer 13, and an ohmic electrode 15 formed on the superlattice layer 14. The superlattice layer 14 is formed by alternately laminating a first thin film and a second thin film made of a semiconductor having a polarization characteristic different from the first thin film and larger in band gap than the first thin film. An interface region as a contact between the upper surface of the first thin film and the lower surface of the second thin film or an interface region as a contact between the lower surface of the first thin film and the upper surface of the second thin film is doped with impurities. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device using a group III-V nitride semiconductor, and more particularly to a transistor used for a high frequency device.

Group III-V nitride semiconductors, that is, gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and a general formula of (In _x Al _1-x ) _y Ga _1-y N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1)) has a wide band gap and a direct transition band structure. In addition to applications to optical elements that utilize such physical characteristics, applications to electronic devices that utilize the features of high breakdown electric field and saturated electron velocity are also being studied. In particular, a heterojunction field effect transistor using a two-dimensional electron gas (hereinafter referred to as 2DEG) that appears at the interface between Al _x Ga _1-x N and GaN epitaxially grown on a semi-insulating substrate ( Hetero-junction Field Effect Transistor (hereinafter abbreviated as HFET) is being developed as a high-output high-frequency device.

  In these nitride semiconductor devices, in order to improve device characteristics, it is necessary to reduce parasitic resistance components such as contact resistance and channel resistance in the semiconductor device as much as possible. When current is carried by electrons, it is necessary to form an ohmic contact from the outside in a region where electrons are conducted.

  As a conventional ohmic contact, for example, aluminum (Al), nickel (Ni), gold (Au), etc. are laminated with titanium (Ti) as a lowermost layer formed on a nitride semiconductor layer such as AlGaN. A multilayer metal thin film is used.

  After forming a multilayer metal thin film having Ti as the lowermost layer on the nitride semiconductor layer, heat treatment at about 500 ° C. to 900 ° C. is performed, so that Ti and nitrogen in the multilayer metal thin film are near the upper surface of the nitride semiconductor layer. (N) reacts. N is extracted by the reaction, and vacancies are formed in the region near the top surface of the nitride semiconductor layer, so that the metallicity of the region near the top surface of the nitride semiconductor layer is increased. Further, the reaction between Ti and the nitride semiconductor produces compounds such as Ga, Al, Ti, and TiN, and these products are stable due to further reaction between Al, Ni, Au, and the like in the multilayer metal thin film. A metal compound is formed. As a result, a low resistance ohmic contact can be obtained.

  By using a contact layer made of n-type doped GaN or the like as high as possible in the nitride semiconductor layer forming the ohmic electrode, the contact can be further reduced.

There has also been proposed a method for improving the electron concentration by making the contact layer a superlattice structure made of n-doped AlGaN and GaN (see, for example, Patent Documents 1 to 3).
JP 2005-26671 A JP-A-9-172164 JP-A-11-112472 Edited by Junichi Nishizawa, Nobuo Mikoshiba, “Physics of Semiconductors [Revised Edition]”, Baifukan, 1991, p. 109-110

However, in the conventional ohmic contact, when n-type doped GaN or the like is used as the contact layer, the lower limit of the contact resistance is the impurity activation rate (5 × 10 ¹⁸ cm ^{−3 to} 3 × 10 ¹⁹ cm ⁻³ ). This is because the highest carrier concentration in the contact layer is defined by the activation rate of the impurities.

  In addition, when the superlattice made of n-type doped AlGaN and GaN is used as the contact layer, the interface between AlGaN and GaN where electrons are accumulated is also doped with impurities, resulting in the impurities. Electron scattering occurs, and the mobility of electrons decreases. As a result, there is a problem that contact resistance and parasitic resistance cannot be sufficiently reduced.

  Further, when an n-type ohmic electrode formed using this method is used as a source electrode and a drain electrode of an HFET, a negative piezoelectric charge appears at the boundary between the electron transit layer of the HFET made of AlGaN or the like and the superlattice. There is also a problem that the potential barrier against electrons at the interface between the heavily doped GaN layer of the superlattice and the AlGaN which is the electron transit layer rises due to piezo charges, resulting in an increase in contact resistance and parasitic resistance.

  An object of the present invention is to solve the above-mentioned conventional problems, and to realize a semiconductor device having an ohmic electrode with a high impurity activation rate and electron mobility in a contact layer and a small contact resistance and parasitic resistance. And

  In order to achieve the above object, the present invention has a semiconductor device including a superlattice layer doped only at a part of the interface.

  A semiconductor device according to the present invention includes a first nitride semiconductor layer formed on a substrate, a first nitride semiconductor layer formed on the first nitride semiconductor layer, a first thin film, and polarization characteristics of the first thin film. And a superlattice layer in which second thin films having a larger band gap than the first thin film are alternately stacked, and an electrode formed on the superlattice layer, A doped region doped with an impurity is formed in an interface region where the upper surface of the first film and the lower surface of the second thin film are in contact with each other or in an interface region where the lower surface of the first thin film and the upper surface of the second thin film are in contact with each other Features.

  According to the semiconductor device of the present invention, the interface region where the upper surface of the first thin film and the lower surface of the second thin film are in contact or the interface region where the lower surface of the first thin film and the upper surface of the second thin film are in contact Since the doped region doped with is formed, unlike the case where the entire superlattice layer is doped with impurities, scattering of electrons due to the impurities hardly occurs. Accordingly, it is possible to greatly reduce the contact resistance and the parasitic resistance without reducing the electron mobility.

  In the semiconductor device of the present invention, negative polarization charges are preferably generated in the interface region where the doped region is formed. With such a configuration, a high concentration of electrons can be generated by the polarization charge, and a decrease in electron mobility resulting from electron scattering by impurities can be prevented.

  The semiconductor device of the present invention preferably further includes a second nitride semiconductor layer formed between the superlattice layer and the electrode and doped with impurities. With this configuration, the potential barrier for electrons at the interface between the electrode and the superlattice layer can be reduced. In addition, electrons can be induced in the vicinity of the interface between the second nitride semiconductor layer and the superlattice layer, and depletion in the vicinity of the interface can be prevented. Accordingly, the contact resistance can be further reduced.

In the semiconductor device of the present invention, the value of the ratio of the thickness of the second thin film to the thickness of the first thin film is preferably different between the upper part and the lower part of the superlattice layer. In this case, in the upper part of the superlattice layer, the first thin film is thicker than the second thin film, and in the lower part of the superlattice layer, the second thin film has the first film thickness. It is preferably thicker than the thickness of the thin film.
With this configuration, the potential barrier for electrons at the interface between the electrode and the superlattice layer can be reduced, and the potential barrier for electrons at the interface between the superlattice layer and the first nitride semiconductor layer can be reduced. Therefore, the contact resistance can be further reduced.

  In the semiconductor device of the present invention, the thickness of the second thin film is preferably larger than the thickness of the first thin film. In this case, the value of the ratio between the thickness of the second thin film and the thickness of the first thin film is preferably greater than 1 and 6 or less.

  In the semiconductor device of the present invention, the sum of the thickness of the first thin film and the thickness of the second thin film is preferably 2 nm or more and 15 nm or less.

In the semiconductor device of the present invention, the impurity concentration in the doped region is preferably 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less.

  In the semiconductor device of the present invention, the doped region is preferably the first delta doped region. With such a configuration, the potential barrier against electrons at the interface between the superlattice layer and the first nitride semiconductor layer can be reduced, so that the contact resistance can be further reduced.

  In the semiconductor device of the present invention, the second delta doped region is formed in a region where the distance from the interface between the first nitride semiconductor layer and the superlattice layer in the first nitride semiconductor layer is 0.1 nm or more and 1 μm or less. Is preferably formed. With such a configuration, the potential barrier against electrons at the interface between the superlattice layer and the first nitride semiconductor layer can be reduced, so that the contact resistance can be further reduced.

  In the semiconductor device of the present invention, the first thin film is preferably made of gallium nitride, and the second thin film is preferably made of aluminum gallium nitride.

  In the semiconductor device of the present invention, the first nitride semiconductor layer is formed by stacking a plurality of semiconductor films, and the semiconductor film formed in the uppermost layer of the plurality of semiconductor films is made of aluminum gallium nitride. preferable. With such a configuration, the potential barrier against electrons at the interface between the superlattice layer and the first nitride semiconductor layer can be reduced, so that the contact resistance can be further reduced.

  The semiconductor device of the present invention further includes a gate electrode formed on the first nitride semiconductor layer, and the first nitride semiconductor layer has a band gap compared to the channel layer and the channel layer stacked on each other. The superlattice layer is selectively formed in regions on both sides of the gate electrode on the first nitride semiconductor layer, and the electrode is a superlattice layer sandwiching the gate electrode. Preferably, the source electrode is formed on one of the superlattice layers and the drain electrode is formed on the other superlattice layer.

  In this case, the semiconductor device preferably further includes a high-concentration impurity layer that is formed between each superlattice layer and the barrier layer, has the same composition as the barrier layer, and has a higher impurity concentration than the barrier layer. . With such a configuration, it becomes easy to form a recess structure of the gate electrode.

  In this case, each superlattice layer preferably has an opening exposing the first nitride semiconductor layer, and the source electrode and the drain electrode are preferably formed in contact with the sidewall of the opening. In addition, each superlattice layer may have a recessed portion in which a part thereof is dug, and the source electrode and the drain electrode may be formed in contact with the sidewall of the recessed portion.

  According to the semiconductor device of the present invention, it is possible to realize a semiconductor device including an ohmic electrode having a high impurity activation rate and electron mobility in the contact layer and a small contact resistance and parasitic resistance.

(First embodiment)
A first embodiment according to the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional configuration of the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device of the first embodiment is an active layer made of gallium nitride (GaN) formed on a substrate 11 made of sapphire with a buffer layer 12 made of aluminum nitride (AlN) interposed. 13, a superlattice layer 14 formed on the active layer 13 and functioning as a contact layer, and an ohmic electrode 15 formed on the superlattice layer 14.

As shown in FIG. 2, the superlattice layer 14 includes a first thin film 14A made of GaN having a thickness of 2.3 nm and an aluminum gallium nitride (Al _x Ga _1-x N, thickness of 4.7 nm). In the embodiment, it is a multilayer film in which the second thin films 14B having x = 0.26) are alternately stacked for seven periods. As shown in FIG. 2, in the superlattice layer 14, in the interface region where the upper surface of the first thin film 14A and the lower surface of the second thin film 14B are in contact with each other, Si as an n-type impurity is 1 × 10 ¹⁹ cm ^−3. An n-type doped region 22 is formed which is doped at a concentration of.

Figure 3 shows a bottom Ec and the Fermi level E _F of the conduction band in the superlattice layer 14. As shown in FIG. 3, at the interface between the first thin film 14A made of GaN and the second thin film 14B made of Al _0.26 Ga _0.74 N having a larger band gap than GaN, the first thin film 14A and the first thin film 14A A polarization charge is generated in accordance with the spontaneous polarization difference and the piezoelectric polarization difference with the second thin film 14B. In this embodiment, positive polarization charge + a is generated at the interface 21A where the upper surface of the first thin film 14A and the lower surface of the second thin film 14B are in contact, and the upper surface of the second thin film 14B and the first thin film 14A Negative polarization charge -a is generated at the interface 21B in contact with the lower surface.

Inside the superlattice layer 14, many free charges composed of electrons are generated by being induced by polarization charges. The generated free charge is accumulated at the interface 21A where the upper surface of the first thin film 14A and the lower surface of the second thin film 14B are in contact. In the present embodiment, the region including the interface 21B where the negative polarization charge -a occurs is doped with Si, which is an n-type impurity. Since the region doped with Si has a large energy difference between the donor level E _D and the Fermi level E _F , the donor activation rate can be particularly increased. As a result, the concentration of charges accumulated at the interface 21A is 1 × 10 ¹³ cm ⁻² . This is equivalent to 5 × 10 ¹⁹ cm ⁻³ in terms of volume concentration, and is 2 × 10 ¹⁹ cm ^{−3 to} 3 × 10 ¹⁹ cm ^−3, which is the upper limit concentration of charge achieved by normal n-type doping. Is over.

  On the other hand, in this embodiment, the region including the interface 21A where the positive polarization charge + a is generated is not doped. For this reason, the electron mobility in the horizontal plane in the epitaxially grown layer is not scattered and reduced by the impurities, and the electrical resistance is not increased by the impurities. Also, regarding the movement of electrons in the direction perpendicular to the epitaxially grown layer, the second thin film 14B is as thin as 4.7 nm, and the piezoelectric field generated in the second thin film 14B further reduces the effective potential barrier. Accordingly, the electrons contributing to conduction in the first thin film 14A easily tunnel through the potential barrier of the second thin film 14B, so that the electrical resistance does not increase.

  The reason why a very high activation rate of electrons is obtained will be described below. In general, in consideration of electron statistics in an impurity semiconductor, the concentration nD of electrons occupying a donor level is expressed by Equation 1.

  Here, ND is an impurity concentration, fD is an electron distribution function, ED is a donor level, EF is a Fermi level, kB is a Boltzmann constant, and T is an absolute temperature (see Non-Patent Document 1). When Equation 1 is used, since the concentration of the donor activated by releasing free electrons is expressed by ND-nD, the activation rate η of the donor impurity is expressed by Equation 2.

  From Equation 2, it can be seen that as the difference between the donor level and the Fermi level increases, the second term on the rightmost side becomes asymptotic to 0 and the activation rate approaches 1 (ie, 100% activation). Therefore, a high activation rate can be obtained by increasing the difference between the donor level and the Fermi level. This can also be applied to acceptor impurities by changing the sign.

As shown in FIG. 3, the difference between the donor level E _D and the Fermi level E _F is larger than any other part of the superlattice layer 14 at the interface 21B where the negative polarization charge −a appears. By the difference between the donor level E _D and the Fermi level E _F is doped with impurities so as to include the largest surface 21B, it is possible to increase the activation rate of the donor impurity. As a result, the electron concentration can be increased and the parasitic resistance can be reduced.

  Hereinafter, a method for manufacturing the superlattice layer 14 in which only the region including the interface 21B is doped and the region including the interface 21A is not doped will be described. On the substrate 11 made of sapphire, a buffer layer 12 made of AlN having a thickness of 200 nm is formed in a chamber by a known method, and then an active layer 13 made of GaN having a thickness of 3000 nm is epitaxially grown.

Next, Al _0.26 Ga _0.74 N is epitaxially grown on the active layer 13 by supplying trimethylaluminum as an aluminum source, supplying trimethylgallium as a gallium source, and supplying ammonia as a nitrogen source. After the Al _0.26 Ga _0.74 N is epitaxially grown, a Si to Al _0.26 Ga _0.74 N to about 1 × 10 ¹⁹ cm ^-3 doping by further supplying silane (SiH _4). Thereafter, the supply of trimethylaluminum is stopped, and then the supply of SiH ₄ is stopped to grow GaN.

As a result, a second thin film 14B made of Al _0.26 Ga _0.74 N having a thickness of 4.7 nm and a first thin film 14A made of GaN having a thickness of 2.3 nm are formed on the active layer 13. . Next, the Al raw material is supplied again to start the growth of Al _0.26 Ga _0.74 N. The superlattice layer 14 is obtained by alternately repeating the growth of Al _0.26 Ga _0.74 N and the growth of GaN seven times.

  In the method of manufacturing the superlattice layer 14 of the present embodiment, Si is supplied from the middle of the growth of the second thin film 14B, and the supply of Si is stopped while the first thin film 14A is being grown. Therefore, the region near the interface where the second thin film 14B switches to the first thin film 14A is doped with Si, but the region near the interface where the first thin film 14A switches to the second thin film 14B is not doped. .

Even if the film thickness of the first thin film 14A and the film thickness of the second thin film 14B are too thin or too thick, the effect of reducing the contact resistance is lowered. This is due to the following reason. If the first thin film 14A is made too thin, the region for accumulating electrons becomes narrow, and the electron concentration decreases. On the other hand, if the second thin film 14B is made too thin, the volume of the n-type Al _0.26 Ga _0.74 N layer becomes small and the amount of electron supply decreases. On the other hand, if the second thin film is too thick, electrons cannot tunnel through the second thin film, and the resistance in the vertical direction of the superlattice layer 14 increases.

  FIG. 4 shows the result of measuring the relationship between the source resistance and the sum of the thickness of the first thin film 14A and the thickness of the second thin film 14B for the HFET having the superlattice layer 14 of this embodiment. Show. In FIG. 4, the horizontal axis represents the sum of the film thickness of the first thin film 14A and the film thickness of the second thin film 14B. The value of the ratio of the thickness of the first thin film 14A to the thickness of the second thin film 14B (14B / 14A) was 2. As shown in FIG. 4, the source resistance was the smallest when the sum of the film thicknesses was around 7 nm. This is because if the first thin film 14A and the second thin film 14B are too thin, electrons cannot be supplied and stored sufficiently. If the film is too thick, electrons are formed by the second thin film 14B. This is because the potential barrier cannot be tunneled. Therefore, the sum of the thickness of the first thin film 14A and the thickness of the second thin film 14B is preferably 2 nm or more and 15 nm or less.

  FIG. 5 shows a film of the second thin film 14B in the HFET having the superlattice layer 14 of the present embodiment, with the sum of the film thickness of the first thin film 14A and the film thickness of the second thin film 14B being constant. The result of measuring the change in source resistance when the thickness is changed is shown. In FIG. 5, the sum of the thickness of the first thin film 14A and the thickness of the second thin film 14B is fixed at 7 nm. As shown in FIG. 5, the source resistance value decreased as the thickness of the second thin film 14B increased. This is presumably because the n-type AlGaN layer, which is an electron supply layer, is increased by increasing the thickness of the AlGaN layer, and the electron concentration is increased. However, when the thickness of the second thin film 14B approaches 7 nm, the thickness of the first thin film 14A becomes too thin, and the value of the source resistance increases. This is presumably because the region where electrons are accumulated becomes narrow and the electron concentration decreases.

  From the above results, it is preferable that the film thickness of the second thin film 14B is larger than the film thickness of the first thin film 14A, and the value of the film thickness ratio (14B / 14A) is greater than 1 and 6 or less. It is preferable. The thickness of the first thin film is preferably 1 nm or more.

  The first thin film 14A and the second thin film 14B are GaN and AlGaN, respectively, and the active layer 13 includes AlGaN having the same Al composition as the second thin film 14B or AlGaN having an Al composition different from that of the second thin film 14B. In addition, when this film is in contact with the superlattice layer 14, the effect of reducing the resistance is particularly great.

  Furthermore, the thickness of the first thin film 14A and the thickness of the second thin film 14B may be changed in the superlattice layer 14, respectively. For example, immediately below the ohmic electrode 15, the effective band gap can be reduced above the superlattice layer 14 by increasing the thickness of the first thin film 14 </ b> A. Thereby, the contact resistance between the ohmic electrode 15 and the superlattice layer 14 can be reduced. Also in this case, the potential barrier at the interface between the superlattice layer 14 and the active layer is formed below the superlattice layer 14 by making the thickness of the second thin film 14B larger than the thickness of the first thin film 14A. Can be reduced.

  When the first thin film 14A is GaN and an n-type doped GaN layer is provided between the superlattice layer 14 and the ohmic electrode 15, the film of the first thin film 14A is formed above the superlattice layer 14. The effect of making the thickness thicker than the thickness of the second thin film 14B is great.

In this embodiment, since AlGaN and GaN having a pseudomorphic crystal structure epitaxially grown are used as the first thin film 14A and the second thin film 14B, the first thin film 14A and the second thin film 14B A piezopolarization difference occurred between them. Even when a relaxed crystal is used, there is a difference in spontaneous polarization between the first thin film 14A and the second thin film 14B, so that there is an interface between the first thin film 14A and the second thin film 14B. A free charge corresponding to spontaneous polarization is induced. In this case, the charge amount is about 5 × 10 ¹² cm ⁻² , but the same effect as in the present embodiment can be obtained by reducing the thickness of each thin film to about half.

The composition of the first thin film 14A and the second thin film 14B is such that the polarization characteristics of the first thin film 14A and the second thin film 14B are different, and the band gap of the second thin film 14B is the band of the first thin film 14A. What is necessary is just to make it large compared with a gap. For example, when GaN is used for the first thin film 14A and Al _x Ga _1-x N is used for the second thin film 14B, an electron confinement effect is expected by setting the value of x to about 0.01 to 1. It is preferable because it is possible.

Further, not only the combination of GaN and AlGaN, but the general formula is represented by (In _x Al _1-x ) _y Ga _1-y N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1). Two compounds having different band gaps selected from the compounds can be used in combination. A general formula in which only piezo polarization is dominant is a band selected from Pb _x ZyTi _z O _2-xyz (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1). It is also possible to use two compounds having different gaps in combination.

  Note that the n-type doping method in the superlattice layer 14 may be delta doping that can increase the doping concentration to the limit and at the same time reduce the thickness of the doping layer to the limit. By setting the position of the delta doped layer in the vicinity of the interface between the AlGaN layer and the GaN layer where negative piezo-polarized charges appear, the same effect can be obtained and the contact resistance can be reduced.

  Further, as shown in FIG. 6, a delta doped layer 18 may be provided below the interface between the superlattice layer 14 and the active layer 13. With such a configuration, the potential barrier against electrons at the interface between the superlattice layer 14 and the active layer 13 can be reduced, and the contact resistance can be reduced. The position where the delta doped layer 18 is provided is preferably a position where the distance from the interface between the superlattice layer 14 and the active layer 13 in the active layer 13 is 0.1 nm or more and 1 μm or less.

  In the present embodiment, the active layer 13 has been described as a GaN layer, but it may be another nitride semiconductor or a stacked body of a plurality of semiconductor films. Further, although the example in which the lowermost layer of the superlattice layer 14 is the second thin film 14B and the uppermost layer is the first thin film 14A has been shown, the order of stacking may be reversed. Furthermore, as long as they are laminated alternately, the uppermost layer and the lowermost layer may both be the first thin film 14A or the second thin film 14B.

  In this embodiment, since negative polarization charges are generated at the interface 21B where the upper surface of the second thin film 14B and the lower surface of the first thin film 14A are in contact, the region in the vicinity of the interface 21B is doped. However, depending on the configuration of the semiconductor device, negative polarization charges are generated at the interface 21A where the upper surface of the first thin film 14A and the lower surface of the second thin film 14B are in contact. In this case, the region near the interface 21A is doped.

(First modification of the first embodiment)
Below, the 1st modification of 1st Embodiment which concerns on this invention is demonstrated with reference to drawings. FIG. 7 shows a cross-sectional configuration of a semiconductor device according to a first modification of the first embodiment. In FIG. 7, the same components as those in FIG.

  As shown in FIG. 7, the semiconductor device of this embodiment further includes an n-type doped layer 16 made of GaN having a thickness of 20 nm between the superlattice layer 14 and the ohmic electrode 15.

The n-type doped layer 16 is a heavily doped layer doped with Si having a concentration of 1 × 10 ¹⁹ cm ⁻³ . By providing the n-type doped layer 16, the potential barrier at the interface between the ohmic electrode 15 and the superlattice layer 14 can be reduced, so that the contact resistance can be reduced.

  In this case, since the n-type doped layer 16 is made of GaN, the contact resistance can be further reduced by making the uppermost layer of the superlattice layer 14 a thin film made of GaN. Further, in the upper portion of the superlattice layer 14, the first thin film 14A is thicker than the second thin film 14B, so that the n-type doped layer 16 and the superlattice layer 14 The difference in the band gap at the interface can be reduced. As a result, the contact resistance can be further reduced. In the lower part of the superlattice layer 14, the contact resistance between the superlattice layer 14 and the active layer 13 is increased by making the thickness of the second thin film 14B larger than the thickness of the first thin film 14A. It can be suppressed.

(Second modification of the first embodiment)
Below, the 2nd modification of 1st Embodiment which concerns on this invention is demonstrated with reference to drawings. FIG. 8 shows a cross-sectional configuration of a semiconductor device according to a second modification of the first embodiment. In FIG. 8, the same components as those in FIG.

As shown in FIG. 8, the semiconductor device of this embodiment is characterized in that the active layer 13 is composed of a channel layer 13A made of GaN and a barrier layer 13B made of Al _0.26 Ga _0.74 N.

  Since the semiconductor device of this embodiment can use 2DEG having high concentration and high mobility generated at the interface between the channel layer 13A and the barrier layer 13B, it can be operated at high speed.

(Third Modification of First Embodiment)
Below, the 3rd modification of 1st Embodiment which concerns on this invention is demonstrated with reference to drawings. FIG. 9 shows a cross-sectional configuration of a semiconductor device according to a third modification of the first embodiment. In FIG. 9, the same components as those of FIG.

As shown in FIG. 9, the semiconductor device of this embodiment further includes an n-type doped layer 16 made of GaN between the superlattice layer 14 and the ohmic electrode. Further, the active layer 13 is constituted by a channel layer 13A made of GaN and a barrier layer 13B made of Al _0.26 Ga _0.74 N.

  In the first embodiment and each modification, only the ohmic electrode portion of the semiconductor device is shown. By providing a Schottky electrode on the first nitride semiconductor layer, a Schottky barrier diode or an HFET can be formed. It is also possible to form a heterojunction bipolar transistor using an ohmic electrode as a base electrode.

(Second Embodiment)
A second embodiment according to the present invention will be described below with reference to the drawings. FIG. 10 shows a cross-sectional configuration of the semiconductor device according to the second embodiment. As shown in FIG. 10, the semiconductor device of this embodiment is an HFET. An active layer 33 is formed on a substrate 31 made of sapphire with a buffer layer 32 made of AlN interposed. The active layer 33 includes a channel layer 33A made of GaN having a thickness of 3 μm and a barrier layer 33B made of Al _0.26 Ga _0.74 N having a thickness of 25 nm formed on the channel layer 33A.

  On the barrier layer 33B, a gate electrode 37 made of palladium silicon alloy (PdSi), palladium (Pd), gold (Au), or the like is formed. A source electrode 35A and a drain electrode 35B made of a laminate of titanium and aluminum are formed with an n-type doped layer 39, a superlattice layer 34, and an n-type doped layer 36 interposed therebetween.

The high-concentration n-type doped layer 39 is made of Al _0.26 Ga _0.74 N having a thickness of 20 nm, and Si is doped at a concentration of 7 × 10 ¹⁸ cm ⁻³ .

The superlattice layer 14 is formed by alternately laminating seven periods of first thin films 34A made of GaN having a thickness of 2.4 nm and second thin films 34B made of Al _0.26 Ga _0.74 N having a thickness of 4.6 nm. Multilayer film. The region in the vicinity of the interface where the upper surface of the second thin film 34B and the lower surface of the first thin film 34A are in contact is doped with Si, which is an n-type impurity, at a concentration of about 1 × 10 ¹⁹ cm ⁻³ .

The n-type doped layer 36 is made of GaN having a thickness of 20 nm, and Si is doped at a concentration of 1 × 10 ¹⁹ cm ⁻³ .

  In the semiconductor device of this embodiment, a region including an interface where negative piezo-polarized charges are generated is doped with Si that is an n-type impurity. Since the region doped with Si has a large energy difference between the donor level and the Fermi level, the donor activation rate can be particularly increased. Thereby, a high concentration charge can be accumulated at the interface where the positive polarization charge is generated. Further, since the region near the interface where the positive polarization charge is generated is not doped, the electron mobility in the horizontal plane is not scattered by the impurity and does not decrease with respect to the epi, and the electrical resistance increases due to the impurity. Absent. As a result, the contact resistance of the source electrode 35A and the drain electrode 35B can be significantly reduced.

In the semiconductor device of this embodiment, the channel layer 33A can be regarded as a cap layer. The laminated structure of Al _0.26 Ga _0.74 N and GaN constituting the superlattice layer 14 has an electron layer that can be transported in a direction parallel to the channel having a much higher concentration than conventional. Therefore, the parasitic resistance can be greatly reduced as compared with the conventional semiconductor device.

Below, the manufacturing method of the semiconductor device of this embodiment is demonstrated with reference to drawings. FIG. 11 shows the method of manufacturing the semiconductor device according to this embodiment in the order of steps. First, as shown in FIG. 11A, after a buffer layer 32 made of AlN is formed on a substrate 31 made of sapphire by a known method, a channel layer 33A made of GaN having a thickness of 3 μm and a thickness of 33 A are formed. A barrier layer 33B made of 25 nm Al _0.26 Ga _0.74 N is sequentially formed. Subsequently, 20 nm of Al _0.26 Ga _0.74 N is deposited on the barrier layer 33B while doping silicon to form a high-concentration n-type doped layer 39.

Next, a second thin film 34B made of Al _0.26 Ga _0.74 N having a thickness of 4.7 nm and a first thin film 34A made of GaN having a thickness of 2.4 nm are formed on the high-concentration n-type doped layer 39. Are alternately epitaxially grown for seven periods to form a superlattice layer 34. At this time, Si is doped in a region near the interface where the upper surface of the second thin film 34B and the lower surface of the first thin film 34A are in contact. Subsequently, an n-type doped layer 36 made of GaN having a thickness of 20 nm is formed by a metal organic chemical growth (MOCVD) method or the like.

  Next, as shown in FIG. 11B, Ti and Al are sequentially deposited on the n-type doped layer 36, and lift-off is performed to form the source electrode 35A and the drain electrode 35B. The source electrode 35A and the drain electrode 35B are alloyed by heat treatment.

  Next, as shown in FIG. 11C, a mask 41 having an opening is formed from a resist, and a gate recess is formed by a method such as reactive ion etching (ICP-RIE) using inductively coupled plasma. Subsequently, a gate electrode 37 made of palladium silicon alloy (PdSi), palladium (Pd), gold (Au) or the like is formed.

  When the gate recess is formed, the heavily doped n-type doped layer 39 formed in the lowermost layer of the superlattice layer 34 and the relatively lightly doped barrier layer 33B have a highly doped n-type. The doped layer 39 has a higher etch rate. Therefore, the etching automatically stops at the interface between the high concentration n-type doped layer 39 and the barrier layer 33B. As a result, since the high-concentration n-type doped layer 39 does not remain in the gate electrode formation region, it is possible to reproducibly form a gate electrode with little leakage current. In addition, since the gate recess depth can be made uniform in the substrate surface, in-plane uniformity of characteristics such as threshold voltage is improved.

  The semiconductor device according to the present embodiment includes the n-type doped layer 36 between the source electrode 35A and the drain electrode 35B and the superlattice layer 34. However, the source electrode 35A and the drain electrode 35B are included in the superlattice layer 34. It may be formed directly on. Further, depending on the etching conditions, the high-concentration n-type doped layer 39 may not be provided.

(One Modification of Second Embodiment)
A modification of the second embodiment according to the present invention will be described below with reference to the drawings. FIG. 12 shows a cross-sectional configuration of a semiconductor device according to a modification of the second embodiment. In FIG. 12, the same components as those in FIG.

  As shown in FIG. 12, in the semiconductor device of this modification, the n-type doped layer 36, the superlattice layer 34, and the high-concentration n-type doped layer 39 have openings, and the source electrode 35A and the drain electrode 35B have openings. It is embedded in the part. The source electrode 35A and the drain electrode 35B are in contact with the superlattice layer 34 on the side wall of the opening. This makes it possible to use a high-concentration electron layer that can be transported in a direction parallel to the channel of the superlattice layer 34, and thus parasitic resistance can be reduced.

  Although the example in which the source electrode 35A and the drain electrode 35B penetrate the superlattice layer 34 and is in contact with the barrier layer 33B is shown, the source electrode 35A and the drain electrode 35B do not necessarily have to be in contact with the barrier layer 33B. The superlattice layer 34 may be partially left below the source electrode 35A and the drain electrode 35B.

  In each embodiment and its modification, an n-type semiconductor has been described, but a p-type semiconductor can also be formed by a similar method.

  The semiconductor device according to the present invention can realize a semiconductor device including an ohmic electrode having a high impurity activation rate and electron mobility in a contact layer, and having low contact resistance and parasitic resistance, and uses a III-V nitride semiconductor. It is useful as a transistor used in a semiconductor device, particularly a high-frequency circuit.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. 1 is an enlarged sectional view showing a superlattice layer portion of a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the state of the potential in the superlattice layer part of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a graph which shows the correlation of the structure of the superlattice layer which concerns on the 1st Embodiment of this invention, and source resistance. It is a graph which shows the correlation of the structure of the superlattice layer which concerns on the 1st Embodiment of this invention, and source resistance. It is sectional drawing which shows another example of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the semiconductor device which concerns on the 1st modification of the 1st Embodiment of this invention. It is sectional drawing which shows the semiconductor device which concerns on the 2nd modification of the 1st Embodiment of this invention. It is sectional drawing which shows the semiconductor device which concerns on the 3rd modification of the 1st Embodiment of this invention. It is sectional drawing which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of 2nd Embodiment of this invention to process order. It is sectional drawing which shows the semiconductor device which concerns on the 1st modification of the 2nd Embodiment of this invention.

Explanation of symbols

11 substrate 12 buffer layer 13 active layer 13A channel layer 13B barrier layer 14 superlattice layer 14A first thin film 14B second thin film 15 ohmic electrode 16 n-type doped layer 17 gate electrode 18 delta doped layer 21A interface 21B interface 22 doped region 31 Substrate 32 Buffer layer 33 Active layer 33A Channel layer 33B Barrier layer 34 Superlattice layer 34A First thin film 34B Second thin film 35A Source electrode 35B Drain electrode 36 N-type doped layer 37 Gate electrode 39 High-concentration n-type doped layer 41 Mask

Claims (17)

A first nitride semiconductor layer;
The first thin film and the second thin film having polarization characteristics different from those of the first thin film and having a band gap larger than that of the first thin film are alternately formed on the first nitride semiconductor layer. A superlattice layer formed by lamination;
An electrode formed on the superlattice layer,
Dope doped with impurities in an interface region where the upper surface of the first thin film and the lower surface of the second thin film are in contact or an interface region where the lower surface of the first thin film and the upper surface of the second thin film are in contact A semiconductor device characterized in that a region is formed.   The semiconductor device according to claim 1, wherein negative polarization charges are generated in an interface region where the doped region is formed.   3. The semiconductor device according to claim 1, further comprising a second nitride semiconductor layer formed between the superlattice layer and the electrode and doped with impurities.   The value of the ratio between the thickness of the second thin film and the thickness of the first thin film is different between the upper part and the lower part of the superlattice layer. 2. A semiconductor device according to item 1.   In the upper part of the superlattice layer, the thickness of the first thin film is thicker than that of the second thin film, and in the lower part of the superlattice layer, the thickness of the second thin film is the first thickness. The semiconductor device according to claim 4, wherein the semiconductor device is thicker than the thickness of the thin film.   5. The semiconductor device according to claim 1, wherein a film thickness of the second thin film is larger than a film thickness of the first thin film.   The semiconductor device according to claim 6, wherein a value of a ratio between the thickness of the second thin film and the thickness of the first thin film is greater than 1 and 6 or less.   8. The semiconductor according to claim 1, wherein the sum of the thickness of the first thin film and the thickness of the second thin film is 2 nm or more and 15 nm or less. apparatus. 9. The semiconductor device according to claim 1, wherein an impurity concentration of the doped region is 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²¹ cm ⁻³ or less.   The semiconductor device according to claim 1, wherein the doped region is a first delta doped region.   A second delta doped region is formed in a region where the distance from the interface between the first nitride semiconductor layer and the superlattice layer in the first nitride semiconductor layer is not less than 0.1 nm and not more than 1 μm. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.   12. The semiconductor device according to claim 1, wherein the first thin film is made of gallium nitride, and the second thin film is made of aluminum gallium nitride. The first nitride semiconductor layer is formed by laminating a plurality of semiconductor films,
The semiconductor device according to claim 12, wherein a semiconductor film formed in an uppermost layer of the plurality of semiconductor films is made of aluminum gallium nitride. A gate electrode formed on the first nitride semiconductor layer;
The first nitride semiconductor layer includes a channel layer stacked on each other and a barrier layer having a larger band gap than the channel layer,
The superlattice layer is selectively formed in regions on both sides of the gate electrode on the first nitride semiconductor layer,
The electrode is a source electrode formed on one of the superlattice layers sandwiching the gate electrode, and a drain electrode formed on the other superlattice layer, The semiconductor device according to any one of claims 1 to 12.   The high-concentration impurity layer further formed between each of the superlattice layers and the barrier layer, having the same composition as the barrier layer and a higher impurity concentration than the barrier layer. 14. The semiconductor device according to 14. Each superlattice layer has an opening that exposes the first nitride semiconductor layer;
The semiconductor device according to claim 14, wherein the source electrode and the drain electrode are respectively formed in contact with the side wall of the opening. Each superlattice layer has a recess dug in part,
The semiconductor device according to claim 14, wherein the source electrode and the drain electrode are formed in contact with a sidewall of the recess.

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