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JP2006190774A - Laminated ceramic electronic component - Google Patents

Laminated ceramic electronic component Download PDF

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JP2006190774A
JP2006190774A JP2005000775A JP2005000775A JP2006190774A JP 2006190774 A JP2006190774 A JP 2006190774A JP 2005000775 A JP2005000775 A JP 2005000775A JP 2005000775 A JP2005000775 A JP 2005000775A JP 2006190774 A JP2006190774 A JP 2006190774A
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electronic component
large area
portions
multilayer ceramic
small area
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Katsuyuki Uchida
勝之 内田
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Capacitors (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a laminated ceramic electronic component capable of suppressing variation in electrostatic capacitance caused by the slippage of a laminate. <P>SOLUTION: Capacitor conductor patterns 3, 4 are composed of large areas 11, 21 arranged in a line in a lengthwise direction (Y direction) of a ceramic green sheet 2; narrow areas 12, 22; and small width portions 13, 23 arranged between the portions 11, 21 and the portions 12, 22 to connect the portions 11, 21 to the portions 12, 22, respectively. The area 11 is arranged on a portion of the conductor pattern 3 where the pattern 3 is connected to an external electrode, and the area 21 is arranged on a portion of the conductor pattern 4 where the pattern 4 is connected to an external electrode. The portion 12 is formed at the end of the conductor pattern 3, and the portion 22 is formed at the end of the conductor pattern 4. The portions 12, 22 are overlapped on the portions 21, 11, respectively, in a plan view in the portions 21, 11 which the portions 12, 22 oppose each other via the ceramic green sheet 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、積層セラミック電子部品、特に、コンデンサやバリスタやサーミスタやLCフィルタなどの積層セラミック電子部品に関する。   The present invention relates to a multilayer ceramic electronic component, and more particularly to a multilayer ceramic electronic component such as a capacitor, a varistor, a thermistor, or an LC filter.

従来より、積層セラミックコンデンサには、内部電極の位置ずれによって静電容量が変化してしまうという問題がある。すなわち、図9の水平断面模式図に示すような同一形状の内部電極72,73を有したコンデンサ71において、内部電極72,73の長さ方向(Y方向)のずれおよび幅方向(X方向)のずれが生じると、対向する内部電極72,73の重なり面積に増減が生じるので、静電容量が変化してしまう。なお、符号76,77は外部電極である。   Conventionally, a multilayer ceramic capacitor has a problem that the capacitance changes due to the displacement of the internal electrodes. That is, in the capacitor 71 having the internal electrodes 72 and 73 having the same shape as shown in the horizontal cross-sectional schematic diagram of FIG. 9, the displacement of the internal electrodes 72 and 73 in the length direction (Y direction) and the width direction (X direction). When the deviation occurs, the overlapping area of the opposed internal electrodes 72 and 73 increases and decreases, and the capacitance changes. Reference numerals 76 and 77 are external electrodes.

そこで、この対策として、特許文献1の図12や特許文献2に記載のコンデンサが知られている。図10に示すように、このコンデンサ81は、幅の異なる内部電極82,83を有したものであって、積層時に内部電極82,83相互間に多少の幅方向(X方向)の位置ずれが生じても、内部電極82,83の重なり面積を一定に維持することができ、静電容量変化が生じない。なお、符号86,87は外部電極である。   Therefore, as a countermeasure, the capacitors described in FIG. 12 of Patent Document 1 and Patent Document 2 are known. As shown in FIG. 10, this capacitor 81 has internal electrodes 82 and 83 having different widths, and there is a slight displacement in the width direction (X direction) between the internal electrodes 82 and 83 during lamination. Even if it occurs, the overlapping area of the internal electrodes 82 and 83 can be kept constant, and the capacitance does not change. Reference numerals 86 and 87 are external electrodes.

しかしながら、内部電極82,83相互間に長さ方向(Y方向)の位置ずれが生じると、内部電極82,83の重なり面積に増減が生じ、静電容量が変化してしまう。また、内部電極82の先端部が対向する内部電極83からはみ出しているので、外部電極87との間の静電容量が大きく発生し、位置ずれによる静電容量の変化が大きくなってしまう。さらに、形状が異なる内部電極82,83を奇数枚で積層した場合には、静電容量のばらつきが大きくなるという問題も発生する。
特開平6−84689号公報 特開平8−273973号公報
However, if a positional shift in the length direction (Y direction) occurs between the internal electrodes 82 and 83, the overlapping area of the internal electrodes 82 and 83 increases and decreases, and the capacitance changes. In addition, since the tip portion of the internal electrode 82 protrudes from the opposing internal electrode 83, a large capacitance is generated between the internal electrode 82 and the external electrode 87, and a change in the capacitance due to the displacement is increased. Furthermore, when odd-numbered internal electrodes 82 and 83 having different shapes are stacked, there is a problem that the variation in capacitance increases.
Japanese Patent Laid-Open No. 6-84690 JP-A-8-273973

そこで、本発明の目的は、積層ずれによる静電容量のばらつきを抑えることができる積層セラミック電子部品を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer ceramic electronic component that can suppress variations in capacitance due to misalignment.

前記目的を達成するため、本発明に係る積層セラミック電子部品は、複数のセラミック層と内部導体を積み重ねて構成した積層体と、積層体の両端部に形成され、かつ内部電極と交互に接続する一対の外部電極とを有する積層セラミック電子部品であって、内部電極は、大面積部と、小面積部と、大面積部および小面積部の間に配置されて大面積部と小面積部を繋ぐ幅狭部とからなり、大面積部は内部電極の外部電極との接続部側に配置されるとともに、小面積部は内部電極の先端部に形成され、大面積部は平面視でセラミック層を介して対向する小面積部と重なっていることを特徴とする。   In order to achieve the above object, a multilayer ceramic electronic component according to the present invention is formed by stacking a plurality of ceramic layers and internal conductors, and formed at both ends of the multilayer body and alternately connected to internal electrodes. A multilayer ceramic electronic component having a pair of external electrodes, wherein the internal electrodes are arranged between the large area part, the small area part, and the large area part and the small area part. The large area portion is arranged on the side of the internal electrode connected to the external electrode, the small area portion is formed at the tip of the internal electrode, and the large area portion is a ceramic layer in plan view. It overlaps with the small area part which opposes via.

積層セラミック電子部品としては、例えば積層セラミックコンデンサやLCフィルタなどがある。   Examples of the multilayer ceramic electronic component include a multilayer ceramic capacitor and an LC filter.

そして、大面積部および小面積部は略矩形状であり、大面積部は小面積部よりも電極幅が広く、かつ電極長が長いことが好ましい。   The large area portion and the small area portion are substantially rectangular, and the large area portion preferably has a wider electrode width and a longer electrode length than the small area portion.

また、小面積部は、平面視で、セラミック層を介して対向する大面積部内で該大面積部と重なっていることが好ましい。   Moreover, it is preferable that a small area part has overlapped with this large area part in the large area part which opposes via a ceramic layer by planar view.

また、幅狭部は、平面視で、セラミック層を介して対向する幅狭部と互いに重なっている場合と、重なっていない場合のいずれであってもよい。   Further, the narrow portion may be either in the case of overlapping with the narrow portion facing through the ceramic layer in a plan view or in the case of not overlapping.

本発明によれば、大面積部と小面積部が重なっているので、内部電極の位置がずれても大面積部内で小面積部が移動し、静電容量変化を抑制することができる。そして、内部電極の先端側に小面積部が形成されているので、内部電極の先端側が、対向する内部電極からはみ出して外部電極との間に静電容量が大きく生じ、位置ずれによる静電容量変化が大きくなることも抑制できる。さらに、内部電極の形状が全て同一に形成されるので、内部電極を奇数枚で積層した場合の静電容量のばらつきを抑制することができる。   According to the present invention, since the large area portion and the small area portion overlap each other, even if the position of the internal electrode is shifted, the small area portion moves within the large area portion, and the capacitance change can be suppressed. And since the small area part is formed in the front end side of an internal electrode, the front end side of an internal electrode protrudes from the opposing internal electrode, and an electrostatic capacitance produces large between external electrodes, and the electrostatic capacitance by position shift An increase in change can also be suppressed. Furthermore, since the internal electrodes are all formed in the same shape, it is possible to suppress variation in capacitance when the internal electrodes are stacked in an odd number.

以下に、本発明に係る積層セラミック電子部品の実施例について添付図面を参照して説明する。   Embodiments of a multilayer ceramic electronic component according to the present invention will be described below with reference to the accompanying drawings.

図1に示すように、積層セラミックコンデンサ1は、コンデンサ導体パターン3,4をそれぞれ設けたセラミックグリーンシート2と、予め導体パターンを設けない外層用セラミックグリーンシート2等で構成されている。   As shown in FIG. 1, the multilayer ceramic capacitor 1 includes a ceramic green sheet 2 provided with capacitor conductor patterns 3 and 4, an outer layer ceramic green sheet 2 provided with no conductor pattern in advance, and the like.

セラミックグリーンシート2は、磁性体や誘電体の原料粉末を溶剤に分散させてセラミックスラリを調整し、これをドクターブレード法により厚さ30μmのシート状に成形することにより得る。次に、セラミックグリーンシート2のそれぞれにスクリーン印刷法によって、コンデンサ導体パターン3、4を形成する。   The ceramic green sheet 2 is obtained by dispersing a powder of magnetic material or dielectric material in a solvent to adjust a ceramic slurry, and forming this into a 30 μm thick sheet by the doctor blade method. Next, capacitor conductor patterns 3 and 4 are formed on each of the ceramic green sheets 2 by screen printing.

コンデンサ導体パターン3,4はそれぞれ、セラミックグリーンシート2の長さ方向(Y方向)に一列に配置された大面積部11,21と、小面積部12,22と、大面積部11,21および小面積部12,22の間に配置されて大面積部11,21と小面積部12,22を繋ぐ幅狭部13,23と、引出し部14,24とからなる。大面積部11はコンデンサ導体パターン3の外部電極32(後述)との接続部側に配置され、大面積部21はコンデンサ導体パターン4の外部電極33(後述)との接続部側に配置される。小面積部12はコンデンサ導体パターン3の先端部に形成され、小面積部22はコンデンサ導体パターン4の先端部に形成されている。   The capacitor conductor patterns 3 and 4 have large area portions 11 and 21, small area portions 12 and 22, large area portions 11 and 21, which are arranged in a line in the length direction (Y direction) of the ceramic green sheet 2, respectively. The narrow area parts 13 and 23 which are arrange | positioned between the small area parts 12 and 22 and connect the large area parts 11 and 21 and the small area parts 12 and 22 and the drawer parts 14 and 24 are comprised. The large area portion 11 is disposed on the connection portion side of the capacitor conductor pattern 3 with the external electrode 32 (described later), and the large area portion 21 is disposed on the connection portion side of the capacitor conductor pattern 4 with the external electrode 33 (described later). . The small area portion 12 is formed at the tip portion of the capacitor conductor pattern 3, and the small area portion 22 is formed at the tip portion of the capacitor conductor pattern 4.

そして、大面積部11,21および小面積部12,22は略矩形状であり、大面積部11,21は小面積部12,22よりも電極幅が広く(X方向に広く)、かつ電極長が長い(Y方向に長い)。   The large area portions 11 and 21 and the small area portions 12 and 22 have a substantially rectangular shape, and the large area portions 11 and 21 have a wider electrode width (wider in the X direction) than the small area portions 12 and 22, and electrodes Long length (long in the Y direction).

本実施例の場合、大面積部11,21の幅方向(X方向)の寸法は300μmで、長さ方向(Y方向)の寸法は380μmである。小面積部12,22の幅方向(X方向)の寸法は230μmで、長さ方向(Y方向)の寸法は310μmである。幅狭部13,23の幅方向(X方向)の寸法は120μmで、長さ方向(Y方向)の寸法は80μmである。   In this embodiment, the large area portions 11 and 21 have a width direction (X direction) dimension of 300 μm and a length direction (Y direction) dimension of 380 μm. The dimension in the width direction (X direction) of the small area portions 12 and 22 is 230 μm, and the dimension in the length direction (Y direction) is 310 μm. The dimensions of the narrow portions 13 and 23 in the width direction (X direction) are 120 μm, and the dimension in the length direction (Y direction) is 80 μm.

コンデンサ導体パターン3の引出し部14はシート2の左辺に露出している。コンデンサ導体パターン4の引出し部24はシート2の右辺に露出している。本実施例の場合、引出し部14,24の幅方向(X方向)の寸法は200μmで、長さ方向(Y方向)の寸法は100μmである。   The lead portion 14 of the capacitor conductor pattern 3 is exposed on the left side of the sheet 2. The lead portion 24 of the capacitor conductor pattern 4 is exposed on the right side of the sheet 2. In the case of the present embodiment, the width direction (X direction) of the drawer portions 14 and 24 is 200 μm, and the length direction (Y direction) is 100 μm.

各セラミックグリーンシート2はコンデンサ導体パターン3,4が交互になるように積み重ねられ、さらに、上下に外層用セラミックグリーンシート2が配置された後、圧着して積層体ブロックとする。積層体ブロックは所定のサイズにカットされた後、一体的に焼成される。これにより、図2に示す積層体31とされる。   The ceramic green sheets 2 are stacked so that the capacitor conductor patterns 3 and 4 are alternately arranged. Further, after the ceramic green sheets 2 for outer layers are arranged on the upper and lower sides, the ceramic green sheets 2 are pressure-bonded to form a laminate block. The laminated body block is cut into a predetermined size and then fired integrally. Thereby, it is set as the laminated body 31 shown in FIG.

次に、積層体31の両端部に導電ペーストを塗布し、焼き付けすることにより外部電極32,33を形成する。外部電極32はコンデンサ導体パターン3の引出し部14に電気的に接続され、外部電極33はコンデンサ導体パターン4の引出し部24に電気的に接続されている。   Next, the external electrodes 32 and 33 are formed by applying and baking a conductive paste on both ends of the laminate 31. The external electrode 32 is electrically connected to the lead portion 14 of the capacitor conductor pattern 3, and the external electrode 33 is electrically connected to the lead portion 24 of the capacitor conductor pattern 4.

以上の構成からなる積層コンデンサ1は、図3に示すように、大面積部11,21が平面視でセラミックグリーンシート2を介して対向する小面積部22,12と重なっている。具体的には、小面積部12,22はそれぞれ、平面視で、セラミックグリーンシート2を介して対向する大面積部21,11内で大面積部21,11と重なっている。また幅狭部13は、平面視で、セラミックグリーンシート2を介して対向する幅狭部23と互いに重なっている。なお、ここで平面視とは、セラミックグリーンシート2の積み重ね方向から透視することをいう。   In the multilayer capacitor 1 having the above configuration, as shown in FIG. 3, the large area portions 11 and 21 are overlapped with the small area portions 22 and 12 facing each other with the ceramic green sheet 2 in plan view. Specifically, each of the small area portions 12 and 22 overlaps the large area portions 21 and 11 in the large area portions 21 and 11 that are opposed to each other with the ceramic green sheet 2 in plan view. Further, the narrow portion 13 overlaps with the narrow portion 23 facing each other with the ceramic green sheet 2 in plan view. Here, the plan view refers to seeing through from the stacking direction of the ceramic green sheets 2.

大面積部11,21と小面積部22,12が重なっているので、コンデンサ導体パターン3,4の位置が図4のように幅方向(X方向)にずれても、また、図5のように長さ方向(Y方向)にずれても、あるいは、図6のように幅方向(X方向)および長さ方向(Y方向)の両方にずれても、大面積部11,21内で小面積部22,12が移動するだけであり、静電容量変化を抑制することができる。   Since the large area portions 11 and 21 and the small area portions 22 and 12 overlap each other, even if the positions of the capacitor conductor patterns 3 and 4 are shifted in the width direction (X direction) as shown in FIG. Even if they are displaced in the length direction (Y direction) or in both the width direction (X direction) and the length direction (Y direction) as shown in FIG. Only the area portions 22 and 12 move, and a change in capacitance can be suppressed.

すなわち、本実施例に示す構造であれば、積層ずれが生じた場合に対向面積が変動するのは幅狭部13,23の部分だけであり、対向面積変動を小さくできるので静電容量の変動を抑えられる。   In other words, in the structure shown in this embodiment, when the stacking deviation occurs, the facing area varies only in the narrow portions 13 and 23, and the facing area variation can be reduced. Can be suppressed.

なお、ずれなく積層した場合の設計としては、幅狭部13が対向する幅狭部23と、幅狭部13,23の長さ方向(Y方向)の半分の長さが長さ方向(Y方向)にずれて重なるようにすることが望ましい。このように設計することで、長さ方向(Y方向)の両方向のずれに対して対向面積の変動を幅狭部の部分だけにすることが確実にできる。   In addition, as a design in the case of stacking without misalignment, the narrow portion 23 facing the narrow portion 13 and the half length in the length direction (Y direction) of the narrow portions 13 and 23 are the length direction (Y It is desirable that they overlap in the direction). By designing in this way, it is possible to ensure that the variation of the facing area is limited to only the narrow portion with respect to the deviation in both directions in the length direction (Y direction).

そして、コンデンサ導体パターン3,4の先端側に小面積部12,22が形成されているので、コンデンサ導体パターン3,4の先端側が、対向するコンデンサ導体パターン4,3からはみ出して外部電極33,32との間に静電容量が生じて、積層ずれによる静電容量の変動が大きくなることも抑制できる。   And since the small area parts 12 and 22 are formed in the front end side of the capacitor conductor patterns 3 and 4, the front end side of the capacitor conductor patterns 3 and 4 protrudes from the opposing capacitor conductor patterns 4 and 3, and the external electrodes 33 and It is also possible to suppress an increase in capacitance variation due to stacking deviation due to the capacitance between the first and second layers.

さらに、コンデンサ導体パターン3,4の形状が全て同一に形成されるので、コンデンサ導体パターン3,4を奇数枚で積層した場合の静電容量のばらつきを抑制することができる。   Furthermore, since the capacitor conductor patterns 3 and 4 are all formed in the same shape, it is possible to suppress variation in capacitance when the capacitor conductor patterns 3 and 4 are laminated in an odd number.

この結果、積層ずれによる静電容量のばらつきを抑えることができ、かつ、静電容量の変動が小さい積層コンデンサ1が得られる。   As a result, it is possible to obtain a multilayer capacitor 1 that can suppress variations in capacitance due to stacking deviation and that has small variations in capacitance.

より具体的には、積層コンデンサ1の試料を作製してその静電容量の変動率を評価した(実施例1)。ここで、コンデンサ導体パターン3,4は10層とし、部品サイズは長さ1mm×幅0.5mm×厚み0.5mmとした。比較のために、図9に示したコンデンサ導体パターン72,73(幅が265μm)を有する従来の積層コンデンサ71の場合(比較例1)、並びに、図10に示したコンデンサ導体パターン82(幅が300μm),83(幅が230μm)を有する従来の積層コンデンサ81の場合(比較例2)の評価も併せて行った。なお、積層ずれや外部電極寸法による静電容量ばらつきの影響を調べるため、長さ方向(Y方向)および幅方向(X方向)に30μmの積層ずれを生じさせるとともに、外部電極の回り込み寸法(折り返し部分の寸法)を0.15mmから0.35mmまで変動させた。   More specifically, a sample of the multilayer capacitor 1 was prepared and the variation rate of the capacitance was evaluated (Example 1). Here, the capacitor conductor patterns 3 and 4 have 10 layers, and the component size is 1 mm long × 0.5 mm wide × 0.5 mm thick. For comparison, in the case of the conventional multilayer capacitor 71 having the capacitor conductor patterns 72 and 73 (width of 265 μm) shown in FIG. 9 (Comparative Example 1), the capacitor conductor pattern 82 shown in FIG. In the case of the conventional multilayer capacitor 81 having a width of 300 μm and 83 (width of 230 μm) (Comparative Example 2) was also evaluated. In order to investigate the influence of capacitance variation due to stacking deviation and external electrode dimensions, a stacking deviation of 30 μm is caused in the length direction (Y direction) and width direction (X direction), and the wraparound dimension of the external electrode (folding back) The size of the part) was varied from 0.15 mm to 0.35 mm.

その結果、実施例1の静電容量の変動率は±1.7%であった。一方、比較例1の静電容量の変動率は±11.7%であり、比較例2の静電容量の変動率は±3.5%であった。これにより、実施例1のコンデンサ構造をとれば、大幅に静電容量変動を抑えられることがわかる。   As a result, the variation rate of the capacitance in Example 1 was ± 1.7%. On the other hand, the capacitance variation rate of Comparative Example 1 was ± 11.7%, and the capacitance variation rate of Comparative Example 2 was ± 3.5%. Thus, it can be seen that if the capacitor structure of Example 1 is adopted, the capacitance fluctuation can be greatly suppressed.

次に、図7に示すようなコイルとコンデンサからなるトラップ型の積層LCフィルタ41を作製してその共振周波数の変動率を評価した。このLCフィルタ41は、厚さ30μmのガラスを主成分とするセラミックグリーンシートに図3のコンデンサ導体パターン3,4を印刷し、交互に4層積層して、さらにその上部にコイル用導体パターン45を印刷した厚さ20μmのガラスを主成分とするセラミックグリーンシートを積層して積層体ブロックを形成した。積層体ブロックは所定のサイズにカットした後、一体的に焼成した。これにより、積層体51を得た。   Next, a trap-type multilayer LC filter 41 composed of a coil and a capacitor as shown in FIG. 7 was produced, and the variation rate of the resonance frequency was evaluated. The LC filter 41 is formed by printing the capacitor conductor patterns 3 and 4 of FIG. 3 on a ceramic green sheet whose main component is glass having a thickness of 30 μm, laminating four layers alternately, and further forming a coil conductor pattern 45 thereon. A ceramic green sheet mainly composed of glass having a thickness of 20 μm printed thereon was laminated to form a laminate block. The laminated body block was cut into a predetermined size and then fired integrally. Thereby, the laminated body 51 was obtained.

コイル用導体パターン45はセラミックグリーンシートに形成したビアホールを介して層間接続され、10.5ターンのコイルを構成している。コイルとコンデンサは積層体51内部で電気的に並列接続している。部品サイズは長さ1mm×幅0.5mm×厚み0.5mmとした。   The coil conductor pattern 45 is connected between layers through via holes formed in a ceramic green sheet to constitute a 10.5 turn coil. The coil and the capacitor are electrically connected in parallel inside the multilayer body 51. The component size was 1 mm long × 0.5 mm wide × 0.5 mm thick.

次に、積層体51の両端部に導電ペーストを塗布し、焼き付けすることにより外部電極52,53を形成した。外部電極52はコンデンサ導体パターン3の引出し部14に電気的に接続されるとともに、コイル用導体パターン45にて構成されたコイルの一端に電気的に接続されている。外部電極53はコンデンサ導体パターン4の引出し部24に電気的に接続されるとともに、コイル用導体パターン45にて構成されたコイルの他端に電気的に接続されている。   Next, the external electrodes 52 and 53 were formed by applying and baking a conductive paste on both ends of the laminate 51. The external electrode 52 is electrically connected to the lead portion 14 of the capacitor conductor pattern 3 and is also electrically connected to one end of a coil constituted by the coil conductor pattern 45. The external electrode 53 is electrically connected to the lead portion 24 of the capacitor conductor pattern 4 and is also electrically connected to the other end of the coil constituted by the coil conductor pattern 45.

比較のために、コイル用導体パターン45の形状は同じで、図9に示したコンデンサ導体パターン72,73(幅が265μm)を有する積層LCフィルタ(比較例3)、並びに、図10に示したコンデンサ導体パターン82(幅が300μm),83(幅が230μm)を有する積層LCフィルタ(比較例4)を作製し、その評価も併せて行った。なお、積層ずれや外部電極寸法による共振周波数ばらつきの影響を調べるため、長さ方向(Y方向)および幅方向(X方向)に30μmの積層ずれを生じさせるとともに、外部電極の回り込み寸法(折り返し部分の寸法)を0.15mmから0.35mmまで変動させた。   For comparison, the shape of the coil conductor pattern 45 is the same, and the laminated LC filter (Comparative Example 3) having the capacitor conductor patterns 72 and 73 (width 265 μm) shown in FIG. A laminated LC filter (Comparative Example 4) having capacitor conductor patterns 82 (width: 300 μm) and 83 (width: 230 μm) was prepared and evaluated. In addition, in order to investigate the influence of variations in resonance frequency due to stacking deviation and external electrode dimensions, a stacking deviation of 30 μm is generated in the length direction (Y direction) and width direction (X direction), and the wraparound dimension of the external electrode (folded portion) ) Was varied from 0.15 mm to 0.35 mm.

その結果、実施例2の共振周波数の変動率は±2.4%であった。一方、比較例3の共振周波数の変動率は±9.8%であり、比較例4の共振周波数の変動率は±4.9%であった。これにより、実施例2のLCフィルタ構造をとれば、大幅に共振周波数変動を抑えられることがわかる。   As a result, the variation rate of the resonance frequency in Example 2 was ± 2.4%. On the other hand, the variation rate of the resonance frequency of Comparative Example 3 was ± 9.8%, and the variation rate of the resonance frequency of Comparative Example 4 was ± 4.9%. Thus, it can be seen that if the LC filter structure of Example 2 is adopted, the resonance frequency fluctuation can be greatly suppressed.

また、図8には、幅狭部13,23が互いに重なり合わない積層コンデンサ61が示されている。このように幅狭部13,23が重なり合わない積層コンデンサ61の場合には、幅方向(X方向)の積層ずれが発生しても、幅狭部13,23の対向面積はゼロで殆ど変化しない。従って、積層コンデンサ61は、図1に示した前記積層コンデンサ1(実施例1)より幅方向(X方向)の積層ずれに対して静電容量の変化を抑制することができる。   Further, FIG. 8 shows a multilayer capacitor 61 in which the narrow portions 13 and 23 do not overlap each other. In the case of the multilayer capacitor 61 in which the narrow portions 13 and 23 do not overlap in this way, even if a stacking shift in the width direction (X direction) occurs, the facing area of the narrow portions 13 and 23 changes almost at zero. do not do. Therefore, the multilayer capacitor 61 can suppress a change in capacitance with respect to the stacking deviation in the width direction (X direction) than the multilayer capacitor 1 (Example 1) shown in FIG.

なお、本発明は前記実施例に限定するものではなく、その要旨の範囲内で種々に変更することができる。   In addition, this invention is not limited to the said Example, It can change variously within the range of the summary.

特に、前記実施例では、積層コンデンサや積層LCフィルタを例にして説明したが、積層バリスタや積層サーミスタなどであってもよい。   In particular, in the above embodiments, the multilayer capacitor and the multilayer LC filter have been described as examples. However, a multilayer varistor, a multilayer thermistor, or the like may be used.

また、前記実施例ではコンデンサ導体パターンの引出し部の幅が狭くなっているが、これはコンデンサ導体パターンをセラミックグリーンシートに印刷する際、ペーストの塗布量が多くなり引出し部が厚くなることを抑制するためである。従って、このような問題が発生しない場合には、大面積部の幅と同じ寸法であっても構わない。   In the above embodiment, the width of the lead portion of the capacitor conductor pattern is narrow, but this suppresses an increase in the amount of paste applied and the lead portion becomes thick when the capacitor conductor pattern is printed on the ceramic green sheet. It is to do. Therefore, when such a problem does not occur, the size may be the same as the width of the large area portion.

また、前記実施例はセラミックグリーンシートを積み重ねて積層体を形成するものであるが、導電ペーストを順に重ね塗りする方法で積層体を形成するものであってもよい。   Moreover, although the said Example piles up a ceramic green sheet and forms a laminated body, it may form a laminated body by the method of repeatedly applying a conductive paste in order.

本発明に係る積層セラミック電子部品の一実施例を示す分解斜視図。1 is an exploded perspective view showing an embodiment of a multilayer ceramic electronic component according to the present invention. 図1に示した積層セラミック電子部品の垂直断面を示す模式図。The schematic diagram which shows the vertical cross section of the multilayer ceramic electronic component shown in FIG. 図1に示した積層セラミック電子部品の水平断面を示す模式図。The schematic diagram which shows the horizontal cross section of the multilayer ceramic electronic component shown in FIG. 図3の内部電極のずれを示す模式図。FIG. 4 is a schematic diagram showing the displacement of the internal electrode in FIG. 3. 図3の内部電極の別のずれを示す模式図。FIG. 4 is a schematic diagram showing another shift of the internal electrode in FIG. 3. 図3の内部電極のさらに別のずれを示す模式図。FIG. 4 is a schematic diagram showing still another shift of the internal electrode of FIG. 3. 本発明に係る積層セラミック電子部品の別の実施例を示す垂直断面模式図。The vertical cross-sectional schematic diagram which shows another Example of the multilayer ceramic electronic component which concerns on this invention. 本発明に係る積層セラミック電子部品のさらに別の実施例を示す水平断面模式図。The horizontal cross-sectional schematic diagram which shows another Example of the multilayer ceramic electronic component which concerns on this invention. 従来の積層セラミック電子部品の水平断面模式図。The horizontal cross-section schematic diagram of the conventional multilayer ceramic electronic component. 従来の別の積層セラミック電子部品の水平断面模式図。The horizontal cross-section schematic diagram of another conventional multilayer ceramic electronic component.

符号の説明Explanation of symbols

1,61…積層コンデンサ
2…セラミックグリーンシート
3,4,63,64…コンデンサ導体パターン
11,21…大面積部
12,21…小面積部
13,23…幅狭部
31…積層体
32,33…外部電極
41…積層LCフィルタ
45…コイル用導体パターン
51…積層体
52,53…外部電極
DESCRIPTION OF SYMBOLS 1,61 ... Multilayer capacitor 2 ... Ceramic green sheet 3, 4, 63, 64 ... Capacitor conductor pattern 11, 21 ... Large area part 12, 21 ... Small area part 13, 23 ... Narrow part 31 ... Laminate body 32, 33 ... External electrode 41 ... Laminated LC filter 45 ... Conductor pattern for coil 51 ... Laminated body 52, 53 ... External electrode

Claims (7)

複数のセラミック層と内部導体を積み重ねて構成した積層体と、前記積層体の両端部に形成され、かつ前記内部電極と交互に接続する一対の外部電極とを有する積層セラミック電子部品において、
前記内部電極は、大面積部と、小面積部と、前記大面積部および前記小面積部の間に配置されて大面積部と小面積部を繋ぐ幅狭部とからなり、
前記大面積部は前記内部電極の前記外部電極との接続部側に配置されるとともに、前記小面積部は前記内部電極の先端部に形成され、
前記大面積部は平面視で前記セラミック層を介して対向する前記小面積部と重なっていることを特徴とする積層セラミック電子部品。
In a multilayer ceramic electronic component having a laminate configured by stacking a plurality of ceramic layers and internal conductors, and a pair of external electrodes formed at both ends of the multilayer body and alternately connected to the internal electrodes,
The internal electrode is composed of a large area part, a small area part, a narrow part that is arranged between the large area part and the small area part and connects the large area part and the small area part,
The large area portion is disposed on the connection portion side of the internal electrode with the external electrode, and the small area portion is formed at a tip portion of the internal electrode,
The multilayer ceramic electronic component according to claim 1, wherein the large area portion overlaps the small area portion facing through the ceramic layer in plan view.
前記大面積部および前記小面積部は略矩形状であり、前記大面積部は前記小面積部よりも電極幅が広く、かつ電極長が長いことを特徴とする請求項1に記載の積層セラミック電子部品。   2. The multilayer ceramic according to claim 1, wherein the large area portion and the small area portion have a substantially rectangular shape, and the large area portion has a wider electrode width and a longer electrode length than the small area portion. Electronic components. 前記小面積部は、平面視で、前記セラミック層を介して対向する前記大面積部内で該大面積部と重なっていることを特徴とする請求項1または請求項2に記載の積層セラミック電子部品。   3. The multilayer ceramic electronic component according to claim 1, wherein the small area portion overlaps the large area portion in the large area portion opposed to the ceramic layer through the ceramic layer in a plan view. . 前記幅狭部は、平面視で、前記セラミック層を介して対向する前記幅狭部と互いに重なっていることを特徴とする請求項1〜請求項3のいずれかに記載の積層セラミック電子部品。   4. The multilayer ceramic electronic component according to claim 1, wherein the narrow portion overlaps the narrow portion facing each other through the ceramic layer in a plan view. 前記幅狭部は、平面視で、前記セラミック層を介して対向する前記幅狭部と互いに重なっていないことを特徴とする請求項1〜請求項3のいずれかに記載の積層セラミック電子部品。   4. The multilayer ceramic electronic component according to claim 1, wherein the narrow portion does not overlap with the narrow portion opposed to each other through the ceramic layer in plan view. 前記積層セラミック電子部品は積層セラミックコンデンサであることを特徴とする請求項1〜請求項5のいずれかに記載の積層セラミック電子部品。   6. The multilayer ceramic electronic component according to claim 1, wherein the multilayer ceramic electronic component is a multilayer ceramic capacitor. 前記積層体の内部にインダクタを備え、LCフィルタとしたことを特徴とする請求項6に記載の積層セラミック電子部品。   The multilayer ceramic electronic component according to claim 6, wherein an inductor is provided inside the multilayer body to form an LC filter.
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