JP2006185365A - Semiconductor device and debugging method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which eliminates the need of special equipment for research such as an incircuit emulator and can easily research interrupt delay, and a debugging method. <P>SOLUTION: A CPU control part receives an interrupt request IRQ_2, changes a priority level to "10" in accordance with the priority level of the interrupt request IRQ_2 and executes a task 1. When an interrupt inhibition instruction is executed at time Tb, the CPU control part changes the priority level to "15" and inhibits all of the other interrupt requests. When an interrupt request IRQ_1 with a priority level "14" is inputted at time Tc, an IPC control part reads a program counter value from a program counter and stores the program counter value in an IPC register. Then, the IPC control part reads a program counter value of the task 2 stored in the IPC register by a register reading instruction included in a task 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device provided with means for easily investigating the cause of an interrupt delay and a debugging method.

  In the field of electronic computers, control by an interrupt request is performed in order to deal with an exceptional event that occurs regardless of program execution.

  When an interrupt request is input, the arithmetic unit that executes the program temporarily saves the program counter value and the like, interrupts the program being executed, and executes the interrupt program with priority.

  Further, in order to deal with a plurality of exceptional events, a plurality of interrupt requests each having a priority level set can be input.

  For example, as disclosed in Non-Patent Document 1, when a plurality of interrupt requests are input at the same time or the interrupt program corresponding to the previously input interrupt request is not terminated, the next interrupt request is input In some cases, the interrupt program with the higher priority level is executed preferentially.

  By the way, bugs are likely to occur in a so-called critical section where a plurality of programs share a shared resource such as a memory or a file. Therefore, exclusive processing for preventing the execution of other programs is generally performed. For this reason, an interrupt prohibition process that temporarily sets the priority level to the maximum value and prohibits the execution of all other interrupt programs is also a conventional means in the interrupt program.

  As a result, even if an interrupt request having a higher priority level than the previously input interrupt request is input later, if interrupt disable processing is performed in the interrupt program executed in response to the interrupt request input earlier, The start of an interrupt program in response to an interrupt request having a high priority level input later is delayed. Such a phenomenon is called “interrupt delay”. Therefore, in the case of an interrupt program in which the time from the occurrence of an exceptional event to the completion of execution is restricted, the processing is hindered due to the interrupt delay.

  Therefore, it is necessary to identify a program that performs interrupt prohibition processing that causes an interrupt delay and to perform debugging to correct the contents.

  As a method for identifying the program causing the interrupt delay as described above, there are a method by reviewing the entire source code of the program and a method by in-circuit emulation.

  The entire source code review of a program is a method in which a program developer reviews a source code and identifies a program that is executing an interrupt prohibition process.

  In-circuit emulation is a method of specifying a program that is performing interrupt prohibition processing by executing a program using an apparatus (in-circuit emulator) that reproduces the operation of the arithmetic unit instead of the arithmetic unit.

Patent Document 1 discloses an in-circuit emulator that can be debugged when an interrupt processing program is not executed in response to an input of an interrupt request.
JP 2000-40015 A SH7011 Hardware Manual HD6417011, February 1999 1st Edition, Hitachi, Ltd. Semiconductor Division, p64, p74-78

  However, in recent years, the source code size of programs has grown, making it difficult for program developers to review the source code.

  Further, the in-circuit emulator needs to be manufactured according to each arithmetic unit, and is not general except for a general-purpose semiconductor device. There were also many functional restrictions. For this reason, sufficient debugging cannot always be performed.

  Therefore, the present invention has been made to solve such a problem, and the object thereof is to provide a semiconductor device that does not require special investigation equipment such as an in-circuit emulator and can easily investigate an interrupt delay. It is to provide a debugging method.

  When receiving an interrupt request, the present invention interrupts the program being executed, executes the interrupt program according to the interrupt request, and outputs the priority level of the interrupt request or the priority level set by the interrupt program When an interrupt request with a priority level set from the outside is received, the priority level received from the calculation unit is compared with the priority level of the interrupt request.If the priority level from the calculation unit is lower than the priority level of the interrupt request, Outputs an interrupt request to the arithmetic unit, and if the priority level from the arithmetic unit is the same or higher than the priority level of the interrupt request, the interrupt that delays the output of the interrupt request until the priority level from the arithmetic unit decreases When the control unit and the interrupt control unit receive an interrupt request, an interrupt delay investigating unit that stores information indicating the execution state of the program in the arithmetic unit It is a semiconductor device comprising a.

  In addition, when an interrupt request is received, the present invention interrupts the program being executed, executes the interrupt program according to the interrupt request, and outputs the priority level of the interrupt request or the priority level set by the interrupt program When an interrupt request with a priority level set from outside is received from the arithmetic unit, the priority level received from the arithmetic unit is compared with the priority level of the interrupt request, and the priority level from the arithmetic unit is lower than the priority level of the interrupt request In this case, an interrupt request is output to the arithmetic unit, and if the priority level from the arithmetic unit is equal to or higher than the priority level of the interrupt request, the output of the interrupt request is delayed until the priority level from the arithmetic unit decreases. A debugging method for avoiding an interrupt delay of a program executed in a semiconductor device including an interrupt control unit When the control unit receives an interrupt request, a step of storing a program counter value for specifying a program executed by the arithmetic unit and a program counter value stored in the interrupt program executed in response to the interrupt request are read out. Steps.

  According to the present invention, when the interrupt control unit receives an interrupt request, the interrupt delay investigating unit stores information indicating the execution state of the program in the arithmetic unit, so that immediately before the interrupt program corresponding to the interrupt request is executed. Information about the program that was being executed can be acquired. Therefore, the cause of the interrupt delay can be easily investigated based on the information indicating the execution state of the stored program, and debugging can be performed based on the investigated cause.

  Embodiments of the present invention will be described in detail with reference to the drawings. Note that the same or corresponding parts in the drawings are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a schematic block diagram showing a configuration of a semiconductor device 100 according to the first embodiment of the present invention.

  Referring to FIG. 1, semiconductor device 100 according to the first embodiment of the present invention includes an interrupt control unit 2, a calculation unit (CPU unit: Central Processing Unit; hereinafter referred to as CPU unit) 4, a memory 14, And an internal bus 52.

  The interrupt control unit 2, the CPU unit 4, and the memory 14 are connected to each other via an internal bus 52.

  The interrupt control unit 2 includes a register 20, an input control unit 18, a priority level setting register 28, a priority order determination unit 26, and a comparator 30.

  The register 20 includes an interrupt control register (ICR) 22 and an interrupt status register (ISR) 24.

  The interrupt control register 22 stores a setting value for enabling or disabling interrupt for each interrupt request input to the input control unit 18.

  The interrupt status register 24 stores the input status of each interrupt request.

  When any one of the interrupt requests IRQ_1, IRQ_2,..., IRQ_n is input, the input control unit 18 reads the setting value corresponding to the input interrupt request from the interrupt control register 22. Then, the input control unit 18 determines whether or not the interrupt request is permitted based on the read set value, and outputs the interrupt request to the priority order determination unit 26 if permitted. Further, the input control unit 18 stores each input state of the interrupt request in the interrupt status register 24.

  The priority level setting register 28 stores the priority level set for each interrupt request input to the input control unit 18.

  Upon receiving an interrupt request from the input control unit 18, the priority determination unit 26 reads the priority level set for the interrupt request from the priority level setting register 28. Further, if a plurality of interrupt requests are input simultaneously, the priority determination unit 26 compares the priority levels set in the respective interrupt requests with each other, and sequentially outputs the interrupt requests with the higher priority level to the comparator 30. .

  When the comparator 30 receives an interrupt request from the priority order determination unit 26, the comparator 30 compares the priority level of the interrupt request with the priority level received from the CPU unit 4. If the priority level received from the CPU unit 4 is lower than the priority level of the interrupt request, the comparator 30 outputs the interrupt request to the CPU unit 4. If the priority level received from the CPU unit 4 is equal to or higher than the priority level of the interrupt request, the comparator 30 outputs the interrupt request until the priority level received from the CPU unit 4 becomes lower than the priority level of the interrupt request. Delay.

  The CPU unit 4 includes a register 32, a CPU control unit 54, and an IPC control unit 40.

  The register 32 includes an IPC register 42, an IPC control register 44, a program counter (PC: Program Counter) 46, a status register (SR: Status Register) 48, and a stack pointer (SP: Stack Pointer) 50.

  The program counter 46 stores an instruction address of a program executed in the CPU unit 4.

  The status register 48 stores the priority level of the CPU unit 4.

  The stack pointer 50 stores an address value for designating a stack area in the memory 14.

  The IPC register 42 stores the program counter value output from the IPC control unit 40.

  The IPC control register 44 stores a set value indicating whether or not the operation of the IPC control unit 40 is valid when an interrupt request is input to the IPC control unit 40.

  The CPU control unit 54 counts up the value of the program counter 46 according to the program to be executed. When the CPU control unit 54 receives an interrupt request from the interrupt control unit 2, the CPU control unit 54 stores the value stored in the program counter 46 and the status register 48 based on the address value stored in the stack pointer 50. The stored value is saved in the stack area in the memory 14, and the interrupt program corresponding to the interrupt request is executed. Further, the CPU control unit 54 changes the value of the status register 48 to the priority level of the interrupt request. Further, the CPU control unit 54 changes the value of the status register 48 in accordance with an instruction of the program to be executed.

  The IPC control unit 40 outputs an interrupt request from the priority determination unit 26 to the comparator 30 and simultaneously receives the interrupt request, reads the setting value from the IPC control register 44, and determines whether or not the setting value is valid. Judging. Only when the set value is valid, the IPC control unit 40 reads the program counter value stored in the program counter 46 and stores the value in the IPC register 42.

  In the first embodiment, the IPC control unit 40, the IPC register 42, and the IPC control register 44 constitute a program counter value storage unit.

  FIG. 2 is an example of a state diagram of semiconductor device 100 according to the first embodiment of the present invention.

  Referring to FIG. 2, semiconductor device 100 receives interrupt requests IRQ_1 and IRQ_2 from the outside, and executes interrupt handler 1 and interrupt handler 2 as interrupt programs, respectively. The priority level of the interrupt request can be set in the range of 1 to 14, and the priority levels of the interrupt requests IRQ_1 and IRQ_2 are “14” and “10”, respectively. That is, the interrupt handler 1 has a higher priority than the interrupt handler 2.

  Referring to FIGS. 1 and 2, at time T0, neither interrupt request IRQ_1 nor IRQ_2 is input, and CPU unit 4 is executing the IDLE task. The priority level of the CPU unit 4 is “0”.

  Next, when an interrupt request IRQ_2 is input from the outside at time Ta, since no other interrupt request is input, the interrupt request IRQ_2 passes through the input control unit 18 and the priority determination unit 26 and is compared with the comparator. 30. The comparator 30 compares the priority level “0” received from the CPU unit 4 with the priority level “10” of the interrupt request IRQ_2, and outputs an interrupt request IRQ_2 having a high priority level to the CPU control unit 54. Then, the CPU control unit 54 receives the interrupt request IRQ_2, performs interrupt processing, and saves the value stored in the program counter 46 being executed and the value stored in the status register 48 to the stack area of the memory 14. (Step S1). At the same time, the CPU control unit 54 changes the priority level to “10” according to the priority level of the interrupt request IRQ_2. Then, the CPU control unit 54 executes the interrupt handler 2 that is an interrupt program of IRQ_2 (step S2).

  When a critical section occurs in the process of the interrupt handler 2 at time Tb, an interrupt prohibition instruction is executed. Then, the CPU control unit 54 changes the priority level to “15” which exceeds the maximum value of the priority level of the interrupt request, and prohibits all other interrupt requests (step S3).

  When an interrupt request IRQ_1 is input from the outside at time Tc when all other interrupt requests are prohibited, the interrupt request IRQ_1 set at the priority level “14” is input to the input control unit 18 and the priority determination unit. 26 and output to the comparator 30. The comparator 30 compares the priority level “15” received from the CPU unit 4 with the priority level “14” of the interrupt request IRQ_1, and delays the output of the interrupt request IRQ_1 having a low priority level.

  Thereafter, at time Td, the critical session of the interrupt handler 2 ends, and an interrupt prohibition release command is executed. Then, the CPU control unit 54 changes the priority level to the original “10”. In response to the decrease in the priority level, the comparator 30 outputs an interrupt request IRQ_1 to the CPU control unit 54. Then, in response to the interrupt request IRQ_1, the CPU control unit 54 performs an interrupt process in the same manner as in step S1 described above (step S5). At the same time, the CPU control unit 54 changes the priority level to “14” according to the priority level of the interrupt request IRQ_1. Then, the CPU control unit 54 executes the interrupt handler 1 that is an interrupt program of IRQ_1 (step S6).

  As described above, the interrupt prohibition instruction included in the interrupt program executed in response to the interrupt request IRQ_2 input earlier causes execution of the interrupt program corresponding to the interrupt request IRQ_1 having a higher priority level input later (Te -Tc).

  On the other hand, the IPC control unit 40 reads the program counter value of the program being executed in the CPU unit 4 from the program counter 46 at the time when the interrupt request output from the priority determination unit 26 is received, that is, at time Tc. Store in the register 42.

  Since the IPC register 42 is included in the register 32, the data stored in the IPC register 42 can be read using a register read instruction in the program.

  Therefore, the program counter value stored in the IPC register 42 can be read by including a register read instruction in the interrupt handler 1 executed in response to the interrupt request IRQ_1. In this way, the program counter value of the interrupt handler 2 that is the cause of the interrupt delay of the interrupt handler 1 is obtained.

  Therefore, the program developer can identify the program causing the interrupt delay from the obtained program counter value, and can easily perform debugging.

  FIG. 3 is a flowchart showing a method for performing debugging using semiconductor device 100 according to the first embodiment of the present invention.

  Referring to FIG. 3, IPC control unit 40 determines whether an interrupt request is received from priority determination unit 26 (step S100). If no interrupt request has been received (NO in step S100), IPC control unit 40 waits until an interrupt request is received (S100). If an interrupt request is received (YES in step S100), IPC control unit 40 reads the program counter value from program counter 46 and stores it in IPC register 42 (step S102).

  Then, in the interrupt program executed in response to the interrupt request, the program counter value is read from the IPC register 4 (step S104).

  The program developer specifies a program based on the read program counter value (S106). Then, the program developer debugs the identified program (S108).

  In the first embodiment, the case where the IPC control unit 40, the IPC register 42, and the IPC control register 44 constituting the program counter value storage unit are arranged inside the CPU unit 4 has been described. You may arrange | position outside the CPU part 4 via the bus | bath which transmits / receives data.

  According to the first embodiment, when an interrupt request given from the outside is output from the priority determination unit, the IPC control unit determines whether the interrupt request is given to the CPU unit or not. Stores the program counter value of the program being executed. The program counter value stored in the interrupt program executed in response to the interrupt request can be read out. Therefore, when an interrupt delay occurs in the interrupt program, the program developer can identify the program causing the delay from the read program counter value, and can easily perform debugging.

  Further, according to the first embodiment, the IPC control unit determines whether or not to store the program counter value based on the setting value stored in the IPC control register, and therefore identifies the program that causes the interrupt delay. The program counter value can be stored only when necessary. Therefore, redundant processing can be avoided by setting the program counter value not to be stored in a normal state.

[Embodiment 2]
FIG. 4 is a schematic block diagram showing a configuration of semiconductor device 200 according to the second embodiment of the present invention.

  Referring to FIG. 4, a semiconductor device 200 according to the second embodiment of the present invention is obtained by replacing CPU unit 4 with CPU unit 6 in semiconductor device 100 according to the first embodiment shown in FIG.

  The CPU unit 6 includes a register 34, a CPU control unit 56, a comparator 62, and a timer (TMR) control unit 60.

  The register 34 includes a timer activation priority level register (I_LVL) 64, a timer count register (TM_CNT) 66, a program counter 46, a status register 48, and a stack pointer 50.

  The timer activation priority level register 64 stores a setting value of a priority level that is a condition for the timer control unit 60 to receive an interrupt request and start time measurement.

  The timer count register 66 receives the reset value (0) or the time measurement value from the timer control unit and stores the value.

  Since program counter 46, status register 48, and stack pointer 50 are the same as those in the first embodiment, description thereof will not be repeated.

  In addition to the function of the CPU control unit 54 in the first embodiment, the CPU control unit 56 receives a command from the timer control unit 60 and changes the value of the status register 48.

  When an interrupt request is output from the priority determination unit 26, the comparator 62 compares the priority level of the interrupt request with the priority level read from the timer activation priority level register 64. The comparator 62 outputs the interrupt request to the timer control unit 60 only when the priority level of the interrupt request is higher than the priority level of the timer activation priority register.

  Upon receiving an interrupt request from the comparator 62, the timer control unit 60 resets the value of the timer count register 66 and then starts measuring time. Then, the timer control unit 60 stores the measured value in the timer count register 66. Furthermore, when the measured time exceeds a predetermined set value, the timer control unit 60 gives a command for forcibly lowering the priority level of the CPU unit 4 to the CPU control unit 56. The process for forcibly lowering the priority level of the CPU unit 4 in this way is referred to as an NMI (Non Maskable Interrupt) process.

  In the second embodiment, the timer control unit 60, the comparator 62, the timer activation priority level register 64, and the timer count register 66 constitute a delay time measurement unit.

  FIG. 5 is an example of a state diagram of semiconductor device 200 according to the second embodiment of the present invention.

  Similar to semiconductor device 100 according to the first embodiment shown in FIG. 2, semiconductor device 200 receives interrupt requests IRQ_1 and IRQ_2 from the outside, and executes interrupt handler 1 and interrupt handler 2 as interrupt programs, respectively. The priority level for the interrupt request can be set in the range of 1 to 14, and the priority levels of the interrupt requests IRQ_1 and IRQ_2 are “14” and “10”, respectively.

  Referring to FIGS. 4 and 5, since time T0 to time Tb are the same as those in FIG. 2, description thereof will not be repeated.

  When an interrupt request IRQ_1 is input from the outside at time Tc, the interrupt request IRQ_1 set to the highest priority level “14” passes through the input control unit 18 and the priority determination unit 26, and the comparator 30 and 62 is output.

  The comparator 30 compares the priority level “15” received from the CPU unit 4 with the priority level “14” of the interrupt request IRQ_1, and delays the output of the interrupt request IRQ_1 having a low level.

  On the other hand, the comparator 62 compares the priority level “14” of the interrupt request IRQ_1 received from the priority determination unit 26 with the priority level stored in the timer activation priority level register 64. For example, when the priority level of the timer activation priority level register is “13”, the comparator 62 outputs an interrupt request IRQ_1 having a high priority level to the timer control unit 60. Then, after resetting the timer count register 66, the timer control unit 60 starts measuring time and stores the measured value in the timer count register 66.

  Since timer count register 66 is included in register 32, data stored by a register read instruction executed by the program can be read.

  Therefore, by including a register read instruction in the interrupt handler 1 executed in response to the interrupt request IRQ_1, the time measurement value stored in the IPC register 42 is read, and the interrupt delay time of the interrupt handler 1 is obtained. In this way, the program developer can grasp the delay state of the interrupt handler 1.

  Therefore, the program developer can know whether or not an interrupt delay occurs every time the interrupt program is executed, and can easily perform debugging.

  Further, when the interrupt delay time exceeds a predetermined set value, the timer control unit 60 executes the NMI processing, and the CPU control unit 56 lowers the priority level of the CPU unit 4, so that it is delayed by the interrupt prohibition processing. Interrupted interrupt program is executed.

  Therefore, by setting the setting value, which is a condition for executing the NMI processing in the timer control unit 60, to be equal to or less than the allowable time for interrupt delay, it is possible to avoid processing defects due to interrupt delay.

  In the second embodiment, the case where the timer control unit 60, the comparator 62, the timer activation priority level register 64, and the timer count register 66 constituting the delay time measurement unit are arranged inside the CPU unit 6 has been described. However, you may arrange | position outside the CPU part 6 via the bus | bath which exchanges data with the CPU part 6. FIG.

  According to the second embodiment, when an interrupt request given from the outside is output from the priority determination unit, the IPC control unit measures time regardless of whether or not the interrupt request is given to the CPU unit. To start. Then, the measured value can be read by an interrupt program executed in response to the interrupt request. Therefore, the program developer can grasp the interrupt delay state of the interrupt program and can identify which interrupt program has a problem when a plurality of interrupt programs are executed, so that debugging can be easily performed. .

  Further, according to the second embodiment, the timer control unit measures the delay time when an interrupt request set to a priority level higher than the priority level stored in the timer activation priority level register is input. Therefore, the time delay until the completion of processing is particularly severe, and the interrupt delay state can be monitored by paying attention to the interrupt program set at a high priority level.

  Furthermore, according to the second embodiment, when the interrupt delay time exceeds the set value, the timer control unit performs NMI processing and forcibly executes the interrupt program. Therefore, the interrupt delay time of the interrupt program can be suppressed to a predetermined value or less, and processing problems due to the interrupt delay can be avoided.

[Embodiment 3]
In the first embodiment described above, the case where the program counter value of the program being executed is stored when an interrupt request given from the outside is output from the priority determination unit has been described. Further, in the above-described second embodiment, the case where the time is measured when an interrupt request given from the outside is output from the priority determination unit has been described.

  On the other hand, in Embodiment 3, the case where both functions are provided will be described.

  FIG. 6 is a schematic block diagram showing a configuration of semiconductor device 300 according to the third embodiment of the present invention.

  Referring to FIG. 6, semiconductor device 300 according to the third embodiment of the present invention is obtained by replacing CPU unit 4 with CPU unit 8 in semiconductor device 100 according to the first embodiment shown in FIG.

  The CPU unit 8 includes a register 36, a CPU control unit 54, a switching unit 72, a timer control unit 60, and an IPC control unit 40.

  The register 36 includes a switching setting register (FSW) 78, a shared register 80, a program counter 46, a status register 48, and a stack pointer 50.

  The switching setting register 78 stores a setting value for switching which of the timer control unit 60 and the IPC control unit 40 the switching unit 72 validates.

  The shared register 80 stores data output from the timer control unit 60 and the IPC control unit 40.

  Since program counter 46, status register 48, stack pointer 50, and CPU control unit 54 are the same as those in the first embodiment, description thereof will not be repeated.

  When the switching unit 72 receives an interrupt request from the priority determination unit 26, the switching unit 72 reads the setting value from the switching setting register 78, and interrupts either the timer control unit 60 or the IPC control unit 40 according to the read setting value. Give a request.

  When the timer control unit 60 receives an interrupt request from the switching unit 72, the timer control unit 60 resets the shared register 80 and then starts measuring time. Then, the timer control unit 60 stores the measured data in the shared register 80.

  When receiving an interrupt request from the switching unit 72, the IPC control unit 40 reads the program counter value stored in the program counter 46 and stores it in the shared register 80.

  In the third embodiment, IPC control unit 40 and shared register 80 constitute a program counter storage unit, and timer control unit 60 and shared register 80 constitute a delay time measuring unit.

  Since switching setting register 78 and shared register 80 are included in register 36, the stored data can be updated using a register write instruction in the program, and the stored data can be read using a register read instruction. be able to.

  For example, a register write instruction is executed in the interrupt program, and the setting value stored in the switching setting register 78 is changed so that the timer control unit 60 becomes valid. Further, a register read instruction is executed to read the time measurement value stored in the shared register 80. In this way, the interrupt delay state in the interrupt program is first grasped.

  If an interrupt delay of the interrupt program has occurred, a register write instruction is executed in the interrupt program, and the setting value stored in the switching setting register 78 is changed so that the IPC control unit 40 becomes valid. Further, a register read instruction is executed to read the program counter value stored in the shared register 80. In this way, the program counter value of the program that causes the interrupt delay is obtained.

  Therefore, the program developer can determine whether or not an interrupt delay has occurred, and can further identify the program causing the interrupt delay, thereby facilitating debugging.

  In the third embodiment, when the IPC control unit 40, the timer control unit 60, the switching setting register 78, and the shared register 80 that constitute the program counter storage unit and the delay time measurement unit are arranged inside the CPU unit 8. However, it may be arranged outside the CPU unit 8 via a bus that exchanges data with the CPU unit 8.

  According to the third embodiment, since either the IPC control unit or the timer control unit is enabled according to the set value of the switching setting register, an area for storing data by the IPC control unit and the timer control unit is set. Can be shared. Therefore, the register of the CPU unit can be used effectively, and the register area can be suppressed.

[Embodiment 4]
FIG. 7 is a schematic block diagram showing the configuration of semiconductor device 400 according to the fourth embodiment of the present invention.

  Referring to FIG. 7, semiconductor device 400 according to the fourth embodiment of the present invention includes an interface unit 84 in place of CPU unit 4 in the semiconductor device 100 according to the first embodiment shown in FIG. Is.

  The CPU unit 10 includes a register 38, a CPU control unit 58, and a trace unit 82.

  The register 38 includes a program counter 46, a status register 48, and a stack pointer 50. Since program counter 46, status register 48, and stack pointer 50 are the same as those in the first embodiment, description thereof will not be repeated.

  In addition to the function of the CPU control unit 54 in the first embodiment, the CPU control unit 58 outputs trace information including an execution address, an executed instruction code, operand access information, and the like to the trace unit 82.

  When the trace unit 82 receives an interrupt request from the priority order determination unit 26, the trace unit 82 starts collecting the trace information of the CPU unit 10 via the CPU control unit 58. Then, the trace unit 82 stores the collected trace information in itself. Further, the trace unit 82 outputs the collected trace information to the interface unit 84.

  The interface unit 84 converts the trace information received from the trace unit 82 into data of a predetermined format and outputs the data to an external analysis device or the like.

  Trace information stored in the trace unit 82 can be read using a read command executed in the program. Therefore, the program developer can acquire more detailed information when the interrupt delay occurs.

  In addition, the trace unit 82 outputs the stored trace information to an external analysis device via the interface unit 84. Therefore, the program developer can more easily analyze the program execution state when the interrupt delay occurs.

  In the fourth embodiment, the case where the trace unit 82 is arranged inside the CPU unit 10 has been described. However, the trace unit 82 may be arranged outside the CPU unit 10 via a bus that exchanges data with the CPU unit 10. Good.

  According to the fourth embodiment, the trace unit starts collecting trace information when an interrupt request given from the outside is output from the priority determination unit. Therefore, since only necessary trace information can be collected, the trace unit does not collect redundant trace information, the storage capacity of the trace unit can be suppressed, and analysis work can be performed efficiently.

[Embodiment 5]
FIG. 8 is a schematic block diagram showing the configuration of semiconductor device 500 according to the fifth embodiment of the present invention.

  Referring to FIG. 8, semiconductor device 500 according to the fifth embodiment of the present invention is obtained by replacing CPU unit 10 with CPU unit 12 in semiconductor device 400 according to the fourth embodiment shown in FIG. In the CPU unit 10, the CPU unit 12 is obtained by replacing the CPU control unit 58 with the CPU control unit 59 and replacing the trace unit 82 with the bus related information storage unit 94.

  The CPU control unit 59 outputs bus access information to the bus related information storage unit 94 in addition to the function of the CPU control unit 54 in the first embodiment.

  The bus related information storage unit 94 includes a bus access counter 92 and a performance counter 90. When the bus-related information storage unit 94 receives an interrupt request from the priority order determination unit 26, the bus-related information storage unit 94 activates the bus access counter 92 and the performance counter 90. Further, the bus related information storage unit 94 reads out the data stored in the bus access counter 92 and the performance counter 90 and outputs the data to the interface unit 84.

  Based on the bus access information received from the CPU control unit 59, the bus access counter 92 counts the number of bus accesses performed by the CPU unit 12 to the internal bus 52, that is, the number of read / write accesses. The count number is stored.

  Based on the bus access information received from the CPU control unit 59, the performance counter 90 performs the number of execution cycles of the bus access performed by the CPU unit 12 with respect to the internal bus 52, that is, the number of cycles required for read / write access ( The number of clocks) is counted and the count number is stored.

  Further, the bus related information storage unit 94 reads out the program counter value stored in the program counter 46 and outputs it to the interface unit 84.

  In the fifth embodiment, the bus related information storage unit 94 and the interface unit 84 constitute an information output unit.

  In addition, the bus related information storage unit 94 can output the number of bus accesses, the number of bus access execution cycles, and the program counter value to a recording device connected via the interface unit 84. The program developer can more easily analyze the program execution state when an interrupt delay occurs.

  In the fifth embodiment, the case where the bus-related information storage unit 94 is arranged in the CPU unit 12 has been described. However, the bus-related information storage unit 94 is arranged outside the CPU unit 12 via a bus that exchanges data with the CPU unit 12. May be.

  According to the fifth embodiment, the bus related information storage unit starts collecting the number of bus accesses and the number of bus access execution cycles when an externally applied interrupt request is output from the priority order determination unit. Therefore, since the bus related information can be collected at a necessary timing, unnecessary information is not collected and analysis work can be performed efficiently. Further, since the program counter value is also output at the same time, the analysis work can be performed more efficiently.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention. It is an example of a state diagram of semiconductor device 100 according to the first embodiment of the present invention. It is a flowchart which shows the method of debugging using the semiconductor device 100 according to Embodiment 1 of this invention. It is a schematic block diagram which shows the structure of the semiconductor device 200 according to Embodiment 2 of this invention. It is an example of the state diagram of the semiconductor device 200 according to Embodiment 2 of this invention. It is a schematic block diagram which shows the structure of the semiconductor device 300 according to Embodiment 3 of this invention. It is a schematic block diagram which shows the structure of the semiconductor device 400 according to Embodiment 4 of this invention. It is a schematic block diagram which shows the structure of the semiconductor device 500 according to Embodiment 5 of this invention.

Explanation of symbols

  2 interrupt control unit, 4, 6, 8, 10, 12 arithmetic unit (CPU unit), 14 memory, 18 input control unit, 20, 32, 34, 36, 38 register, 22 interrupt control register (ICR), 24 interrupt Status register (ISR), 26 priority order determination unit, 28 priority level setting register, 30, 62 comparator, 40 IPC control unit, 42 IPC register, 44 IPC control register, 46 program counter (PC), 48 status register (SR) ), 50 stack pointer (SP), 52 internal bus, 54, 56, 58, 59 CPU control unit, 60 timer (TMR) control unit, 64 timer activation priority level register (I_LVL), 66 timer count register (TM_CNT), 72 switching unit, 78 switching setting register (FSW ), 80 shared register, 82 trace unit, 84 interface unit, 90 performance counter, 92 bus access counter, 94 bus related information storage unit, 100, 200, 300, 400, 500 semiconductor device, IRQ_1, IRQ_2,. IRQ_n Interrupt request.

Claims (12)

When receiving an interrupt request, an arithmetic unit that interrupts the program being executed, executes the interrupt program according to the interrupt request, and outputs a priority level of the interrupt request or a priority level set by the interrupt program; ,
When an interrupt request with a priority level set from outside is received, the priority level received from the arithmetic unit is compared with the priority level of the interrupt request, and the priority level from the arithmetic unit is the priority level of the interrupt request. If it is lower, the interrupt request is output to the arithmetic unit, and if the priority level from the arithmetic unit is equal to or higher than the priority level of the interrupt request, the priority level from the arithmetic unit is An interrupt controller that delays the output of the interrupt request until low;
When the interrupt control unit receives the interrupt request, the semiconductor device includes an interrupt delay examining unit that stores information indicating an execution state of a program in the arithmetic unit.   2. The program according to claim 1, wherein the interrupt delay investigating unit includes a program counter value storage unit that stores a program counter value of a program being executed by the arithmetic unit when the interrupt control unit receives the interrupt request. Semiconductor device.   3. The interrupt delay examining unit further includes a delay time measuring unit that measures a time required until the interrupt program is executed in the arithmetic unit when the interrupt control unit receives the interrupt request. A semiconductor device according to 1. The interrupt delay investigation unit
At the time when the interrupt control unit receives the interrupt request, a program counter value storage unit that stores a program counter value of a program executed by the arithmetic unit;
When the interrupt control unit receives the interrupt request, a delay time measuring unit that measures a time required until the interrupt program is executed in the arithmetic unit;
The semiconductor device according to claim 1, further comprising a switching unit that enables one of the program counter value storage unit and the delay time measurement unit according to a predetermined set value.   5. The semiconductor according to claim 2, wherein the program counter value storage unit determines whether or not to store a program counter value of a program executed by the arithmetic unit according to a predetermined set value. 6. apparatus.   The semiconductor device according to claim 3, wherein the delay time measurement unit determines whether to measure the time according to a priority level of the interrupt request received by the interrupt control unit.   7. The delay time measuring unit according to claim 3, wherein, when the measured time is equal to or greater than a predetermined set value, the arithmetic unit forcibly executes the interrupt program. 8. The semiconductor device described.   The semiconductor device according to claim 1, wherein the interrupt delay examining unit further includes a trace unit that stores trace information in the arithmetic unit when the interrupt control unit receives the interrupt request.   The interrupt delay checking unit further includes an information output unit that outputs information indicating an execution state of a program in the arithmetic unit to the outside when the interrupt control unit receives the interrupt request. 2. A semiconductor device according to item 1.   The semiconductor device according to claim 9, wherein the information output unit outputs bus access information of the arithmetic unit to the outside as information indicating an execution state of a program in the arithmetic unit.   The semiconductor device according to claim 10, wherein the information output unit further outputs a program counter value of the calculation unit to the outside as information indicating an execution state of a program in the calculation unit. When receiving an interrupt request, an arithmetic unit that interrupts the program being executed, executes the interrupt program according to the interrupt request, and outputs a priority level of the interrupt request or a priority level set by the interrupt program; ,
When an interrupt request with a priority level set from outside is received, the priority level received from the arithmetic unit is compared with the priority level of the interrupt request, and the priority level from the arithmetic unit is the priority level of the interrupt request. If it is lower, the interrupt request is output to the arithmetic unit, and if the priority level from the arithmetic unit is equal to or higher than the priority level of the interrupt request, the priority level from the arithmetic unit is A debugging method for avoiding an interrupt delay of a program executed in a semiconductor device including an interrupt control unit that delays the output of the interrupt request until low.
When the interrupt control unit receives the interrupt request, storing a program counter value for specifying a program executed by the arithmetic unit;
Reading the stored program counter value in an interrupt program executed in response to the interrupt request.

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