JP2006185290A - Memory controller, flash memory system and method for controlling flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily prevent a flash memory from being erroneously corrected and erased. <P>SOLUTION: Management information, such as user data YD or card information CIS, and mode information MD is written in a user area of each physical block of the flash memory. Meanwhile, a block status, logical block information and data type information are written in a redundant area of each physical block. As the block status, there are information indicating a non-defective block and information indicating a defective block, and in the physical block with the management information written therein, information indicating an FOh or OFh defective block is written as a block status. In addition, the type (3h or Ch) of the management information is shown in the data type information. Consequently, access to the physical block with the management information written therein from a host system is limited, and for example, the management information is prevented from being erroneously erased. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory controller, a flash memory system, and a flash memory control method.

  In recent years, flash memories have been widely adopted as semiconductor memories used in memory systems such as memory cards and silicon disks. A flash memory is a kind of nonvolatile memory. Data stored in the flash memory is required to be retained even when power is not supplied.

  A NAND flash memory is a type of flash memory that is particularly frequently used in the above memory system. Each of the plurality of memory cells included in the NAND flash memory receives a logical value “0” from an erased state in which data indicating a logical value “1” is stored, independently of the other memory cells. It is possible to change to a writing state in which the indicated data is stored.

  In contrast, when changing from the written state to the erased state, each memory cell cannot change independently of the other memory cells. At this time, all of a predetermined number of memory cells called blocks are simultaneously erased. This batch erase operation is generally called “block erase”. The writing process or the reading process for the NAND flash memory is performed in units of a predetermined number of memory cells called pages. A block which is a unit of erasure processing is composed of a plurality of pages.

  In the NAND flash memory having the above-described configuration, data cannot be overwritten. Therefore, when data is rewritten, new data (after rewriting) is erased in a block erased block. Data) and the block in which old data (data before rewriting) has been written must be erased. When such data is rewritten, the data after rewriting is written in a different block from the data before rewriting. Accordingly, the correspondence between the logical address managed on the host system side and the physical address in the flash memory where the data is actually written changes dynamically every time data is rewritten.

  In order to manage the correspondence between the logical address and the physical address, the logical address information corresponding to the written data is written in the redundant area of the block in which the user data given from the host system side is written. This logical address information is read when creating a conversion table indicating the correspondence between logical addresses and physical addresses, and a conversion table is created based on the read logical address information.

  In the redundant area of the block in which user data given from the host system side is written, the logical address information is written as described above, but the management information such as card information (CIS: Card Information Structure) is written. No logical address information is written in the redundant area. That is, a logical address is not normally assigned to a block in which management information such as card information is written.

Since the block in which the management information is written is normally assigned to a preset location (block) in the flash memory, the block can be accessed even if no logical address is assigned. For example, in Patent Document 1, card information is written in the first or last physical block in the flash memory. Therefore. The card information can be read out by finding the first or last physical block in the flash memory.
JP-T-2001-503166

  According to the above-described technique, a block in which management information is written and a block in which user data is written can be determined based on logical address information written in the redundant area. However, in the flash memory, data may change due to a disturb phenomenon or the like. Therefore, when a block in which management information is written and a block in which user data is written are determined based on logical address information, an erroneous determination is made. It may be done. If an erroneous determination is made, management information may be erroneously corrected or erased by rewriting processing of user data, error correction processing of written user data, or the like. It is also possible to always manage the position information of the block in which the management information is written, and to exclude the block in which the management information is written from the processing target such as user data rewrite processing and error correction processing. If the determination of whether or not to perform is performed each time, the processing efficiency decreases.

  Accordingly, an object of the present invention is to provide a memory controller, a flash memory system including the memory controller, and a flash memory control method that can easily and reliably prevent erroneous correction and erroneous erasure.

In order to achieve the above object, a memory controller according to the first aspect of the present invention provides:
A memory controller that controls access to flash memory,
First writing means for writing management information referred to when accessing the flash memory to a physical block in the flash memory;
Second writing means for writing user data supplied from the host system to a physical block in the flash memory corresponding to a logical address given from the host system;
Diagnosing means for diagnosing whether a physical block in the flash memory is a bad block;
A first information indicating the quality of the physical block, a second information indicating the information on the logical address, and a third information indicating the type of data are written in the redundant area of each physical block in the flash memory. And writing means,
The first indicating that the redundant block of the physical block in which the management information is written by the first writing unit and the redundant region of the physical block diagnosed as a defective block by the diagnostic unit are defective blocks. Information is written,
The second information corresponding to the written user data is written in the redundant area of the physical block in which the user data is written by the second writing means,
The third information indicating the type of the management information is written in the redundant area of the physical block in which the management information is written by the first writing means.

  By adopting such a configuration, first information indicating a defective block is written in the redundant area of the physical block in which the management information is written. Further, since the third information indicating the type of management information is written in the redundant area of the physical block in which the management information is written, it is possible to easily and reliably prevent erroneous correction and erroneous erasure.

In addition, a table creating means for creating a conversion table showing a correspondence relationship between the logical address and a physical address on the address space of the flash memory,
The table creation means may read the second information of the physical block determined to be a non-defective block based on the first information, and create the conversion table based on the second information. .

Further, management information reading means may be provided that identifies a physical block in which the management information is written based on the third information and reads the management information from the physical block.
In addition, the first information may be assigned to a plurality of bits in the redundant area, and the number of bits in a write state included in the plurality of bits may indicate whether the block is a defective block.

  In order to achieve the above object, a flash memory system according to a second aspect of the present invention includes a memory controller and a flash memory according to the first aspect of the present invention.

In order to achieve the above object, a flash memory control method according to a third aspect of the present invention includes:
A first writing process for writing management information referred to when accessing the flash memory to a physical block in the flash memory;
A second write process for writing user data supplied from a host system to a physical block in the flash memory corresponding to a logical address given from the host system;
A diagnostic process for diagnosing whether the physical block in the flash memory is a bad block;
A third writing process for writing first information indicating the quality of a physical block, second information indicating information on the logical address, and third information indicating a type of data in a redundant area in the flash memory; Including
The first block indicating a defective block in the redundant area of the physical block in which the management information is written by the first writing process and the redundant area of the physical block diagnosed as a defective block by the diagnostic process Information is written,
The second information corresponding to the written data is written in the redundant area of the physical block in which the user data is written by the second writing process,
The third information indicating the type of the management information is written in the redundant area of the physical block in which the management information is written by the first write process.

A table creation process for creating a conversion table indicating a correspondence relationship between the logical address and a physical address in the address space of the flash memory;
The table creation process is a process of reading the second information of the physical block determined to be a non-defective block based on the first information and creating the conversion table based on the second information. May be.

  Further, it may include a management information reading process for identifying a physical block in which the management information is written based on the third information and reading the management information from the physical block.

  In addition, the first information may be assigned to a plurality of bits in the redundant area, and may indicate whether or not the block is a bad block by the number of bits in a write state included in the plurality of bits.

  According to the present invention, it is possible to easily and reliably prevent management information such as card information written in a block to which no logical address is assigned from being erroneously corrected or erased. Also, when creating a conversion table showing the correspondence between logical addresses and physical addresses, the physical block in which the management information is written is handled in the same way as the bad block. There is no need to perform a process of exclusion separately, and the efficiency of the conversion table creation process is improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a configuration diagram showing an outline of a flash memory system according to an embodiment of the present invention.
As shown in FIG. 1, the flash memory system 1 includes a flash memory 2 and a memory controller 3 that controls the flash memory 2. The flash memory system 1 is usually detachably attached to the host system 4 and used as a kind of external storage device for the host system 4.
Examples of the host system 4 include various information processing apparatuses such as a personal computer and a digital still camera that process various information such as characters, sounds, and image information.
Details of the flash memory 2 and the memory controller 3 will be described below.

[Description of flash memory 2]
In this flash memory system 1, a flash memory 2 in which data is stored is composed of a NAND flash memory. The NAND flash memory is a non-volatile memory developed for use as a storage device (as an alternative to a hard disk). This NAND flash memory cannot perform random access, and writing and reading are performed in units of pages and erasing is performed in units of blocks. Since data cannot be overwritten, when data is written, data is written into the erased area.

  Since the NAND flash memory has such characteristics, normally, when data is rewritten, new data (data after rewriting) is written to the erased block that has been erased, and old data is written. A process of erasing a block in which (data before rewriting) has been written is performed.

  When rewriting such data, since the data after rewriting is written in a different block from before rewriting, the logical address given from the host system 4 side and the physical address in the flash memory 2 The correspondence between and changes dynamically every time data is rewritten. Therefore, when accessing the flash memory 2, an address conversion table showing the correspondence between logical addresses and physical addresses is usually created, and the flash memory 2 is accessed using this address conversion table.

FIG. 2 is an explanatory diagram showing the relationship between blocks and pages.
The configuration of the block and page differs depending on the specification of the flash memory. However, in a general flash memory, as shown in FIG. 2A, one block is composed of 32 pages (P0 to P31). Consists of a 512-byte user area and a 16-byte redundant area. As the storage capacity increases, as shown in FIG. 2B, one block is composed of 64 pages (P0 to P63), and each page is composed of a 2048-byte user area and a 64-byte redundant area. What is being provided is also provided. In the present embodiment, one block is composed of 32 pages, and each page is composed of a 512-byte user area and a 16-byte redundant area.

  Here, the user area is mainly an area where data supplied from the host system 4 is stored, and the redundant area is stored with additional data such as an error correction code, corresponding logical address information and block status. Area. The error correction code is additional data for detecting and correcting an error included in the data stored in the user area, and is generated by an ECC block described later.

  The corresponding logical address information is written when data is stored in a physical block, and indicates information related to the logical address of the data stored in the physical block. If no data is stored in the physical block, the corresponding logical address information is not written, so whether the corresponding logical address information is written or not is the erased block. Can be judged. That is, if the corresponding logical block address is not written, it is determined that the block is an erased block.

  The block status is a flag indicating whether or not the physical block is a bad block (a physical block in which data cannot be normally written). When the physical block is determined to be a bad block, Is set with a flag indicating that it is a bad block.

Next, the circuit configuration of the flash memory 2 will be described.
A general NAND flash memory includes a register for holding write data or read data and a memory cell array for storing data. The memory cell array includes a plurality of memory cell groups in which a plurality of memory cells are connected in series, and a specific memory cell in the memory cell group is selected by a word line. Data copying (copying from register to memory cell or copying from memory cell to register) is performed between the memory cell selected by the word line and the register.

  A memory cell constituting the memory cell array is composed of a MOS transistor having two gates. Here, the upper gate is called a control gate, and the lower gate is called a floating gate. By injecting charges (electrons) into the floating gate and discharging charges (electrons) from the floating gate, Data is written or erased.

  Since the floating gate is surrounded by an insulator, the injected electrons are held for a long period of time. When injecting electrons into the floating gate, a high voltage is applied so that the control gate is at the high potential side. When electrons are injected from the floating gate, a high voltage at which the control gate is at the low potential side is applied. Applied to discharge electrons. The state in which electrons are injected into the floating gate (write state) corresponds to data having a logical value “0”, and the state in which electrons are discharged from the floating gate (erased state) has a logical value “1”. Corresponds to data.

[Description of Memory Controller 3]
The memory controller 3 includes a host interface control block 5, a microprocessor 6, a host interface block 7, a work area 8, a buffer 9, a flash memory interface block 10, and an ECC (error collection code) block 11. And a flash memory sequencer block 12. The memory controller 3 constituted by these functional blocks is integrated on one semiconductor chip. Hereinafter, the function of each functional block will be described.

The microprocessor 6 is a functional block that controls the operation of all the functional blocks constituting the memory controller 3.
The host interface control block 5 is a functional block that controls the operation of the host interface block 7. Here, the host interface control block 5 includes an operation setting register (not shown) for setting the operation of the host interface block 7, and the host interface block 7 operates based on the operation setting register.

  The host interface block 7 is a functional block that exchanges data, address information, status information, and external command information with the host system 4. That is, when the flash memory system 1 is attached to the host system 4, the flash memory system 1 and the host system 4 are connected to each other via the external bus 13. In such a state, data or the like supplied from the host system 4 to the flash memory system 1 is taken into the memory controller 3 with the host interface block 7 as an entrance, and is supplied from the flash memory system 1 to the host system 4. Are supplied to the host system 4 using the host interface block 7 as an exit.

  Further, the host interface block 7 has a register for holding a logical address, a sector number and an external command supplied from the host system 4, an error register (not shown) set when an error occurs, and the like. Yes.

  The work area 8 is a work area in which data necessary for controlling the flash memory 2 is temporarily stored, and is composed of a plurality of SRAM (Static Random Access Memory) cells.

  The buffer 9 is a functional block that temporarily holds data read from the flash memory 2 and data to be written to the flash memory 2. That is, data read from the flash memory 2 is held in the buffer 9 until the host system 4 is ready to receive data, and data to be written to the flash memory 2 is stored in the buffer 9 until the flash memory 2 is ready to write. Retained.

  The flash memory sequencer block 12 is a functional block that controls the operation of the flash memory 2 based on an internal command. The flash memory sequencer block 12 includes a plurality of registers (not shown), and information necessary for executing an internal command is set in the plurality of registers. When information necessary for executing an internal command is set in the plurality of registers, the flash memory sequencer block 12 executes processing based on the information.

Here, the “internal command” is a command given from the memory controller 3 to the flash memory 2 and is distinguished from an “external command” which is a command given from the host system 4 to the flash memory system 1.
The flash memory interface block 10 is a functional block that exchanges data, address information, status information, internal command information, device ID information, and the like with the flash memory 2 via the internal bus 14.

  The ECC block 11 generates an error correction code added to data to be written in the flash memory 2 and detects an error included in the read data based on the error correction code added to the read data. This is a functional block to be corrected.

[Description of Access to Flash Memory 2]
FIG. 3 is an explanatory diagram showing the correspondence between logical blocks and physical blocks. The logical address space is indicated by LBA (Logical Block Address), which is a serial number assigned in units of sectors.

  In the flash memory system 1 according to the present embodiment, a zone is formed by a plurality of physical blocks, and a predetermined logical address area is assigned to each zone. In the example shown in FIG. 3, a zone is formed by 1024 physical blocks. Further, a logical block space of 1000 blocks (1000 physical blocks) is allocated to this zone.

  Here, when the capacity of one sector is equal to the capacity of one page of the flash memory 2 and each physical block is composed of 32 pages, each physical block in the zone corresponds to 32 sectors in the logical address space. Assigned to a region. Therefore, if an area for 32 sectors in the logical address space is defined as one logical block, one logical block is assigned to one physical block. In addition, sequential numbers (LBN0 to LBN999) are assigned to logical blocks in which an area of 32000 sectors (LBA0 to LBA31999) allocated to one zone is divided every 32 sectors (hereinafter referred to as logical blocks). Are called logical block serial numbers). On the other hand, serial numbers (# 0 to # 1023) are also assigned to the 1024 physical blocks constituting the zone (hereinafter, the serial numbers assigned to the physical blocks are referred to as physical block serial numbers).

  In the example shown in FIG. 3, the logical block with the logical block sequence number LBN0 corresponding to LBA0 to LBA31 is assigned to the physical block with the physical block sequence number # 3, and the logical block with the logical block sequence number LBN1 corresponding to LBA32 to LBA63 is assigned. The block is assigned to the physical block of physical block serial number # 1, the logical block of logical block serial number LBN2 corresponding to LBA64 to LBA95 is assigned to the physical block of physical block serial number # 5, and corresponds to LBA96 to LBA127. The logical block having the logical block serial number LBN3 is assigned to the physical block having the physical block serial number # 7.

  When accessing the flash memory 2, a conversion table showing the correspondence between logical blocks and physical blocks is created, and the address of the page to be accessed is obtained using this conversion table. The conversion table is created based on logical block information (information indicating a logical block corresponding to user data written in the physical block) written in the redundant area of each physical block.

  For example, when user data is written to a physical block, if the logical block serial number of the logical block corresponding to the user data is written to the redundant area of the physical block, the logical block serial number is read sequentially. A conversion table can be created.

FIG. 4 is an explanatory diagram of the conversion table.
This conversion table is created for one zone, and logical block serial numbers LBN0 to LBN999 of the logical address space assigned to the zone and physical block serial numbers # 0 to # 0 of the corresponding physical blocks. The correspondence relationship of # 1023 is shown. In the example shown in FIG. 4, the logical block serial number LBN0 corresponds to the physical block serial number # 3, the logical block serial number LBN1 corresponds to the physical block serial number # 1, and the logical block serial number LBN2 Corresponds to block sequence number # 5.

  Thus, since the physical block serial number corresponding to each logical block serial number is shown, when the LBA is supplied as address information together with the command from the host system 4, the logical block serial number of the logical block to which the LBA belongs is displayed. By searching the number on the conversion table, the physical block serial number of the corresponding physical block can be obtained.

  In the redundant area of the physical block, information such as block status and data type is written together with the logical block information. Such information will be described with reference to FIG.

FIG. 5 is a diagram showing information written in the redundant area.
The block status is information indicating whether the physical block is a non-defective block or a defective block. In the example shown in FIG. 5, 8-bit data is assigned to the block status.

  In the initial state of the block status, all bits are in the erased state (logical value “1”) (FFh (hexadecimal number)). When it is diagnosed that the block is a defective block, 3 bits out of 8 bits are set in a write state (logical value “0”). Also, when determining pass / fail based on this block status, if the bit in the erased state (logical value “1”) is 1 bit or less, it is determined as a good block and the erased state (logical value “1”). If this bit is 2 bits or more, it is determined as a bad block.

  If it is determined that the block is a defective block, the number of bits to be written (logical value “0”) may be appropriately set in consideration of the reliability of the flash memory 2. In addition, the reliability of the flash memory 2 is also determined with respect to the criteria for determining pass / fail based on the block status, that is, the allowable number of bits in the write state (logical value “0”) that is determined to be a good block It may be set as appropriate in consideration.

  Further, F0h (hexadecimal number) is set as the block status of the physical block in which the card information (CIS) is written, and 0Fh (hexadecimal number) is set in the block status of the physical block in which the mode information (MD) is written. ) Is set. These are substantially block statuses indicating bad blocks.

  The data type information is information indicating the type of data written in the user area, and 4-bit data is allocated. For example, data type information is detected when card information (CIS) such as attributes, user data (YD) given from the host system 4 or mode information (MD) indicating a write mode is written in the user area. By doing so, it can be determined which data is written in each block.

In FIG. 5, the data type information of the physical block in which the user data (YD) is written has Fh (hexadecimal number) in which all bits are in the erased state (logical value “1”). On the other hand, the data type information of the physical block in which the card information (CIS) is written is set to 3h (hexadecimal number), and the data type of the physical block in which the mode information (MD) is written is Ch (16 Hex).
In this case, the data type information of the defective block is also the same as the data type information of the physical block in which the user data (YD) is written. The data type information of the physical block in which the user data (YD) is written is the same as the data type information of the defective block, but a data type different from Fh (hexadecimal number) may be set.

  In the logical block information, the logical block serial number of the logical block corresponding to the user data (YD) written in the user area is written as 10-bit data. In a physical block in which card information (CIS) or mode information (MD) without a corresponding logical block is written, logical block information is not written, and all bits are in an erased state (logical value “1”). ing. That is, the logical block information of the physical block in which card information (CIS) and mode information (MD) are written is 3FFh.

  Information such as logical block information, block status, and data type written in the redundant area is management information such as card information (CIS) and mode information (MD) when creating the conversion table shown in FIG. Referenced when accessing the physical block to which is written.

  When the conversion table shown in FIG. 4 is created, an area for creating the conversion table is secured on the work area 8, and the correspondence between the logical block serial number and the physical block serial number is described in this area. The correspondence between the logical block serial number and the physical block serial number is described based on the logical block information read from the redundant area. When reading out the logical block information, the logical block information of the non-defective block is sequentially read out.

  Since the non-defective block is determined based on the block status, the physical block in which management information such as card information (CIS) and mode information (MD) in which the block status is set to information indicating a defective block is written. In contrast, the logical block information is not read.

  In other words, management information such as card information (CIS) and mode information (MD) is written by excluding a physical block in which information indicating a bad block is set in the block status from a reading target of logical block information. The physical block that is present can also be excluded from the read target of the logical block information.

  Further, the user data (YD) is written by making the block status of the physical block in which management information such as card information (CIS) and mode information (MD) is written the same as the information indicating the defective block. It can be reduced that management information is rewritten or erased by mistake with a physical block. In other words, the data in the flash memory may change due to a disturb phenomenon, etc., but if the block status is set to information indicating a bad block, it is almost never mistaken for a good block, so the wrong processing It becomes very rare to be targeted.

As the block status of the physical block in which management information such as card information (CIS) and mode information (MD) is written, the same information as that of the defective block is set, but the management information is based on the data type information. Can be determined.
In other words, the data type of the defective block is Fh (hexadecimal) in which all bits are in the erased state (logical value “1”), but the data type of the physical block in which the card information (CIS) is written. Is set to 3h (hexadecimal number), and the data type of the physical block in which the mode information (MD) is written is set to Ch (hexadecimal number).

  Therefore, by searching for a physical block with a data type of 3h (hexadecimal number), a physical block in which card information (CIS) is written can be obtained, and a physical block with a data type of Ch (hexadecimal number) can be obtained. By searching, a physical block in which mode information (MD) is written can be obtained.

Next, logical block information, block status, and data type setting processing will be described.
When it is diagnosed as a defective block by the diagnostic processing, a block status indicating the defective block is written in the redundant area of the physical block. In the defective block diagnosis process, for example, a diagnosis is made as to whether all bits are in an erased state when erasing is performed, and whether data is normally written when preset data is written.

  When management information such as card information (CIS) or mode information (MD) is written, a block status indicating a defective block is written in a redundant area of the physical block in which the management information is written, and information indicating a data type is written. When user data (YD) is written, information indicating logical block information is written in the redundant area of the physical block in which user data (YD) is written.

  Note that if the logical block information, the block status, and the data type information are not written, they remain in the erased state. That is, when the logical block information is not written, the logical block information is 3FFh (hexadecimal number), when the block status is not written, the block status is FFh (hexadecimal number), and when the data type is not written, the data type Is Fh (hexadecimal).

1 is a block diagram of a flash memory system according to an embodiment of the present invention. It is a figure which shows the structure of the block and page of flash memory. It is a figure which shows the correspondence of a logical block and a physical block. It is a figure which shows a conversion table. It is a figure which shows the information written in a redundant area.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory system 2 Flash memory 3 Memory controller 4 Host system 5 Host interface control block 6 Microprocessor 7 Host interface block 8 Work area 9 Buffer 10 Flash memory interface block 11 ECC block 12 Flash memory sequencer block 13 External bus 14 Internal bus

Claims (9)

A memory controller that controls access to flash memory,
First writing means for writing management information referred to when accessing the flash memory to a physical block in the flash memory;
Second writing means for writing user data supplied from the host system to a physical block in the flash memory corresponding to a logical address given from the host system;
Diagnosing means for diagnosing whether a physical block in the flash memory is a bad block;
A first information indicating the quality of the physical block, a second information indicating the information on the logical address, and a third information indicating the type of data are written in the redundant area of each physical block in the flash memory. And writing means,
The first indicating that the redundant block of the physical block in which the management information is written by the first writing unit and the redundant region of the physical block diagnosed as a defective block by the diagnostic unit are defective blocks. Information is written,
The second information corresponding to the written user data is written in the redundant area of the physical block in which the user data is written by the second writing means,
The memory controller, wherein the third information indicating the type of the management information is written in a redundant area of the physical block in which the management information is written by the first writing means. Comprising a table creating means for creating a conversion table showing a correspondence relationship between the logical address and a physical address on the address space of the flash memory;
The table creation means reads the second information of the physical block determined to be a non-defective block based on the first information, and creates the conversion table based on the second information. The memory controller according to claim 1.   The management information reading means for specifying a physical block in which the management information is written based on the third information and reading the management information from the physical block is provided. The memory controller described.   2. The first information is assigned to a plurality of bits in the redundant area, and the number of bits in a write state included in the plurality of bits indicates whether the block is a bad block or not. 4. The memory controller according to any one of items 1 to 3.   A flash memory system comprising the memory controller according to claim 1 and a flash memory. A first writing process for writing management information referred to when accessing the flash memory to a physical block in the flash memory;
A second write process for writing user data supplied from a host system to a physical block in the flash memory corresponding to a logical address given from the host system;
A diagnostic process for diagnosing whether the physical block in the flash memory is a bad block;
A third writing process for writing first information indicating the quality of a physical block, second information indicating information on the logical address, and third information indicating a type of data in a redundant area in the flash memory; Including
The first block indicating a defective block in the redundant area of the physical block in which the management information is written by the first writing process and the redundant area of the physical block diagnosed as a defective block by the diagnostic process Information is written,
The second information corresponding to the written data is written in the redundant area of the physical block in which the user data is written by the second writing process,
The flash memory control method, wherein the third information indicating the type of the management information is written in a redundant area of the physical block in which the management information is written by the first write processing. Including a table creation process for creating a conversion table indicating a correspondence relationship between the logical address and a physical address on the address space of the flash memory,
The table creation process is a process of reading the second information of the physical block determined to be a non-defective block based on the first information and creating the conversion table based on the second information. The method of controlling a flash memory according to claim 6.   8. The management information reading process of identifying a physical block in which the management information is written based on the third information and reading out the management information from the physical block. Flash memory control method.   7. The first information is assigned to a plurality of bits in the redundant area, and indicates whether or not the block is a bad block according to the number of bits in a write state included in the plurality of bits. 9. The flash memory control method according to any one of items 8 to 9.

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