JP2006173480A - Semiconductor memory device - Google Patents

Abstract

【Task】
Provided is a high-capacity semiconductor memory device that is highly integrated without increasing the area of a memory cell and is low in cost.
[Solution]
A first memory function body 120 having a charge holding function formed on a semiconductor layer, a control gate electrode 106 formed on the first memory function body 120, and a channel region disposed under the first memory function body 120 The diffusion regions 101 and 102 are disposed on both sides of the channel region and have a conductivity type opposite to that of the channel region. The diffusion regions 101 and 102 are disposed on both sides or one side of the first memory function body 120 and the control gate electrode 106. And a second memory function body 108 and 109 having a charge holding function formed so as to be in contact with each other.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor memory device including an element having a function of converting a change in charge amount into a current amount.

  As a technology capable of increasing the capacity of a semiconductor memory device, there is a semiconductor memory device in which a memory function body having a memory function is formed in so-called sidewall regions on both sides of a gate electrode of a transistor (for example, Patent Document 1). reference). As shown in FIG. 1, the semiconductor memory device includes a semiconductor substrate 1, a gate insulating film 2, a gate electrode 3, a charge storage layer 4 formed in a sidewall shape, a channel region 6, and a high drain or source. It is composed of a concentration impurity region 7. In such a configuration, two memories can be configured in one transistor region.

International Publication No. 03/044868 Pamphlet

  However, the semiconductor memory device of Patent Document 1 is intended to achieve high integration by functioning the side wall region as a memory, but it is possible to increase the capacity by providing the memory function in other regions of the memory element. In view of recent technological trends, a low-cost and larger-capacity semiconductor device is desired.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device that is highly integrated without increasing the area of the memory cell, and that has a lower cost and a larger capacity.

  In order to achieve the above object, a semiconductor memory device according to the present invention includes a first memory function body having a charge holding function formed on a semiconductor layer, and a control gate electrode formed on the first memory function body. A channel region disposed under the first memory function body, a diffusion region disposed on both sides of the channel region and having a conductivity type opposite to that of the channel region, and the first memory function body and the control gate electrode. It has a memory element provided with the 2nd memory functional body which is arrange | positioned on both sides or one side, and was formed so that the said diffusion region may be contact | connected, and which has a charge holding function.

  In the semiconductor memory device according to the present invention having the above characteristics, the first memory function body further includes a first insulating film formed on the channel region, and a floating gate electrode formed on the first insulating film. And a second insulating film formed between the floating gate electrode and the control gate electrode.

  The semiconductor memory device according to the present invention having any one of the above features is characterized in that two second memory function bodies are formed on both sides of the first memory function body and the control gate electrode. To do.

  Furthermore, in the semiconductor memory device according to the present invention having any one of the above characteristics, the memory element includes a first terminal connected to the semiconductor layer, a second terminal connected to one of the diffusion regions, and the diffusion. Only four terminals of a third terminal connected to the other of the regions and a fourth terminal connected to the control gate electrode are provided for connection to other circuits.

  In the semiconductor memory device according to the present invention having any one of the above characteristics, the second memory function body is at least in accordance with a charge amount held in the memory function body by applying a voltage to the control gate electrode. The resistance of the diffusion region located under the second memory function body may be changed, and the amount of current flowing from one diffusion region to the other diffusion region may be changed, or the second The memory function body depletes at least a part of the diffusion region located under the second memory function body or inverts the conductivity type according to the amount of charge held in the second memory function body. It may be configured as follows.

  Furthermore, in the semiconductor memory device according to the present invention having any one of the above characteristics, the second memory function body includes a charge holding film having a charge holding function, and at least a part of the charge holding film is a part of the diffusion region. It is formed so as to be in contact with the portion.

  Furthermore, in the semiconductor memory device according to the present invention having any one of the above characteristics, the semiconductor layer is a semiconductor substrate, a well region provided in the semiconductor substrate, or a semiconductor layer disposed on an insulator. It is characterized by.

  Furthermore, in the semiconductor memory device according to the present invention having any one of the above characteristics, the gate voltage when reading the second memory function body is higher than a threshold voltage defined by the charge retention amount of the first memory function body. It is characterized by that.

  Due to the above features, the memory element according to the present invention forms a cell used for a flash memory or the like as a first memory function body instead of the gate of a transistor, and has a memory function on both sides of the cell, so-called sidewall regions. Forming a second memory function body. By adopting such a configuration, other regions other than the sidewall region in the memory element can function as a memory. Accordingly, it is possible to provide a high-density memory element without increasing the area of the memory cell. As a result, it is possible to provide a low-cost and large-capacity semiconductor memory device.

  An embodiment of a semiconductor memory device according to the present invention (hereinafter referred to as “the present invention device” as appropriate) will be described with reference to the drawings.

  First, the configuration of the semiconductor memory device according to the present invention will be described with reference to FIGS. Here, FIG. 2 is a schematic plan view of the memory element (memory cell) of the present embodiment. 3A is a schematic cross-sectional view in the AA direction of FIG. 2, and FIG. 3B is a schematic cross-sectional view in the BB direction of FIG. FIG. 4 shows terminals connected to the respective electrodes in the memory cell of the present embodiment.

  As shown in FIG. 2 and FIGS. 3A and 3B, the memory cell of this embodiment has a first memory function having a charge holding function formed on a p-type silicon substrate 100 as an example of a semiconductor substrate. Body 120, control gate electrode 106 formed on first memory function body 120, channel region disposed below first memory function body 120, and disposed on both sides of the channel region, having a conductivity type opposite to that of the channel region And a second memory function having a charge holding function disposed on both sides or one side of the first memory function body 120 and the control gate electrode 106 and formed in contact with the diffusion areas 101 and 102 And bodies 108 and 109. Further, a sidewall 107 is formed on the second memory function bodies 108 and 109.

  The first memory function body 120 of this embodiment includes a tunnel insulating film 103 made of a silicon oxide film formed on a channel region, a floating gate electrode 104 formed on the tunnel insulating film 103, and a floating gate electrode 104. An intergate insulating film 105 formed thereon is formed. In addition, the inter-gate insulating film 105 of this embodiment is an ONO film made of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The diffusion regions 101 and 102 of this embodiment are source / drain regions that are n-type silicon regions.

  In addition, the memory cell of this embodiment is connected to the gate terminal 203 (G), the source / drain terminal 201 (SD1), the source / drain terminal 202 (SD2), and the substrate terminal 204 as shown in FIG. ing. That is, one memory cell is connected to four terminals.

  By connecting at least one or more such memory cells and arranging them in a matrix, a large-capacity semiconductor memory device can be provided at low cost.

  Next, each operation (write operation, erase operation, read operation) of the memory cell according to the present invention will be described with reference to FIGS.

(Write operation)
First, a write operation to the first memory function body 120 (when data is written by increasing a threshold voltage) will be described.

  When inactive, the voltage applied to each terminal of the memory cell is set to 0 V (GND level). Next, at the time of the write operation, for example, 14 to 20 V is applied to the gate terminal 203 (G). As a result, a Fowler-Nordheim current (hereinafter referred to as FN current) flows through the tunnel insulating film 103, electrons are injected into the floating gate electrode 104, and the threshold voltage defined by the charge amount of the floating gate electrode 104 increases. To do.

  Incidentally, as a writing method for the first memory function body 120, there is a method using hot electrons, and a writing method using hot electrons may be used. However, it is necessary to configure so as to prevent erroneous writing to the second memory function bodies 108 and 109.

  Next, a writing operation to the second memory function bodies 108 and 109 (when data is written by reducing a current during reading) will be described. Note that the write operation of the second memory function bodies 108 and 109 includes the voltage applied to the source / drain terminal 201 (SD1) connected to the second memory function body 108 and the source connected to the second memory function body 109. Since only the voltage applied to the / drain terminal 202 (SD2) is switched, the case where data is written to the second memory function body 108 will be described here.

  When inactive, the voltage applied to each terminal of the memory cell is set to 0 V (GND level). Next, at the time of the write operation, the voltage of the terminal SD2 and the substrate terminal remains 0V, for example, 5V is applied to the terminal G and 5V is applied to the terminal SD1. That is, pinch-off (depletion) occurs in the channel below the second memory function body 108 by applying a very large voltage to the terminal SD1 as compared to a voltage (for example, 1.5 V) applied during the read operation. Then, hot electrons are generated to inject electrons into the second memory function body 108. Note that an inversion layer extends from the diffusion region 102 below the second memory function body 109, so that hot electrons are not generated and writing does not occur. By writing to the second memory function body 108, the resistance of the channel below the second memory function body 108 increases, and the current during the read operation decreases. At this time, it is necessary to set the voltage applied at the time of the write operation to such a voltage that electrons are not injected into the floating gate electrode 104 of the first memory function body 120 (suppression of disturbance at the time of the write operation).

  As described above, by setting the potential of each terminal of the memory cell, writing to the first memory function body 120 and the second memory function bodies 108 and 109 can be performed.

(Erase operation)
Next, an erasing operation on the first memory function body 120 (when data is erased by lowering the threshold voltage) will be described.

  When inactive, the voltage applied to each terminal of the memory cell is set to 0 V (GND level). Then, at the time of the erase operation, for example, −5V is applied to the terminal G and 10 to 15V is applied to the substrate terminal. The terminals SD1 and SD2 are in a floating state. As a result, an FN current flows through the tunnel insulating film 103, electrons in the floating gate electrode 104 are emitted to the semiconductor substrate 100, and the threshold voltage rises.

  Next, an erasing operation for the second memory function bodies 108 and 109 (when data is erased by increasing a current during reading) will be described.

  When inactive, the voltage applied to each terminal of the memory cell is set to 0 V (GND level). During the erase operation, for example, −5V is applied to the terminal G, and 5V is applied to the terminals SD1 and SD2 (substrate voltage is 0V). As a result, holes are injected into each second memory function body due to the band-to-band phenomenon near the PN junction located below the second memory function bodies 108 and 109. As a result, the resistance of the channel under the second memory function bodies 108 and 109 decreases, and the current during the read operation increases. At this time, the voltage applied during the erasing operation needs to be a voltage that does not cause a problem (disturbance) in the floating gate electrode 104 of the first memory function body 120.

(Read operation)
Next, a read operation for the first memory function body 120 will be described.

  When inactive, the voltage applied to each terminal of the memory cell is set to 0 V (GND level). At the time of the read operation, for example, 2V is applied to the terminal G, and the voltage of the terminal SD1 or the terminal SD2 is set to 1.5V. At this time, if the threshold voltage of the first memory function body 120 is 3 V, the transistor related to the first memory function body 120 is turned off. When the threshold voltage of the first memory function body 120 is 1V, the transistor related to the first memory function body 120 is turned on. However, since the current changes depending on the state of the first memory function body 120, the terminal G is set so that a current of about 1 to 50 μA flows even when the second memory function body 108 or the second memory function body 109 is in the write state. It is necessary to adjust the voltage applied to or the threshold voltage of the first memory function body 120. Further, in order to ensure reading accuracy, when the second memory function body 108 or the second memory function body 109 is in a writing state, the off state current amount of the transistor related to the first memory function body 120 is off. It is desirable that the amount of current is lower by one digit or more.

  Next, the reading operation of the second memory function bodies 108 and 109 will be described. Here, FIG. 11A shows the configuration of the memory cell as an equivalent circuit. FIG. 11B shows an equivalent circuit during a read operation for the memory function body 108. Note that since the read operation of the memory function body 108 and the memory function body 109 only replaces the voltage applied to the terminal SD1 and the voltage applied to the terminal SD2, here, the case where the memory function body 108 is read. explain. In the present embodiment, a case where the threshold voltage in the write state defined by the charge retention amount of the first memory function body 120 is about 3V and the threshold voltage in the erase state is about 1V will be described as an example.

  When inactive, the voltage applied to each terminal of the memory cell is set to 0 V (GND level). Next, during the read operation, for example, 4V is applied to the terminal G and 1.5V is applied to the terminal SD2. At this time, the transistor related to the first memory function body 120 is always turned on regardless of the state. Further, a depletion layer is formed in the channel region below the second memory function body 109 by the voltage applied to the terminal SD2. As a result, as shown in FIG. 11B, the second memory function body 109 substantially loses the variable resistance function. For this reason, the current flowing through the memory cell is mainly determined by the state of the second memory function body 108, and the second memory function body 108 can be read.

  In the above read operation, the first memory function body 120 and the second memory function bodies 108 and 109 can perform reading regardless of the state of each other. In addition, in order to explain each operation | movement of a memory cell, although demonstrated by demonstrating a specific applied voltage value, you may use the combination of a different voltage, if a desired phenomenon is acquired.

(Production method)
Next, a method for manufacturing the device of the present invention will be described with reference to FIGS. Each figure (a) shows an AA sectional view of the memory cell shown in FIG. 2, and each figure (b) shows a BB sectional view.

  First, as shown in FIG. 5, the first memory function body 120 and the control gate electrode 106 are formed on the surface of a p-type silicon substrate 100 as a semiconductor substrate by a combination of known photolithography, etching, deposition techniques, and the like. Form. Although the first memory function body 120 is formed independently for each memory cell, the control gate electrode 106 is continuously formed in the BB direction of FIG.

  Subsequently, as shown in FIG. 6, for example, a silicon oxide film 121 is formed with a thickness of about 1 to 20 nm using a thermal oxidation method, and then a laminated film of a silicon nitride film 131 is deposited with a thickness of about 2 to 20 nm.

  Next, as shown in FIG. 7, a silicon oxide film 122 which is an insulating film is deposited to a thickness of about 10 to 100 nm. After that, as shown in FIG. 8, the silicon oxide film 122, the silicon nitride film 131, and the silicon oxide film 121 are sequentially etched by reactive ion etching to form the silicon oxide film 122 in a sidewall shape. The stacked film of the silicon oxide film 121 and the silicon nitride film 131 becomes the second memory function body 108 and the second memory function body 109.

Subsequently, as shown in FIG. 9, an n-type silicon impurity region 141 is formed on the surface of the p-type silicon substrate 100 using the control gate electrode 106, the silicon oxide film 122, and the like as a mask by using, for example, an ion implantation method. At the same time, a known Halo injection layer or LDD layer for suppressing punch-through may be formed. The impurity concentration of the n-type silicon impurity region 141 is preferably about 10 ¹⁶ to 10 ²⁰ / cm ³ .

  Thereafter, as shown in FIG. 10, an interlayer insulating film 150 is formed by a known interlayer insulating film forming technique and an interlayer insulating film flattening technique, and contacts and metal wirings 151 are formed by a known wiring forming technique or the like. .

  As described above in detail, in the semiconductor memory device according to the present invention of the present embodiment, the first memory function body 120 and the second memory function bodies 108 and 109 formed on both sides of the first memory function body 120. Thus, 3 bits can be stored in one memory cell, and high integration can be achieved.

  Although the tunnel insulating film 103, the floating gate electrode 104, and the inter-gate insulating film 105 are configured as the first memory function body 120 in the above embodiment, the first memory function body 120 is formed of a silicon oxide film and a silicon nitride film. A composite insulating film may be formed.

  Further, the second memory function body does not necessarily have to be formed on both sides of the first memory function body 120 and the control gate electrode 106, and may be formed only on one of them. Furthermore, although the p-type silicon substrate is used as the semiconductor layer, it may be an SOI layer or a well region provided in the semiconductor substrate.

Sectional drawing which shows the structural example of the memory cell in a prior art FIG. 6 is a layout diagram showing a configuration example of a memory cell of a semiconductor memory device according to the present invention. Sectional drawing which shows the structural example of the memory cell of the semiconductor memory device based on this invention Sectional drawing explaining the electrode of the memory cell of the semiconductor memory device based on this invention Process sectional drawing which shows one manufacturing process of the memory cell in the manufacturing method of the semiconductor memory device based on this invention Process sectional drawing which shows one manufacturing process of the memory cell in the manufacturing method of the semiconductor memory device based on this invention Process sectional drawing which shows one manufacturing process of the memory cell in the manufacturing method of the semiconductor memory device based on this invention Process sectional drawing which shows one manufacturing process of the memory cell in the manufacturing method of the semiconductor memory device based on this invention Process sectional drawing which shows one manufacturing process of the memory cell in the manufacturing method of the semiconductor memory device based on this invention Process sectional drawing which shows one manufacturing process of the memory cell in the manufacturing method of the semiconductor memory device based on this invention 1 is an equivalent circuit diagram showing a configuration of a memory cell and a configuration during a read operation in a semiconductor memory device according to the present invention;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate insulating film 3 Gate electrode 4 Charge holding film 6 Channel region 7 High concentration impurity diffusion region 8 Low concentration impurity diffusion region 100 P-type silicon substrate 101, 102 Diffusion region 103 Tunnel insulating film 104 Floating gate electrode 105 Between gates Insulating film 106 Control gate electrode 107 Side wall 108, 109 Memory function body 120 First memory function body 121, 122 Silicon oxide film 131 Silicon nitride film 141 N-type impurity region 150 Interlayer insulating film 151 Contact, metal wiring 201, 202 Source / Drain terminal 203 Gate terminal 204 Substrate terminal

Claims (9)

  A first memory function body having a charge holding function formed on a semiconductor layer; a control gate electrode formed on the first memory function body; a channel region disposed under the first memory function body; A diffusion region disposed on both sides of the channel region and having a conductivity type opposite to that of the channel region, and disposed on both sides or one side of the first memory function body and the control gate electrode, and formed in contact with the diffusion region A semiconductor memory device comprising a memory element including a second memory function body having a charge holding function.   The first memory function body includes a first insulating film formed on the channel region, a floating gate electrode formed on the first insulating film, and between the floating gate electrode and the control gate electrode. The semiconductor memory device according to claim 1, comprising: a second insulating film formed.   The semiconductor memory device according to claim 1, wherein two second memory function bodies are formed on both sides of the first memory function body and the control gate electrode.   The memory element includes a first terminal connected to the semiconductor layer, a second terminal connected to one of the diffusion regions, a third terminal connected to the other of the diffusion regions, and the control gate electrode. 4. The semiconductor memory device according to claim 1, wherein only four of the fourth terminals to be connected are provided for connection to another circuit. 5.   The second memory function body changes a resistance of at least the diffusion region located under the second memory function body in accordance with a charge amount held in the memory function body by applying a voltage to the control gate electrode. 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to change an amount of current flowing from one of the diffusion regions to the other diffusion region. 6.   The second memory function body depletes at least a part of the diffusion region located under the second memory function body, or has a conductivity type according to the amount of charge held in the second memory function body. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to be inverted.   2. The second memory function body includes a charge holding film having a charge holding function, and is formed so that at least a part of the charge holding film is in contact with a part of the diffusion region. 7. The semiconductor memory device according to any one of items 1 to 6.   8. The semiconductor layer according to claim 1, wherein the semiconductor layer is a semiconductor substrate, a well region provided in the semiconductor substrate, or a semiconductor layer disposed on an insulator. Semiconductor memory device.   The gate voltage for reading out the second memory function body is higher than a threshold voltage defined by a charge retention amount of the first memory function body, according to any one of claims 1 to 8. Semiconductor memory device.

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