JP2006173294A - Semiconductor device - Google Patents

Abstract

In a GaN-based HFET, it is possible to realize a stable drain current and a sufficient gate leakage current reduction effect by using a gate insulating film with a thickness of less than 10 nm that can obtain a high gain, and a high Provided is a semiconductor device in which a high-quality insulating film can be used, which makes it easy to produce a quality insulating film.
A Si ₃ N ₄ film 41A formed on the surface of an HFET substrate using a nitride semiconductor, a SiO ₂ film 41B formed on the Si ₃ N ₄ film 41A, and a SiO ₂ film 41B are formed. The gate electrode 42 is provided. The thickness of the Si ₃ N ₄ film 41A is 0.28 nm to ₃ nm, and the thickness of the SiO ₂ film 41B is 0.5 nm to 7 nm.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having a high temperature, a high output, and a high withstand voltage, and more particularly to an ultrahigh frequency compound semiconductor field effect transistor in the semiconductor device.

  As a heterostructure field effect transistor (HFET), there is an HFET (GaN HFET) using a nitride semiconductor. GaN-based HFETs are very promising as next-generation high-temperature, high-output, high-voltage ultrahigh-frequency transistors, and are currently being actively researched for practical use.

On the other hand, there is an insulated gate HFET structure having an insulating film such as SiO ₂ or SiN on the substrate surface under the gate electrode. This insulated gate HFET structure is very attractive in increasing the gate breakdown voltage to increase the current density and reducing the gate leakage current that causes an increase in power consumption and noise. In general, the insulated gate HFET has the following problems.
(I) If an interface state exists between the insulating film and the substrate surface, drain current instability (current reduction in alternating current operation) is caused. Therefore, it is necessary to select an appropriate insulating film having such an effect. is there.
(Ii) In order to obtain a high gain, it is desirable to reduce the insulating film thickness by using an appropriate insulating film having a high insulating property (a large forbidden band width).

Therefore, at present, an insulated gate HFET having a good characteristic using a thin insulating film of less than 10 nm capable of obtaining a high gain, that is, without a drain current instability, and having a sufficient gate leakage current reducing effect. Development of the insulated gate HFET obtained is being carried out (Non-patent Documents 1 and 2).
N. Maeda, T, Tawara, T. Saitoh, K. Tsubaki, and N. Kobayashi, PhysicaStatus Soldi (a) 200, 168 (2003). N. Maeda, T. Makimura, C. Wang, M. Hiroki, T. Makimoto, T. Kobayashi, T. Enoki, Extended Abstracts of the 2004 International Conference on Solid State Devices and Materials, Tokyo, 2004, pp.324 (2004 ).

  Against this background, it is easy to produce a high-quality insulating film as a high-gain, high-current insulated gate HFET using a thin-layer insulated gate, and an insulated gate that can be produced using a highly versatile insulating film Development of HFET has been desired.

  The present invention can realize a stable drain current and a sufficient gate leakage current reduction effect by using a gate insulating film having a thickness of less than 10 nm that can obtain a high gain in a GaN-based HFET, An object of the present invention is to provide a semiconductor device in which a high-quality insulating film can be easily manufactured and a highly versatile insulating film can be used.

In order to solve the above-mentioned problem, the invention of claim 1 includes a Si ₃ N ₄ film formed on the surface of an HFET substrate using a nitride semiconductor, and a SiO ₂ film formed on the Si ₃ N ₄ film. And a gate electrode formed on the SiO ₂ film.
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a thickness of the Si ₃ N ₄ film is 0.28 nm to ₃ nm.
According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the thickness of the SiO ₂ film is 0.5 nm to 7 nm.
According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to _third aspects, the film thickness of the Si ₃ N ₄ film is controlled at the atomic layer level. It is characterized by that.

The operation of the semiconductor device according to the present invention is as follows. In the present invention, _two layers in which a Si ₃ N ₄ film having a thickness of 0.28 nm to ₃ nm and a SiO ₂ film having a thickness of 0.5 nm to ₇ nm are laminated in this order on the substrate surface under the gate electrode. An insulating gate is used to form an insulated gate HFET. Further, an insulating gate HFET structure is formed by using a two-layer insulating film formed by controlling the film thickness of the Si ₃ N ₄ film at an atomic layer level.

In other words, a two-layer insulation in which a Si ₃ N ₄ film capable of forming a good insulating film / GaN-based semiconductor interface with few interface states and a SiO ₂ film having a larger forbidden band are stacked in this order. By using a film, it is possible to achieve both stabilization of drain current due to good interface formation and reduction of insulation film thickness using high insulation, and high gain and high current insulation gate using thin layer insulation gate. An HFET is realized.

Here, if only the Si ₃ N ₄ film is used as the insulating gate film in order to stabilize the drain current by forming a good interface, the insulating property of the Si ₃ N ₄ film is the insulating property of the SiO ₂ film. Therefore, it is difficult to reduce the insulating film thickness. On the other hand, if only the SiO ₂ film is used as an insulating gate film in order to reduce the insulating film thickness by using a high insulating property, it is difficult to form a good interface with few interface states. It becomes difficult to obtain stabilization of the drain current. Therefore, the present invention is effective in order to obtain both the stabilization of the drain current by forming a favorable interface and the reduction of the insulating film thickness using a high insulating property.

  According to the present invention, in a GaN-based HFET, a stable drain current and a sufficient gate leakage current reducing effect can be obtained by using a gate insulating film having a thickness of less than 10 nm that can obtain a high gain. This is realized using a highly versatile insulating film that is easy to manufacture. As a result, a high gain / high current insulated gate HFET using a thin-layer insulated gate can be realized.

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a basic configuration diagram showing an example of a semiconductor device according to an embodiment of the present invention. The semiconductor device of FIG. 1 is an insulated gate HFET having a two-layer insulating film, and this insulated gate HFET includes a GaN-based HFET structure 10, a source metal (source electrode) 20, a drain metal (drain electrode) 30, and an insulated gate. 40. The GaN-based HFET structure 10 includes a SiC substrate 11, an AlGaN buffer layer 12, a GaN layer 13, and an AlGaN layer 14, and the insulating gate 40 includes a two-layer insulating film 41 and a gate metal (gate electrode) 42. ing. Further, the two-layer insulating film 41 is composed of a Si ₃ N ₄ film 41A and a SiO ₂ film 41B.

  This embodiment will be specifically described. In the insulated gate HFET according to the present embodiment, the AlGaN buffer layer 12 is formed on the SiC substrate 11. A sapphire substrate may be used instead of the SiC substrate 11. The Al composition of the AlGaN buffer layer 12 is 0.1 to 1.0. A GaN layer 13 is formed on the AlGaN buffer layer 12, and an AlGaN layer 14 is formed on the GaN layer 13. The Al composition of the AlGaN layer 14 is 0.1 to 1.0. A source metal 20, a drain metal 30, and an insulated gate 40 are formed on the surface of the AlGaN layer 14. In the present embodiment, the GaN-based HFET structure 10 is fabricated using a crystal growth method called metal organic vapor phase epitaxy or molecular beam epitaxy. Thereafter, an electrode metal is attached by an element manufacturing process to manufacture an insulated gate HFET.

In the present embodiment, the insulated gate 40 is formed as follows. In other words, a good insulating film / semiconductor interface with few interface states is formed by laminating a Si ₃ N ₄ film having a film thickness of 1 to ₃ nm on the surface of the GaN-based HFET structure 10 which is the nitride substrate surface. I was able to. Alternatively, a Si ₃ N ₄ film (corresponding to a film thickness of 0.14 to 1.12 nm) with a film thickness controlled at the atomic layer level is stacked on the nitride substrate surface. As a result, a good insulating film / semiconductor interface with few interface states could be formed. A Si ₃ N ₄ film having a film thickness of 1 to ₃ nm could be laminated by controlling at the atomic layer level.

Incidentally, in the c-axis direction is the main orientation direction of the Si ₃ N ₄ film, Si ₃ N ₄ lattice constant of the film was 0.56 nm, thus, the Si ₃ N ₄ membrane thickness of one atomic layer, 0.56 nm. Here, since one atomic layer of the Si ₃ N ₄ film is composed of four atomic planes, a ¼ atomic layer (0.25 atomic layer = 0.14 nm) is the minimum unit of thickness. . Here, the film thickness is controlled at the atomic layer level by sputtering, CVD (Chemical
It was obtained by controlling the film forming conditions in the Vapor Deposition method or the like. In addition, the fact that a good insulating film / semiconductor interface with few interface states could be formed was confirmed by the fact that drain current instability (current reduction in AC operation) did not occur.

From the viewpoint of the gain element, but Si ₃ N Si ₃ film thickness of N ₄ thin it is desirable that the ₄ film 41A, the film thickness is less than 0.5 atomic layer (0.28 nm), the drain current Instability occurred. Drain current stabilization was obtained by increasing the film thickness of Si ₃ N ₄ , but the critical film thickness depends on the lamination conditions of the GaN-based semiconductor material and Si ₃ N ₄ film on the substrate surface, In the case of a stack controlled at the atomic layer level, it is a general purpose that does not control at the atomic layer level within the range of 0.5 to 2.0 atomic layer (corresponding to a film thickness of 0.28 to 1.12 nm). In the case of lamination, the film thickness was in the range of 1 to 3 nm. Above the critical film thickness, there was no difference in drain current operation. FIG. 2 schematically shows these situations. FIG. 2A shows a case where the Si ₃ N ₄ film is smaller than 0.28, and in this state, the drain current is unstable. FIG. 2B shows that the Si ₃ N ₄ film has a thickness of 0.28 to 1.12 nm by atomic layer level film thickness control, or the Si ₃ N ₄ film has a thickness of 1 to 1 by general-purpose film thickness control. In this case, the drain current is not unstable. Thus, the drain current can be stabilized by the Si ₃ N ₄ film 41A having a film thickness of 0.28 to ₃ nm, and using this film thickness is advantageous in terms of device gain.

Next, the effect of reducing the gate leakage current by the insulating film will be described. When only the Si ₃ N ₄ film 41A having a film thickness of 0.28 to ₃ nm capable of stabilizing the drain current is used as the insulating gate film, the insulating effect is not sufficient, and when the gate voltage is applied positively The reduction in gate leakage current was less than an order of magnitude. Therefore, in order to obtain a sufficient gate leakage current reduction effect of two digits or more, it is necessary to further stack an insulating film on the Si ₃ N ₄ film 41A. In this case, it is advantageous to use an insulating film having a higher insulating property, that is, having a larger forbidden bandwidth, in order to make the film thickness as small as possible.

SiO ₂ film is forbidden band width of about 9 eV, a high insulation property than Si ₃ N ₄ of the forbidden band width of about 5 eV. Therefore, a predetermined gate leakage current reduction effect can be obtained with a smaller film thickness by using the SiO ₂ film. Actually, a two-layer insulating film 41 in which a SiO ₂ film 41B having a thickness of 0.5 nm or more is laminated on a Si ₃ N ₄ film 41A having a thickness of 0.28 to ₃ nm capable of stabilizing the drain current is used. Thus, it was possible to obtain a gate leakage current reduction effect of two digits or more. FIG. 3 schematically shows this state. In FIG. 3, curve a shows the characteristics of the gate leakage current of the normal gate HFET. On the other hand, the characteristic of the insulated gate HFET which obtained the gate leakage current reduction effect by the Si ₃ N ₄ film 41A having a thickness of 0.28 to ₃ nm and the SiO ₂ film 41B having a thickness of 0.5 nm is shown by a curve b. .

  In general, when a positive gate voltage is applied, the increase in gate leakage current is significant, and it is effective to reduce this. If the gate leakage current reduction when applying a positive gate voltage is 2 digits or more, the gate current when applying a positive gate voltage to an insulated gate HFET should be smaller than the gate current when applying a negative gate voltage to a normal gate HFET. It can be said that the effect of reducing the gate leakage current is remarkable.

Note that when a single layer of SiO ₂ is stacked on the surface of the semiconductor substrate, a drain current reduction effect occurs, and it has been confirmed that it is not appropriate to use a single layer as a gate insulating film. Further, the minimum film thickness of the SiO ₂ film 41B in the present invention is a gate of two digits or more when laminated on the Si ₃ N ₄ film 41A having a film thickness of 0.28 to ₃ nm capable of stabilizing the drain current. The minimum film thickness when the leakage reduction effect is recognized is 0.5 nm. Further, the maximum film thickness of the SiO ₂ film 41B in the present invention is less than 10 nm at which the total film thickness of the gate insulating film can obtain a high gain when the SiO ₂ film 41B is laminated on the Si ₃ N ₄ film 41A. Therefore, the maximum film thickness is set to 7 nm.

As described above, the Si ₃ N ₄ film 41A capable of forming a good insulating film / GaN-based semiconductor interface having a small interface state and the SiO ₂ film 41B having a larger forbidden band are stacked in this order. By using the two-layer insulating film 41, it becomes possible to achieve both the stabilization of the drain current by forming a favorable interface and the reduction of the insulating film thickness using a high insulating property, and a high gain using a thin-layer insulating gate. A large current insulated gate HFET has been realized.

Here, the SiO ₂ film is a semiconductor electronic device manufacturing process in which it is easy to produce a high-quality film stably and with high film thickness controllability under a relatively wide film formation condition at the current state of the industrial technology level. It is the most versatile insulating film. The use of the SiO ₂ film having such a feature as an upper high-insulating insulating film in the two-layer insulating film 41 of the present invention has a great advantage in device fabrication. Actually, it was possible to use an Al ₂ O ₃ film instead of the SiO ₂ film 41B. However, in the sputtering method, in order to produce a high-quality Al ₂ O ₃ film, strict control of film forming conditions is performed. However, the production of the high-quality SiO ₂ film 41B is possible under a wide range of film formation conditions. As a result, it was possible to obtain high reproducibility of device characteristics in repeated manufacturing of devices.

Thus, according to the present embodiment, by forming the Si ₃ N ₄ film 41A having a film thickness of 1 to ₃ nm on the nitride substrate surface, a good insulating film / semiconductor interface with few interface states is formed. I was able to.

  The embodiment of the present invention has been described in detail above, but the specific configuration is not limited to the present embodiment, and the present invention can be applied even if there is a design change or the like without departing from the scope of the present invention. included. For example, an insulated gate HFET having such a two-layer insulating film 41 is within the scope of the present invention regardless of the layer structure of the GaN-based HFET 10 of the substrate.

It is a basic composition figure showing the basic composition of the semiconductor device by the embodiment of the present invention. FIG. 4 is a diagram schematically illustrating characteristics of a semiconductor device according to an embodiment of the present invention, and is a diagram illustrating a relationship between drain current and drain voltage. FIG. 4 is a diagram schematically illustrating characteristics of the semiconductor device according to the embodiment of the present invention, and is a diagram illustrating a relationship between a gate leakage current and a gate voltage.

Explanation of symbols

10 GaN-based HFET structure 11 SiC substrate 12 AlGaN buffer layer 13 GaN layer 14 AlGaN layer 20 Source metal 30 Drain metal 40 Insulated gate 41 Two-layer insulating film 41 A Si ₃ N ₄ film 41 B SiO ₂ film 42 Gate metal

Claims (4)

A Si ₃ N ₄ film (41A) formed on the surface of an HFET substrate using a nitride semiconductor;
A SiO ₂ film (41B) formed on the Si ₃ N ₄ film (41A);
A gate electrode (42) formed on the SiO ₂ film (41B);
A semiconductor device comprising: The semiconductor device according to claim 1, wherein the Si ₃ N ₄ film (41 A) has a thickness of 0.28 nm to 3 nm. 3. The semiconductor device according to claim 1, wherein a film thickness of the SiO ₂ film (41 B) is 0.5 nm to 7 nm. 4. The semiconductor device according to claim 1, wherein the film thickness of the Si ₃ N ₄ film (41 A) is controlled at an atomic layer level. 5.

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