JP2006164382A - Ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric memory device having a small circuit scale and less erroneous reading.
[Solution]
A first memory cell and a second memory cell for storing predetermined data; a first bit line connected to the first memory cell; and a second bit line connected to the second memory cell; , A predetermined voltage is supplied to the source, a drain and a gate are connected to the first bit line, a first MOS transistor, a source is supplied with a predetermined voltage, a drain is connected to the second bit line, And a second MOS transistor having a gate connected to the first bit line, and a determination unit that determines data stored in the second memory cell based on the voltage of the second bit line. Dielectric memory device.
[Selection] Figure 1

Description

  The present invention relates to a ferroelectric memory device. In particular, the present invention relates to a ferroelectric memory device with less erroneous data reading.

A conventional FeRAM is disclosed in Japanese Patent Laid-Open No. 2002-1000018 (Patent Document 1). The FeRAM disclosed in Patent Document 1 includes a 0-level setting circuit that resets a low-potential-side signal to 0 V among binarized signals before the sense amplifier.
JP 2002-1000018 A

  However, in the conventional FeRAM disclosed in Patent Document 1, the timing for operating the zero level setting circuit has to be generated, which causes a problem that the circuit configuration of the FeRAM becomes complicated.

  Therefore, an object of the present invention is to provide a ferroelectric memory device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  To achieve the above object, according to one embodiment of the present invention, a first memory cell and a second memory cell for storing predetermined data, a first bit line connected to the first memory cell, And a second bit line connected to the second memory cell and a first MOS transistor whose source is supplied with a predetermined voltage and whose drain and gate are connected to the first bit line, and a source having a predetermined voltage A second memory cell based on a voltage of the second MOS transistor to which a voltage is supplied, a drain connected to the second bit line, a gate connected to the first bit line, and a voltage of the second bit line; A ferroelectric memory device comprising: a determination unit that determines data stored in the memory;

  In the above configuration, when the first bit line is charged until the potential difference between the voltage of the first bit line and the predetermined voltage reaches the threshold voltage of the first MOS transistor, the first MOS transistor is turned off. Then, charging of the first bit line is stopped. The second MOS transistor has a gate connected to the first bit line, and is turned off according to the voltage of the first bit line. That is, the second MOS transistor stops charging the second bit line according to the voltage of the first bit line. The voltage of the second bit line when the second MOS transistor stops charging the second bit line is stored in the capacitor added to the second bit line, that is, the second memory cell. It depends on the data value. Therefore, according to the above configuration, the voltage of the second bit line when charging is stopped differs depending on the data stored in the memory cell, and the determination unit determines the data based on this voltage. It is possible to prevent erroneous reading of data.

  The first MOS transistor and the second MOS transistor charge the first bit line and the second bit line with a predetermined voltage, respectively, and the determination unit stops charging the first bit line. Sometimes it is desirable to determine the data stored in the second memory cell.

  In the ferroelectric memory device, the capacitance added to the drain of the first MOS transistor is different from the capacitance added to the drain of the second MOS transistor, and the determination unit stops charging the second bit line. In this case, it is preferable that the voltage stored in the second memory cell is determined by comparing the voltage of the first bit line and the voltage of the second bit line.

  In the above configuration, since the capacitance of the first bit line is different from that of the second bit line, the voltage of the first bit line when the first bit line and the second bit line are charged is the second bit line. This is different from the voltage of the bit line. Therefore, according to the above configuration, data can be determined using the voltage of the first bit line as a reference voltage. Therefore, it is not necessary to separately provide a circuit for generating a reference voltage for the ferroelectric memory device to determine data, and the circuit scale of the ferroelectric memory device can be reduced.

  In the ferroelectric memory device, it is preferable that the amount of charge that the first MOS transistor charges the first bit line is substantially equal to the amount of charge that the second MOS transistor charges the second bit line.

  In the above configuration, when the charging of the first bit line and the second bit line is stopped, the voltages of the first bit line and the second bit line are determined according to the capacitance added to them. . Therefore, according to the above configuration, the voltage of the first bit line used as the reference voltage when charging is stopped can be easily adjusted.

  In the ferroelectric memory device, the threshold voltage of the first MOS transistor is different from the threshold voltage of the second MOS transistor, and the determination unit determines that the first bit when the charging of the second bit line is stopped. It is preferable to compare the voltage of the line and the voltage of the second bit line to determine the data stored in the second memory cell.

  In the above configuration, since the threshold voltage of the first MOS transistor is different from the threshold voltage of the second MOS transistor, the voltage of the first bit line when the first bit line and the second bit line are charged is This is different from the voltage of the second bit line. Therefore, according to the above configuration, data can be determined using the voltage of the first bit line as a reference voltage. Therefore, it is not necessary to separately provide a circuit for generating a reference voltage for the ferroelectric memory device to determine data, and the circuit scale of the ferroelectric memory device can be reduced.

  Hereinafter, the present invention will be described through embodiments of the invention with reference to the drawings. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.

  FIG. 1 is a diagram showing an embodiment of a ferroelectric memory device according to the present invention. The ferroelectric memory device 100 includes a memory cell array 110, a word line control circuit 120, a plate line control circuit 130, a precharge circuit 160, and a sense amplifier 170. The ferroelectric memory device 100 includes m (m is a positive integer) word lines WL1 to m and plate lines PL1 to m, n (n is a positive integer) bit lines BL1 to n, And a dummy bit line DBL.

  The memory cell array 110 has m × (n + 1) memory cells MC arranged in an array. The memory cell MC includes an n-type MOS transistor TR and a ferroelectric capacitor C.

  The n-type MOS transistor TR has a gate connected to one of the word lines WL1 to WLm, a source connected to one of the dummy bit line DBL and the bit lines BL1 to n, and a drain connected to one end of the ferroelectric capacitor C. It is connected to the. That is, the n-type MOS transistor TR switches whether to connect one end of the ferroelectric capacitor C to the dummy bit line DBL and the bit lines BL1 to n based on the voltages of the word lines WL1 to WLm.

  The other end of the ferroelectric capacitor C is connected to one of the plate lines PL1 to PL, and stores predetermined data based on the potential difference between the one end and the other end, and the stored data Based on the above, a predetermined amount of charge is discharged to the dummy bit line DBL and the bit lines BL1 to BLn. In this embodiment, the ferroelectric capacitor C stores data “1” when the potential at one end is higher than the coercive voltage with respect to the potential at one end, and the potential at the other end is stored. When the potential at one end becomes higher than the coercive voltage, data “0” is stored.

  The word line control circuit 120 is connected to the word lines WL1 to WLm and controls the voltages of the word lines WL1 to WLm. Specifically, the word line control circuit 120 sets the potential of a predetermined word line WL among the word lines WL1 to WLm based on an address signal supplied from the outside of the ferroelectric memory device 100 to another word. The n + 1 memory cells MC connected to the predetermined word line WL are selected with the potential higher than the line WL.

  Plate line control circuit 130 is connected to plate lines PL1-m and controls the voltages of plate lines PL1-m. Specifically, the plate line control circuit 130 makes the potential of a predetermined plate line PL among the plate lines PL1 to PLm higher than the potentials of the other plate lines PL based on the address signal. Select the plate line PL.

  The charge control circuit 150 includes p-type MOS transistors 152 to 156, and charges the dummy bit line DBL and the bit lines BL1 to n. In the present embodiment, the charging control circuit 150 starts charging the dummy bit line DBL and the bit lines BL1 to n based on the signal PON, and the dummy bit line DBL and the bit line based on the voltage of the dummy bit line DBL. The charging of BL1 to n is finished.

  In the p-type MOS transistor 152, the drive voltage VCC is supplied to the source, and the drain is connected to the sources of the p-type MOS transistors 154 and 156. The p-type MOS transistor 152 is supplied with the signal PON at the gate, and switches whether VCC is supplied to the sources of the p-type MOS transistors 154 and 156 based on the voltage of the signal PON.

  The p-type MOS transistor 154 is an example of a first MOS transistor, and has a drain and a gate connected to the dummy bit line DBL. In other words, when the absolute value of the threshold voltage is Vth1, the p-type MOS transistor 154 has a gate voltage, that is, a dummy bit line DBL voltage lower than VCC−Vth1 when VCC is supplied to the source. Is turned on when it is higher than VCC-Vth1. Therefore, the p-type MOS transistor 154 charges the dummy bit line DBL and charges the dummy bit line DBL when the voltage of the dummy bit line DBL is lower than VCC−Vth1 when VCC is supplied to the source. When the voltage exceeds VCC-Vth, charging is stopped.

  The p-type MOS transistor 156 is an example of a second MOS transistor, the source is connected to the drain of the p-type MOS transistor 152, and the drain is connected to the bit lines BL1 to BLn. The p-type MOS transistor 156 has a gate connected to the dummy bit line DBL, and switches whether to charge the bit lines BL1 to BLn based on the voltage of the dummy bit line DBL. That is, when the absolute value of the threshold voltage is Vth2, the p-type MOS transistor 156 has a bit line BL1 to 1 when the voltage of the dummy bit line DBL is lower than VCC-Vth2 when VCC is supplied to the source. When n is charged and the dummy bit line DBL is charged and the voltage exceeds VCC-Vth2, the charging is stopped. That is, the p-type MOS transistor 156 supplies VCC to the bit lines BL1 to BLn for charging until the dummy bit line DBL is saturated.

  The precharge circuit 160 includes an n-type MOS transistor 162 connected to each of the dummy bit line DBL and the bit lines BL1 to BLn. The n-type MOS transistor 162 has a source grounded and a drain connected to the dummy bit line DBL and the bit lines BL1 to BLn. The n-type MOS transistor 162 switches whether to ground the dummy bit line DBL and the bit lines BL1 to BLn based on the voltage of the signal EQ supplied to the gate.

  The sense amplifier 170 includes n-type MOS transistors 172 to 176, p-type MOS transistors 178 to 182 and NOR circuits 184 and 186, and includes memory cells MC connected to the bit lines BL1 to BLn. The data stored in is determined. Specifically, the sense amplifier 170 has a current mirror type configuration, and compares the voltage of the dummy bit line DBL received as an input with the voltages of the bit lines BL1 to n, and outputs the bit lines BL1 to BLn. Data stored in the connected memory cell MC is determined.

  That is, in the sense amplifier 170, the n-type MOS transistor 174 and the p-type MOS transistor 180, and the n-type MOS transistor 176 and the p-type MOS transistor 182 are respectively connected in series, and a dummy bit line is connected to the gate of the n-type MOS transistor 174. DBL is connected, and bit lines BL1 to BLn are connected to the gate of the n-type MOS transistor 176. The gates of the p-type MOS transistors 180 and 182 are connected to each other and further connected to the drain of the p-type MOS transistor 180.

  Then, the sense amplifier 170 compares the voltage supplied to the gate of the n-type MOS transistor 174 with the voltage supplied to the gate of the n-type MOS transistor 176, and the n-type MOS transistor 176 and the p-type MOS transistor 182 are compared. Inverted voltages at the connection point (drain) are output from the NOR circuits 184 and 186 as outputs OUT-D and OUT-1 to n, which are the comparison results, respectively.

  The sources of the n-type MOS transistors 174 and 176 are grounded via the n-type MOS transistor 172, and VCC is supplied to the sources of the p-type MOS transistors 180 and 182 via the p-type MOS transistor 178. ing. Further, the signal SAON is supplied to the gate of the n-type MOS transistor 172, and the signal / SAON, which is an inverted signal thereof, is supplied to the gate of the p-type MOS transistor 178. That is, the n-type MOS transistor 172 and the p-type MOS transistor 178 control whether to operate the sense amplifier 170 based on the voltage of the signal SAON.

  FIG. 2 is a timing chart showing the operation of the ferroelectric memory device 100 of this embodiment. With reference to FIGS. 1 and 2, the operation of the ferroelectric memory device 100 of the present embodiment will be described by taking as an example the case of reading data stored in the memory cells MC connected to the word line WL1.

  In the following example, when each signal indicates L logic, the voltage of the signal is a ground voltage, and when each signal indicates H logic, the signal voltage is VCC, which is the driving voltage of the ferroelectric memory device 100, VDD or VPP. The voltage of each signal is not limited to this, and it is sufficient that the voltage of the signal when indicating H logic is higher than the voltage of the signal when indicating L logic.

  In the initial state, the signal EQ is H logic, and each n-type MOS transistor 162 is on, so that the dummy bit line DBL and the bit lines BL1 to BLn are grounded. Further, since the signal PON is H logic, the p-type MOS transistor 152 is also turned off, and VCC is not supplied to the sources of the p-type MOS transistors 154 and 156.

  First, the word line control circuit 120 raises the voltage of the word line WL1, and turns on the n-type MOS transistor TR constituting the memory cell MC connected to the word line WL1. Thereby, the ferroelectric capacitor C constituting each memory cell MC connected to the word line WL1 is connected to the dummy bit line DBL and the bit lines BL1 to n.

  Next, the signal EQ becomes L logic, the n-type MOS transistor 162 is turned off, and the dummy bit line DBL and the bit lines BL1 to BLn are in a floating state. When the signal PON becomes L logic and the p-type MOS transistor 152 is turned on, VCC is supplied to the sources of the p-type MOS transistors 154 and 156. As a result, the dummy bit line DBL and the bit lines BL1 to BLn whose voltage is 0V are supplied with current through the p-type MOS transistors 154 and 156 and charged.

  When the dummy bit line DBL is charged and its potential rises and exceeds VCC-Vth1, the p-type MOS transistor 154 is turned off, and charging to the dummy bit line DBL is stopped. In this embodiment, since the threshold voltage Vth2 of the p-type MOS transistor 156 is substantially equal to the threshold voltage Vth1 of the p-type MOS transistor 154, the p-type MOS transistor 156 is substantially the same as the timing when the p-type MOS transistor 154 is turned off. Turn off at the same timing. That is, the charging times for the p-type MOS transistors 154 and 156 to charge the dummy bit line DBL and the bit lines BL1 to BLn are substantially equal. In the present embodiment, the p-type MOS transistors 154 and 156 form a current mirror, and the p-type MOS transistors 154 and 156 are between the start of charging and the stop of the p-type MOS transistors 154 and 156. The amount of current flowing through is substantially equal. Therefore, during this charging time, the charges accumulated in the dummy bit line DBL and the charges accumulated in the bit lines BL1 to BLn are substantially equal.

  Since the capacitance added to each bit line BL1 to n varies depending on the value of the data stored in each memory cell MC, the voltage of the charged bit lines BL1 to BLn depends on the connected memory cell MC. Depending on the value of the data stored in. Specifically, since the capacity of the memory cell MC storing data “1” is larger than the capacity of the memory cell MC storing data “0”, the voltage of the bit line BL1 is set to the memory cell connected to the memory cell MC. When the MC stores the data “1”, the voltage rises to the voltage V1 (solid line in the figure), and when the MC stores the data “0”, the voltage rises to the voltage V2 higher than the voltage V1 (the dotted line in the figure). ). That is, a potential difference is generated in the voltage of the bit line BL1 in accordance with the data stored in the memory cell MC connected to the bit line BL1.

  Further, in this embodiment, the sum of the capacity of the dummy bit line DBL and the memory cell MC connected thereto is the sum of the capacity of the memory cell MC when the bit lines BL1 to n and the data “1” are stored. The bit lines BL1 to n and the sum of the capacities of the memory cells MC when data “0” is stored are adjusted. For example, when the memory cell MC connected to the dummy bit line DBL always stores data “1” and the capacity is large, the capacity of the dummy bit line DBL is adjusted to be smaller than the capacity of the bit lines BL1 to BLn. ing. Therefore, the voltage V3 = VCC−Vth1, which is the voltage of the dummy bit line DBL after charging, is a voltage between V1 and V2. On the other hand, when the memory cell MC connected to the dummy bit line DBL always stores data “0” and the capacity is small, the capacity of the dummy bit line DBL is adjusted to be larger than the capacity of the bit lines BL1 to BLn. ing. Similarly, in this case, the voltage V3 = VCC−Vth1, which is the voltage of the dummy bit line DBL after charging, is a voltage between V1 and V2.

  Then, after the voltage of the bit lines BL1 to n is sufficiently increased, when the SAON is set to the H logic and the sense amplifier 170 is operated, the sense amplifier 170 determines that the voltage of the dummy bit line DBL and the voltage of the bit lines BL1 to n are And the comparison results are output as outputs OUT-1 to n. Specifically, when the voltage of the bit lines BL1 to n is higher than the voltage of the dummy bit line DBL, the current flowing through the n-type MOS transistor 176 is the drain voltage, that is, one input of the NOR circuit 186. It is determined that the data stored in the memory cell MC connected to the bit line is “1” by balancing with the current flowing through the p-type MOS transistor 182 due to the voltage drop. On the other hand, when the voltages of the bit lines BL1 to BLn are lower than the voltage of the dummy bit line DBL, the current flowing through the n-type MOS transistor 176 is increased by the voltage at the input of the NOR circuit 186, and the p-type MOS transistor 182 is increased. The data stored in the memory cell MC connected to the bit line is determined to be “0” in balance with the current flowing through the memory cell.

  With the above operation, in the ferroelectric memory device 100, data stored in the memory cell MC is read.

  According to the present embodiment, the voltage of the bit lines BL1 to BLn when charging is stopped differs depending on the data stored in the memory cell MC, and the sense amplifier 170 determines the data based on this voltage. , Erroneous reading of data can be prevented.

  Further, according to the present embodiment, the data stored in the memory cells MC connected to the bit lines BL1 to BLn can be determined using the voltage of the dummy bit line DBL as a reference voltage. Therefore, the ferroelectric memory device 100 does not have to have a circuit or the like that generates a reference voltage for determining data, so that the circuit scale of the ferroelectric memory device 100 can be reduced. .

  In the present embodiment, the voltages of the dummy bit line DBL and the bit lines BL1 to BLn when charging of the dummy bit line DBL and the bit lines BL1 to BLn is stopped are determined according to the capacitance added to them. Become. Therefore, according to this embodiment, the voltage of the dummy bit line DBL used as the reference voltage when charging is stopped can be easily adjusted.

  In the present embodiment, the dummy bit line DBL and the bit lines BL1 to BLn are set to have different capacitances so that the threshold voltage Vth1 of the p-type MOS transistor 154 and the threshold voltage Vth2 of the p-type MOS transistor 156 are substantially equal. Although described, the capacitances are substantially equal, and the same effect can be obtained even in a configuration in which the threshold voltage Vth1 of the p-type MOS transistor 154 and the threshold voltage Vth2 of the p-type MOS transistor 156 are set differently.

  For example, when the memory cell MC connected to the dummy bit line DBL always stores data “1”, the absolute value of the threshold voltage Vth1 of the p-type MOS transistor 154 is the absolute value of the threshold voltage Vth2 of the p-type MOS transistor 156. By setting the value smaller than the value, the voltage V3 = VCC−Vth1 which is the voltage of the dummy bit line DBL after charging becomes a voltage between V1 and V2. On the other hand, when the memory cell MC connected to the dummy bit line DBL always stores data “0”, the absolute value of the threshold voltage Vth1 of the p-type MOS transistor 154 is the absolute value of the threshold voltage Vth2 of the p-type MOS transistor 156. By setting the value larger than the value, the voltage V3 = VCC−Vth1 which is the voltage of the dummy bit line DBL after charging becomes a voltage between V1 and V2.

  The examples and application examples described through the embodiments of the present invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above-described embodiments. It is not a thing. It is apparent from the description of the scope of claims that the embodiments added with such combinations or changes or improvements can be included in the technical scope of the present invention.

It is a figure which shows one Embodiment of the ferroelectric memory device of this invention. 3 is a timing chart showing the operation of the ferroelectric memory device 100 of the present embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Ferroelectric memory device, 110 ... Memory cell array, 120 ... Word line control circuit, 130 ... Plate line control circuit, 150 ... Charge control circuit, 160 ... Precharge circuit 170 Sense amplifier

Claims (5)

A first memory cell and a second memory cell for storing predetermined data;
A first bit line connected to the first memory cell, and a second bit line connected to the second memory cell;
A first MOS transistor having a source supplied with a predetermined voltage and having a drain and a gate connected to the first bit line;
A second MOS transistor having a source supplied with the predetermined voltage, a drain connected to the second bit line, and a gate connected to the first bit line;
A determination unit for determining data stored in the second memory cell based on a voltage of the second bit line;
A ferroelectric memory device comprising: The first MOS transistor and the second MOS transistor respectively charge the first bit line and the second bit line with the predetermined voltage,
2. The ferroelectric memory device according to claim 1, wherein the determination unit determines data stored in the second memory cell when charging of the first bit line is stopped. 3. The capacitance added to the drain of the first MOS transistor is different from the capacitance added to the drain of the second MOS transistor,
The determination unit compares the voltage of the first bit line with the voltage of the second bit line and stores the voltage in the second memory cell when charging of the second bit line is stopped. 2. The ferroelectric memory device according to claim 1, wherein the determined data is determined.   4. The amount of charge that the first MOS transistor charges the first bit line is substantially equal to the amount of charge that the second MOS transistor charges the second bit line. The ferroelectric memory device as described. The threshold voltage of the first MOS transistor is different from the threshold voltage of the second MOS transistor,
The determination unit compares the voltage of the first bit line with the voltage of the second bit line and stores the voltage in the second memory cell when charging of the second bit line is stopped. 2. The ferroelectric memory device according to claim 1, wherein the determined data is determined.

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