JP2006163201A - Data transfer device, data transfer method, and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption necessary for data transfer by reducing the number of signal processing times of transfer data and reducing the number of transfer times.
Transfer data is separated by a pixel separation unit on a transmission side to increase a ratio of consecutive identical values in higher-order partial data. In addition, the encoder 53 generates information on the upper partial data in which the same value continues as a set information of the partial data value and the number of continuous data, thereby reducing the number of transfer data. Since the partial data of the upper bits is reduced in the number of transfers and the transmission is completed earlier than the partial data of the lower bits, the transfer data synthesizing unit 57 converts the lower bit partial data into the upper bit partial data that has been transferred. By using the transmission line used for the transfer of the image data, the entire number of transfer times of the image data for one line is reduced.
[Selection] Figure 3

Description

  The present invention relates to a data transfer device for transferring transfer data of a plurality of bits via a transmission line, a data transfer method using the same, and an image display device such as a matrix type liquid crystal display device using the data transfer device.

  Conventionally, for example, in a matrix type liquid crystal display device, the display screen size has increased and the transfer amount of image data has increased. In addition, since the number of colors of the display image is increased and the number of gradations of the pixel data is also increased, the number of transmission lines necessary for transferring the image data is also increased. For this reason, the power consumption required for transferring image data is also increasing.

  For example, an image display device mounted on a portable electronic information device such as a mobile phone or a digital camera is operated by a battery, so that the operation time of the device is reduced by reducing the power consumption required for transferring image data. Can be extended.

  For example, as shown in FIG. 10, the conventional liquid crystal display device 101 is arranged so that the data signal lines SL1 to SL4... And the scanning signal lines GL1 to GL3. A pixel array 102 in which pixel portions PIX (1, 1) to PIX (4, 3)... PIX (n, m) including switching elements and pixel electrodes connected to wiring adjacent to the pixel region are provided in a matrix. The data signal line driving circuit 103 connected to the data signal lines SL1 to SL4,..., The scanning signal line driving circuit 104 connected to the scanning signal lines GL1 to GL3. And a timing controller 105 for controlling.

  In the liquid crystal display device 101, external video data (image data) ED is supplied to the timing controller 105 via the external video signal line ESL, and the pixel array 102 displays the data signal line driving circuit 103 from the timing controller 105. An internal video data (image data) ID indicating a power image is transferred. Further, the scan signal line driving circuit 104 is supplied with the start pulse signal GSP and the clock signal GCK from the timing controller 105, and the scan signal is supplied to the scan signal lines GL1 to GL3. PIX (n, m) is selectively driven.

  At the time of data transfer from the timing controller 105 to the data signal line driving circuit 103, each bit of the internal video data ID corresponding to a predetermined number of pixel units is simultaneously transferred via a plurality of internal video signal lines ISL. Such transfer is repeated, and the internal video data ID for one horizontal line is transferred. Further, the transmission of the internal video data ID for each horizontal line is repeated, and the internal video data ID for one screen is transferred.

  In the conventional matrix type liquid crystal display device, since binary numbers are used for image data, a large number of bits may be inverted even if one gradation changes, and a large amount of power is consumed for data transfer. become.

  On the other hand, Patent Document 1 discloses a method of converting image data into gray code data and transferring it. In Patent Document 1, since image data is converted to gray code data and transferred, the number of data signal changes can be reduced when data with very close gradation values is transferred continuously. As a result, the number of charge / discharge cycles of the transmission line can be reduced, and power consumption can be reduced.

  Patent Document 2 provides a line memory for storing previously transferred line data, and transfers an exclusive OR of image data to be currently transferred and image data at the same position on the line memory. Is disclosed.

Since an image generally has a display state in which adjacent pixels are similar to each other, adjacent image data often has a similar value. Therefore, the method disclosed in Patent Document 2 can reduce a change in value as compared with a case where image data itself is used as transfer data. As a result, it is possible to reduce power consumption by reducing the number of charge / discharge cycles of the transmission line.
Japanese Patent Laid-Open No. 9-244589 Japanese Patent Laid-Open No. 2003-195821

  In the data transfer method of Patent Document 1 described above, since the gray code is used as the image data representation method, when the change in the gradation value of the pixel is 1, the number of code bits that change is always 1. For this reason, when the amount of change in continuous image data is 0 or 1, the number of data signal changes can be greatly reduced. However, if the amount of change in the gradation value of the pixel is often 2 or more, the number of data signal changes is not always minimized even when data of close values are continuously transferred.

  Further, in Patent Document 1 and Patent Document 2, since it is necessary to perform data transfer more than the number of image data, the number of data transfer cannot be reduced even if the number of signal changes is small. Therefore, there is a limit to reducing the power consumption required for data transfer.

  On the other hand, in order to reduce the number of data transfers, a method of compressing the transfer data amount itself can be considered. For example, in the well-known JPEG compression method, the data amount is compressed using discrete cosine transform (DCT).

  However, since the target area for image compression is not one line of data, it is necessary to provide a separate frame memory or the like when data transfer in units of lines is required, such as transfer to an image display device. Furthermore, the compression / decompression process is also complicated.

  SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and reduces the number of data signal changes and reduces the number of data transfers to reduce power consumption required for data transfer and a data transfer method using the same An object of the present invention is to provide an image display device using the data transfer device.

  The data transfer device of the present invention is a data transfer device that transfers a plurality of bits of transfer data from a transmission unit to a reception unit via a transmission line. The transmission unit includes at least each of upper bits and lower bits for each transfer data. Data separation means that separates into partial data, and a code that converts the continuous data portion into partial data values and the number of continuous data when the same transfer data is continuous for the upper partial data of each continuous transfer data And combining the information on each partial data and sending the transmission transfer data to the transmission line. When the transmission of the higher-order partial data is completed, other partial data that has not yet been transmitted A transmission line in which the other partial data is normally used and a data combining means for sending out the transmission transfer data by using the transmission line of the higher-order partial data at the same time. The above-mentioned object can be achieved.

  Preferably, the data separation means in the data transfer device of the present invention is configured such that the transfer data includes two of the upper part data and the lower part data, or the upper part data, the middle part data, and the lower part data. Separate into three.

  Further preferably, in the data separating means in the data transfer apparatus of the present invention, each of the separated partial data has the same number of bits.

  Further preferably, the encoding means in the data transfer apparatus of the present invention comprises an internal memory for storing the partial data value and an internal counter for storing the continuous number, and the partial data received from the data separation means When the comparison result is different from the partial data value stored in the internal memory, the partial data value stored in the internal memory and the counter value of the internal counter are output as a set, and the internal data The received partial data value is stored in the memory, and when the comparison result is the same, an addition process is performed to add “1” to the counter value of the internal counter.

  Further preferably, the data synthesizing means in the data transfer apparatus of the present invention is such that the transfer data is sent out by a transmission line that is normally used, the transfer data is a continuous number with the partial data value, and data Transfer additional information is generated to indicate whether the partial data that has not been transmitted is transmitted using the transmission line that is normally used or the partial data transmission line that has been transmitted. The data is transmitted together with the transmission transfer data.

  Still preferably, in a data transfer apparatus according to the present invention, the receiving unit separates the received data that has received the transmission transfer data into a plurality of partial data, and when reception of the upper partial data is completed, data reception is not yet performed. Other partial data that is not completed is received simultaneously using the transmission line in which the other partial data is normally used and the transmission line of the higher-order partial data, and the partial data of the continuous transfer data is received. When the partial data value and its continuous number are included, there is provided decoding means for generating the same high-order partial data by the continuous number and synthesizing the high-order partial data.

  Further preferably, the decoding means in the data transfer apparatus of the present invention is the case where the transfer data is sent by a transmission line normally used according to the transfer additional information, or the data sending is completed. The partial data is separated by determining whether or not the partial data that has not been transmitted is transmitted by using the transmission line that is normally used and the transmission line of the partial data that has been transmitted.

  Further preferably, the decoding means in the data transfer apparatus of the present invention determines, based on the transfer additional information, whether the transfer data is the partial data value and its continuous number, and the same partial data is determined as the continuous number. Generate only minutes.

  Further, preferably, each partial data of the transfer data in the data transfer apparatus of the present invention is represented by a color code or a gray code.

  An image display device according to the present invention includes the data transfer device according to any one of claims 1 to 9, and transmits each bit of transfer data corresponding to each pixel data from the transmission unit to the reception unit. To achieve the above objective.

  Preferably, in the image display device of the present invention, a switching element arranged in the vicinity of each intersection of a plurality of scanning signal lines and a plurality of data signal lines, and a pixel portion including a pixel electrode connected thereto, The data signal line driving circuit on the receiving unit side for driving the data signal line, the scanning signal line driving circuit for driving the scanning signal line, and the transfer data to the data signal line driving circuit via the transmission line A control board having a timing controller on the transmission unit side, and a counter board disposed opposite to the control board and sandwiching liquid crystal as a display medium between the control board and the control board.

The data transfer method of the present invention is a data transfer method for transferring a plurality of bits of transfer data from a transmission unit side to a reception unit side via a transmission line, and at the transmission unit side, at least upper bits for each transfer data When the same partial data is continuous for the upper partial data of each continuous transfer data, the continuous data part is converted into partial data values and the number of continuous data. Then, when the transmission data is sent to the transmission line by combining the information on the respective partial data and the data transmission of the higher-order partial data is completed, the other partial data for which the data transmission has not been completed yet The transmission data is sent to the receiving unit side simultaneously using the transmission line in which the other partial data is normally used and the transmission line of the higher-order partial data,
On the receiving unit side, the received data that has received the transmission transfer data is separated into a plurality of partial data, and when the reception of the higher-order partial data is completed, other partial data that has not yet been received, The other partial data is received by using the transmission line in which the other partial data is normally used and the transmission line of the higher-order partial data at the same time. Is included, the same partial data is generated by the continuous number to synthesize the partial data of the transfer data, thereby achieving the above object.

  The operation of the present invention will be described below with the above configuration.

  In general, the gradation values of image data are often biased, and the difference between the gradation values of adjacent pixels is often small. For this reason, in the transfer data for one line, the same value is often continuous in the upper bit part.

  In the present invention, since the transfer data is separated and the upper bits are treated as partial data on the data transmission side, the same partial data value is often continuous in the upper partial data of each successive transfer data. Become. Therefore, if the information of the upper partial data in which the same partial data value is continuous is transmitted as a set of the partial data value and the number of the continuous data, it is possible to reduce the number of transfer times of the partial data corresponding to the upper bits. .

  The transfer data does not necessarily need to be separated into only the upper and lower levels, and may be divided into various types such as upper, middle, and lower levels so that continuous partial data increases depending on the characteristics of the data. Further, the method of expressing the separated data may be a color code or a gray code expression.

  In the present invention, the data transmission is completed earlier than other partial data, for example, by reducing the number of times of transfer of the upper partial data corresponding to the upper bits. Therefore, it is possible to transfer the remaining other partial data using the transmission line used for transferring the upper partial data for which data transfer has been completed, thereby reducing the total number of times image data is transferred for one line. Is possible.

  Further, in the present invention, when the data receiving unit separates the received data into a plurality of partial data and receives the partial data value and the number of continuous data, the same upper partial data is converted into the continuous data. By generating as many as the number, it becomes possible to more accurately reproduce the original transfer data input to the transmission unit side.

  As described above, according to the present invention, since one data is separated into at least upper bit and lower bit partial data on the data transmitting unit side, data that is not the same value but has a small difference in gradation value is included. Even when they are continuous, since the same partial data values are often continuous in the upper partial data, it is possible to increase the ratio at which the same higher partial data values are continuous as compared to the case where the same partial data values are not separated.

  Also, when the upper partial data of the same transfer data is continuous, the partial data value is converted to the upper partial data value and the number of continuous data, and then transmitted, so that the partial data value is transferred repeatedly compared to the case of repeatedly transferring the same partial data value. The number of transfers can be greatly reduced.

  Furthermore, when transmission of any partial data is completed, other partial data for which data transfer has not yet been completed are transferred to the transmission line in which the other partial data is normally used and the partial data for which data transmission has been completed. By using the transmission lines for transmission at the same time, it is possible to reduce the number of transfers of the entire data and reduce the power consumption required for the data transfer operation. Moreover, since the transfer order of transfer data that has been transferred in one line does not change, data rearrangement processing is not required at the data transfer destination, and reception processing at the transfer destination is simplified.

  Further, according to the present invention, on the data receiving unit side, the received data is separated into a plurality of partial data, and when the transfer of the upper partial data is completed, the other partial data for which the data transfer has not been completed is performed. The same is true when the other partial data is received by using the transmission line normally used for the partial data and the transmission line of the upper partial data for which data transfer has been completed at the same time, and the value of the upper partial data and the number of continuous data are received. By generating as many partial data as the number of continuous data, the original transfer data input to the transmission unit side can be reproduced more correctly on the reception unit side.

  Therefore, according to the present invention, consumption required for data transfer can be reduced by reducing the number of data signal changes and reducing the number of data transfers without using a frame memory or the like as in the prior art or performing complicated compression / decompression processing. Electric power can be reduced.

  Hereinafter, a case where an embodiment of a data transfer device and a data transfer method using the same according to the present invention is applied to a liquid crystal display device as an image display device will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration example of a main part of the liquid crystal display device according to the present embodiment.

  In FIG. 1, a liquid crystal display device 1 is a display unit having pixel units PIX (1, 1) to PIX (n, m; n and m are natural numbers) including switching elements and pixel electrodes arranged in a matrix. A pixel array 2, a data signal line driving circuit 3 on the receiving side that drives the data signal lines SL1 to SLn of the pixel array 2, and a scanning signal line driving circuit 4 that drives the scanning signal lines GL1 to GLm of the pixel array 2. And a timing controller 5 on the transmission unit side for transmitting the digital internal video data ID of the transfer data to the data signal line driving circuit 3 via the internal video signal line ISL which is a transmission line.

  In other words, the liquid crystal display device 1 is arranged in a matrix at each intersection of the plurality of scanning signal lines GL1 to GLm and the plurality of data signal lines SL1 to SLn (each region surrounded by the scanning signal lines and the data signal lines). Pixel units PIX (1,1) to PIX (n, m) including the arrayed switching elements and pixel electrodes, the data signal line driving circuit 3 on the receiving unit side for driving the data signal lines SL1 to SLn, and the scanning signal line GL1 A control board having a scanning signal line driving circuit 4 for driving GLm and a timing controller 5 on the transmission unit side for transmitting transfer data to the data signal line driving circuit 3 via a transmission line, and facing this control board And a counter substrate sandwiching liquid crystal as a display medium between the control substrate and the control substrate.

  The data transfer apparatus of this embodiment corresponds to each pixel data via a transmission line from the data signal transmission unit of the timing controller 5 on the transmission unit side to the data signal reception unit of the data signal line drive circuit 3 on the reception unit side. Each bit of transfer data is transferred.

  Hereinafter, before describing the configuration of the data signal line driving circuit 3 and the timing controller 5 in detail, a schematic configuration example and the operation of the liquid crystal display device 1 will be briefly described. For convenience of explanation, for example, as in the case of the i-th data signal line SLi, reference is made with numerals or letters indicating the position only when the position needs to be specified, and the position need not be specified. When referring generically, the characters indicating the position are omitted for reference.

  In the liquid crystal display device 1 of the present embodiment, as described above, the pixel array 2 includes a plurality (n pieces; n is a natural number) of data signal lines SL1 to SLn and a plurality of pixel signal lines SL1 to SLn that respectively cross the data signal lines SL1 to SLn. (M) scanning signal lines GL1 to GLm, where an arbitrary integer from 1 to n and an arbitrary integer from 1 to m are j, a combination of the data signal line SLi and the scanning signal line GLj A pixel unit PIX (i, j) is provided for each.

  Each pixel unit PIX (i, j) is arranged in a region surrounded by two data signal lines and scanning signal lines.

  As an example, the case where the liquid crystal display device 1 is a liquid crystal display device will be described. As shown in FIG. 2, for example, the pixel unit PIX (i, j) has a gate connected to a scanning signal line GLj and a source thereof. A field effect transistor SW (i, j) as a switching element connected to the data signal line SLi, and a pixel capacitor Cp (one electrode (pixel electrode) connected to the drain of the field effect transistor SW (i, j)) i, j). Further, the other end of the pixel capacitor Cp (i, j) is connected to a common electrode line common to all the pixel portions PIX. The pixel capacitor Cp (i, j) includes a liquid crystal capacitor CL (i, j) and an auxiliary capacitor Cs (i, j) that is added as necessary.

  In the pixel portion PIX (i, j), when the scanning signal line GLj is selected, the field effect transistor SW (i, j) is turned on, and the display voltage applied to the data signal line SLi is changed to the pixel capacitance Cp ( i, j). On the other hand, while the selection period of the scanning signal line GLj is ended and the field effect transistor SW (i, j) is cut off, the pixel capacitor Cp (i, j) continues to hold the display voltage at the time of cut-off.

  Here, the transmittance or reflectance of the liquid crystal changes depending on the voltage applied to the liquid crystal capacitance CL (i, j). Therefore, when the scanning signal line GLj is selected and a display voltage corresponding to the video data D indicating the display state of the pixel unit PIX (i, j) is applied to the data signal line SLi as the output signal Oi, the pixel unit The display state of PIX (i, j) can be changed according to the video data D.

  In the above description, the liquid crystal display device has been described as an example. However, the pixel unit PIX (i, j) has a data signal line while the scanning signal indicating the selected state is applied to the scanning signal line GLj. As long as the brightness (luminance) of the pixel unit PIX (i, j) can be adjusted according to the value of the data signal applied to the SLi, it can be of any other configuration regardless of whether it is self-luminous or not. A pixel portion can also be used.

  In the liquid crystal display device 1, the scanning signal line drive circuit 4 shown in FIG. 1 selects a predetermined voltage signal for turning on the field effect transistor SW (i, j) for each scanning signal line GL 1 to GLm in a selection period. A scanning signal indicating whether or not there is output. Further, the scanning signal line driving circuit 4 changes the scanning signal line GLj that outputs a scanning signal indicating the selection period based on a timing signal such as a clock signal GCK or a start pulse signal GSP supplied from the timing controller 5 or the like, for example. is doing. Thereby, the scanning signal lines GL1 to GLm are sequentially selected at a predetermined timing.

  Further, the data signal line driving circuit 3 is configured to display the pixel units PIX (1, j) ˜ connected to the currently selected scanning signal line GLj based on the internal video data ID supplied through the internal video signal line ISL. The display state of PIX (n, j) is specified, and the output signals O1 to On corresponding to the video data D (1, j) to D (n, j) having values corresponding to the respective display states are generated, It outputs to each of the data signal lines SL1 to SLn.

  On the other hand, each pixel unit PIX (1, j) to PIX (n, j) is given to the data signal lines SL1 to SLn corresponding to itself while the scanning signal line GLj corresponding to itself is selected. In accordance with the voltage value of the data signal, the brightness and the transmittance when emitting light are adjusted to determine its own brightness.

  The scanning signal line driving circuit 4 sequentially selects the scanning signal lines GL1 to GLm. Therefore, it is possible to set all the pixel portions PIX (1, 1) to PIX (n, m) of the pixel array 2 to the brightness indicated by the video data D. The displayed image can be updated.

  The liquid crystal display device 1 may update the display of the pixel array 2 in units of frames (for example, in units of one screen), or divides one frame into a plurality of fields and displays the pixel array 2 in units of fields. However, in the following, as an example, a case where display is performed in units of frames will be described.

  The liquid crystal display device 1 according to this embodiment displays an image on the pixel array 2 by repeating display update in units of frames. In the liquid crystal display device 1, when the timing controller 5 transfers the internal video data ID for displaying each frame via the internal video signal line ISL, for example, the internal video data ID for a certain frame is used. Are transferred in a time-division manner, for example, by transferring the internal video data ID for the next frame after transferring all of the internal video data ID for the next frame.

  The frame is composed of a plurality of horizontal lines. For example, after all the internal video data ID for a certain horizontal line is transferred on the internal video signal line ISL, the internal video for the next horizontal line is transmitted. The internal video data ID for each horizontal line is transferred in a time-sharing manner by transferring the data ID.

  The timing controller 5 also time-divisionally drives the internal video signal line ISL when transferring the internal video data ID... For one horizontal line, and the internal timing corresponding to a predetermined number of video data D is transferred. After the video data ID is collectively transferred via the internal video signal line ISL, the internal video data ID corresponding to the next video data D is transferred.

  In the present embodiment, the unit for transferring the internal video data ID is, for example, one pixel unit, and the internal video data ID (i, i) corresponding to the video data D (i, j) of the one pixel unit PIX (i, j). , J) are transferred in a batch. Accordingly, each pixel unit PIX (i, j) is a pixel unit capable of selecting different display states of 2q bits, such as a pixel unit capable of displaying 2q bit gradation and a pixel unit capable of displaying 2q bit color. is there.

  Furthermore, in the present embodiment, for example, the order in which the internal video data ID (i, j) is transferred is, for example, from left to right, and the pixel unit PIX (i, j) corresponding to the internal video data ID (i, j). ) In the order corresponding to the horizontal position (i).

  In the following, the timing controller 5 receives digital external video data ED... And external control indicating each frame from an external device of the liquid crystal display device 1 such as a computer video board via an external video signal line ESL. As an example, the timing controller 5 and the data signal line drive circuit 3 receive the signal EC and generate an internal video data ID based on the external video data ED and the external control signal EC. A detailed configuration example will be described.

  As an example of the case of being transferred for each frame, the external video data ED for each frame is transferred to the external video signal line ESL in a time-sharing manner as with the internal video data ID. When transferring the external video data ED for one frame, the external video data ED for each horizontal line is transferred in a time division manner. The external video signal line ESL is also time-division driven when transferring external video data ED... For one horizontal line.

  In the liquid crystal display device 1 according to the present embodiment, a digital signal indicating a display state to be displayed by the pixel unit PIX is transferred to the external video signal line ESL as the external video data ED corresponding to one pixel unit PIX. Yes.

  Further, in the present embodiment, as an example, the unit and the order when the internal video data ID for one horizontal line is transferred in time division and the external video data ED for one horizontal line are transferred in time division. Units and order are set the same. Therefore, for example, in the case of a pixel portion that can select a 2q-bit display state, the number of external video signal lines ESL is set to 2q, and each external video data ED. The pixel portions PIX (i, j) corresponding to i, j) are transferred in the order according to the horizontal position (i).

  First, the timing controller 5 will be described in detail.

  As shown in FIG. 1, in the liquid crystal display device 1 of the present embodiment, the timing controller 5 includes a data signal transmission unit 5a as a transmission unit and a timing control unit 5b.

  The timing controller 5b receives an external control signal EC from an external device of the liquid crystal display device 1 and outputs a scan signal to the scan signal line drive circuit 4 to the start pulse signal GSP and the scan signal line GLj. In addition, the timing control unit 5b determines the validity period of the external video data ED ... transferred in a time division manner, and for each horizontal line, the data signal transmission unit 5a has one horizontal line effective. A period, a timing signal for the data signal transmission unit 5a to capture data, and the like are output.

  FIG. 3A is a block diagram illustrating a configuration example of the data signal transmission unit 5a in FIG. 1, and FIG. 3B is a block diagram illustrating a configuration example of the data signal reception unit 3a in FIG.

  In FIG. 3A, a data signal transmission unit 5a on the transmission unit side which is a data transfer source includes a transfer control unit 51, a pixel data separation unit 52 as a data separation unit, and an encoder 53 as an encoding unit. And an encoder 54, a buffer memory 55 and a buffer memory 56 as storage means, and a transfer data synthesis unit 57 as data synthesis means.

  The transfer control unit 51 controls the pixel data separation unit 52 to take in the external image data ED based on the control signal indicating the effective period of one horizontal line received from the timing control unit 5b. A control signal DC for transmitting the image data of the horizontal line to the data transfer destination is output.

  The pixel data separation unit 52 separates pixel data (transfer data) corresponding to one pixel part PIX of the captured external image data ED into predetermined partial data. In the present embodiment, for example, it is assumed that pixel data corresponding to 2q bits of one pixel unit PIX is separated into two partial data of upper partial data of upper q bits and lower partial data of lower q bits.

  Note that the number of bits of the signals constituting the upper and lower partial data need not be the same. For example, when the rate of transferring image data with little change is high, the number of times of data transfer may be further reduced by setting a larger number of bits to be allocated to partial data on the upper bit side. . Furthermore, the data is not limited to the upper and lower partial data, and may be separated into a plurality of partial data of three or more. In the present embodiment, as an example, the same q bits are divided into two.

  The two pieces of partial data thus separated are output to the encoders 53 and 54, respectively.

The encoder 53 has an internal memory for storing partial data values and an internal counter for storing the number of partial data of continuous transfer data (pixel data), and a control signal from the timing control unit 5b. Based on the above, the following processing is performed while repeatedly receiving the upper part data of each transfer data for one horizontal line from the pixel data separation unit 52.
(Processing of the encoder 53)
The encoder 53 resets the internal counter to “0” when the effective period signal of one horizontal line supplied from the timing control unit 5b becomes effective, and starts processing. When the valid period signal of one horizontal line supplied from the timing control unit 5b becomes invalid, the value stored in the buffer memory 55 is output to the transfer data synthesis unit 57, and then the internal counter The counter value is output to the buffer memory 55, and the processing of the encoder 53 is terminated.

  The encoder 53 performs the following determination on the upper bit partial data received from the data separator 52.

(1) When the value of the internal counter is “0” When the value of the internal counter is “0”, since it is the first upper part data of one horizontal line, the internal counter is set to “1” and stored in the internal memory. Save the received partial data value.

(2) When the value of the internal counter is 2 ^q −1 (2 to the power of q−1) When the value of the internal counter is 2 ^q −1, the maximum number of consecutive upper part data that can be expressed by q bits Therefore, the partial data value saved in the internal memory and the counter value of the internal counter are output to the buffer memory 55 as a set. The internal counter is set to “1” and the received partial data value is stored in the internal memory.

(3) When the received higher-order partial data has a value different from the partial data value stored in the internal memory If the received higher-order partial data has a value different from the partial data value stored in the internal memory, the data is transferred to the buffer memory 55. The partial data value stored in the internal memory and the counter value of the internal counter are output as a set. The internal counter is set to “1”, and the received partial data value is recorded in the internal memory.

(4) When the received upper partial data is the same value as the partial data value stored in the internal memory If the received upper partial data is the same value as the partial data value stored in the internal memory, the same partial data value is Since it is continuous, a process of adding “1” to the counter value of the internal counter is performed.
(Processing of the encoder 54)
The encoder 54 outputs the partial data of the lower bits for one horizontal line received from the pixel data separation unit 52 to the buffer memory 56 as it is based on the control signal from the timing control unit 5 b. That is, in the encoder 54, even if the same value is continuous, it is not converted into data and the continuous number.

The buffer memories 55 and 56 are storage circuits that are readable and writable in a first-in first-out manner. The buffer memory 55 stores the number of consecutive upper data values and the buffer memory 56 stores lower data values.
(Processing of transfer data synthesis unit 57)
Based on the control signal from the timing control unit 5b, the transfer data synthesizing unit 57 synthesizes information related to the transfer data stored in the buffer memory 55 and the buffer memory 56 and outputs it as transfer image data ID. At this time, the information on each partial data is combined and sent to the transmission line, and when the transmission of any partial data is completed, the other partial data that has not yet been sent is transferred to the other partial data. Transmission is performed using a transmission line that is normally used and a transmission line for partial data for which data transmission has been completed.

  Further, the transfer data combining unit 57 generates and outputs transfer additional information IF as information indicating a configuration example of the transfer image data ID. This transfer additional information IF indicates the following three types of states 1-3.

  (1) State 1: When transfer data is sent by a transmission line that is normally used, the upper q bits of the transfer data represent the partial data value of the upper partial data, and the lower q bits represent the partial data of the lower partial data Represents a value.

  (2) State 2: When the same partial data is continuous, the upper q bits represent the number of consecutive upper partial data, and the lower q bits represent the data value of the lower partial data.

  (3) State 3: When the partial data whose transmission has not been completed is transmitted simultaneously using the transmission line in which the partial data is normally used and the transmission line of the partial data whose transmission has been completed, the upper q bits and the lower q Both bits represent the partial data value of the lower partial data.

  In the following, details of the process of combining the information related to the transfer data by the transfer data combining unit 57 will be described.

  The transfer data combining unit 57 combines transfer data when the upper bit encoder 53 and the lower bit encoder 56 complete reading of each partial data of transfer data for one horizontal line. Start processing.

(1) When there is partial data that has not yet been read out in both the buffer memory 55 and the buffer memory 56, the partial data value stored from the buffer memory 55 and the set of the number of continuous data are read and transferred. The value of the partial data read from the buffer memory 55 is set in the upper q bits of the image data ID. Further, one partial data is read from the buffer memory 56, and the read value is set in the lower q bits of the transfer image data ID. Further, the transfer additional information IF is set to state 1. One piece of transfer image data is sent at an appropriate timing determined by the timing controller 5b.

(1-1) When the number of continuous data is 2 or more When the number of continuous data is 2 or more, the following processing is performed continuously.

  The number of continuous data read from the buffer memory 55 is set in the upper q bits of the transfer image data ID. Further, one partial data is read from the buffer memory 56, and the read value is set in the lower q bits of the transfer image data ID. Further, the transfer additional information IF is set to state 2. One piece of transfer image data is sent at an appropriate timing determined by the timing controller 5b.

(2) When there is partial data that has not yet been read only in the buffer memory 56, one partial data is read from the buffer memory 56, and the read value is set in the upper q bits of the transfer image data ID. Subsequently, one partial data is read from the buffer memory 56, and the read value is set in the lower q bits of the transfer image data ID. At this time, if there is no partial data that has not been read in the buffer memory 56, all the lower q bits of the transfer image data ID are set to “0”. Further, the transfer additional information IF is set to state 3. One piece of transfer image data is sent at an appropriate timing determined by the timing controller 5b.

  In both the buffer memory 55 and the buffer memory 56, when all the partial data has been read, the synthesis process of information relating to the transfer data ends.

   Hereinafter, a series of processing by the data signal transmission unit 5a of the present embodiment will be described in detail with a specific example.

  As shown in FIG. 4, it is assumed that one horizontal line is composed of 12 pieces of image data. In this example, pixel data corresponding to one pixel portion PIX is expressed by binary 6 bits (q = 3).

(Processing of the pixel data separation unit 52)
As shown in FIG. 4, the pixel data separation unit 52 separates each pixel data into partial data composed of upper 3 bits and partial data composed of lower 3 bits. In FIG. The data value “1” of 1 is “001110” in binary, the partial data flow graph of the upper bits is “001”, and the partial data of the lower bits is “110”.

(Processing of the encoder 53)
The partial data of the upper bits is input to the encoder 53, and the buffer memory 55 stores a set of the number of pieces of continuous data as shown in FIG. This procedure will be described in detail as follows.

  First, the encoder 53 receives No. 1 which is the first data of the upper bit partial data. When 1 is received, since this is the first partial data of one horizontal line, the value of the internal counter becomes “1”, and “001” is stored in the internal memory.

  Subsequently, the encoder 53 receives the No. of the partial data of the upper bits. 2-No. 7 is received, but since the value is the same as “001” stored in the internal memory, the value of the internal counter is incremented by “1”. When the partial data value of 7 is read, the value of the internal counter becomes “7”.

  Subsequently, the encoder 53 performs No. When the partial data value of 8 is read, the internal counter value “7” is the maximum number that can be expressed in 3 bits, so the combination of the partial data “001” and the internal counter value “7” is the buffer memory. 55 is recorded at address 1. The internal counter value is set to “1” and No. is stored in the internal memory. A value “8” of “000” is stored.

  Subsequently, the encoder 53 performs No. The partial data value “001” of 9 is received, but since this is different from “000” stored in the internal memory, the value of “000” stored in the internal memory and the internal counter value of 1 The set is recorded at address 2 of the buffer memory 55. The internal counter value is set to 1 and No. is stored in the internal memory. The value “001”, which is the value of 9, is stored.

  Subsequently, the encoder 53 receives the No. of the partial data of the upper bits. 10-No. 12 is received, but since the value is the same as “001” stored in the internal memory, the value of the internal counter is incremented by one. At the time when 12 partial data values are read, the value of the internal counter becomes 4.

  When the reception of all the upper bit partial data is completed and the valid period signal of one horizontal line becomes invalid, a set of 4 of the value “001” and the internal counter value stored in the internal memory is It is recorded at address 3 of the buffer memory 55.

(Processing of the encoder 57)
The partial data of the lower bits is input to the encoder 54, and the partial data value is stored in the buffer memory 56 as shown in FIG. Here, No. 1 is assigned to addresses 1 to 12 of the buffer memory 56. Partial data 1 to 12 are stored.

(Processing of transfer data synthesis unit 57)
When all the partial data has been read in the encoder 53 and the encoder 54, the transfer data combining unit 57 sequentially outputs the transfer image data ID and the transfer additional information IF shown in FIG. This procedure will be described in detail as follows.

  First, since there is partial data that has not been read out in both the buffer memories 55 and 56, the transfer data synthesis unit 57 sets a combination of the partial data value “001” and the number of consecutive data “7” from the buffer memory 55. And “001” is set in the upper 3 bits of the transfer image data ID. Also, the partial data “110” is read from the buffer memory 56 and “110” is set in the lower 3 bits of the transfer image data ID. Further, the transfer additional information IF is set to state 1. Transfer image data “001 110” is transmitted at an appropriate timing determined by the timing control unit 5b.

  Next, since the number of continuous data is 7 and corresponds to the case of 2 or more, the transfer data synthesis unit 57 performs the following processing in succession. In the upper 3 bits of the transfer image data ID, “7” which is the number of continuous data, that is, binary “111” is set. Also, the partial data “101” is read from the lower-bit buffer memory 56 and “101” is set in the lower 3 bits of the transfer image data ID. Further, the transfer additional information IF is set to state 2. The transfer image data “111 101” is transmitted at an appropriate timing determined by the timing control unit 5b.

  Furthermore, since there is partial data that has not yet been read out in both the buffer memories 55 and 56, the transfer data synthesis unit 57 has the number of data “1” that is continuous with the partial data value “000” from the buffer memory 55. The set is read and “000” is set in the upper 3 bits of the transfer image data ID. Further, the partial data “111” is read from the buffer memory 56 and “111” is set in the lower 3 bits of the transfer image data ID. Further, the transfer additional information IF is set to state 1. Transfer image data “000 111” is transmitted at an appropriate timing determined by the timing control unit 5b. Here, since the number of continuous data is 1, it does not correspond to the case of 2 or more.

  Furthermore, since there is partial data that has not yet been read out in both the buffer memories 55 and 56, the transfer data synthesis unit 53 has the number of pieces of data “4” continuous with the partial data value “001” from the buffer memory 55. The set is read and “001” is set in the upper 3 bits of the transfer image data ID. Also, the partial data “100” is read from the buffer memory 56 and “100” is set in the lower 3 bits of the transfer image data ID. Further, the transfer additional information IF is set to state 1. Transfer image data “001 100” is transmitted at an appropriate timing determined by the timing controller 5b.

  Furthermore, since the number of continuous data is 4 and corresponds to the case of 2 or more, the transfer data combining unit 57 performs the following processing in succession. In the upper 3 bits of the transfer image data ID, “4” which is the number of continuous data, that is, “100” in binary number is set. Also, the partial data “110” is read from the buffer memory 56 and “110” is set in the lower 3 bits of the transfer image data ID. Further, the transfer additional information IF is set to state 2. Transfer image data “100 110” is transmitted at an appropriate timing determined by the timing controller 5b.

  Here, this corresponds to the case where all partial data is read from the buffer memory 55 and there is partial data that has not been read yet only in the buffer memory 56.

  Further, the transfer data synthesis unit 57 reads the partial data “010” from the buffer memory 56 and sets “010” in the upper 3 bits of the transfer image data ID. Subsequently, the partial data “000” is read from the buffer memory 56 and “000” is set in the lower 3 bits of the transfer image data ID. Further, the transfer additional information IF is set to state 3. Transfer image data “010 000” is transmitted at an appropriate timing determined by the timing control unit 5b.

  Thereafter, the process in the case where there is partial data that has not yet been read only in the buffer memory 56 is repeated.

  The eighth and ninth data in the buffer memory 56 are set to the upper 3 bits and the lower 3 bits, respectively, and the transfer image data “111 010” is transmitted. The tenth and eleventh data in the buffer memory 56 are set to the upper 3 bits and the lower 3 bits, respectively, and the transfer image data “011 010” is transmitted. Further, the 12th data in the buffer memory 56 is set to the upper 3 bits. Here, since all the data in the buffer memory 56 has been read, “000” is set in the lower 3 bits, and the transfer image data “100 000” is transmitted.

  As described above, the 12 pieces of pixel data are transmitted by the data signal transmission unit 5a with the number of transfer times of nine.

  Next, the data signal line driving circuit 3 will be described.

  As shown in FIG. 1, in the liquid crystal display device 1 of the present embodiment, the data signal line driving circuit 3 includes a data signal receiving unit 3a and a data signal line driving unit 3b as receiving units.

  The data signal line driving unit 3b is configured based on the internal video data (image data) ID supplied from the data signal receiving unit 3a to each pixel PIX (1, j) ˜ connected to the currently selected scanning signal line GLj. The display state of PIX (n, j) is specified, and the output signals O1 to On corresponding to the video data D (1, j) to D (n, j) having values corresponding to the respective display states are generated, It outputs to each of the data signal lines SL1 to SLn.

  FIG. 3B is a block diagram illustrating a configuration example of a main part of the data signal receiving unit 3a in the liquid crystal display device 1 of FIG.

  In FIG. 3, the data signal receiving unit 3a of the present embodiment includes a transfer control unit 31, a decoder 33 and a decoder 34 as decoding means, and a buffer memory 35 and a buffer memory 36 as storage means. Have.

  In the transfer control unit 31, the transfer image data ID is taken in based on the control signal DC received from the data signal transmission unit 5a of the timing controller 5, and a control signal for outputting the image data to the data signal line driving circuit 3b is received. Is output.

  The buffer memories 35 and 36 are storage circuits that can be read and written by a first-in first-out method. The buffer memory 35 stores the upper partial data value and the continuous number thereof, and the buffer memory 36 stores the lower partial data value.

  Received data is input to the decoders 33 and 34 and separated into a plurality of partial data.

  At this time, in the decoders 33 and 34, the transfer additional information IF supplied from the data signal transmission unit 5a of the timing controller 5 determines whether the transfer data is a partial data value and its continuous number, and the same part. Data for the continuous number is generated.

  In addition, in the decoders 33 and 34, when data reception of any partial data is completed, the partial data for which data reception has not been completed has been completed. It is received using the partial data transmission line at the same time. In this case, in the decoders 33 and 34, the transfer additional information IF supplied from the data signal transmission unit 5a of the timing controller 5 is a case where the transfer data is sent out through a transmission line that is normally used, or The partial data is separated by determining whether or not the partial data for which data transmission has not been completed is transmitted using the transmission line for which data transmission is normally performed and the transmission line for the partial data for which data transmission has been completed. . In this way, the partial data are combined to generate image data.

  Hereinafter, the operation of the data signal receiving unit 3 will be described in detail.

(Processing of the decoder 33)
The decoder 1 has an internal memory for storing the upper part data currently being output and a counter for storing the number of upper data not yet output. In the initial state, the upper part data currently being output: None The number of upper partial data not yet output is set to 0.

(1) When data in state 1 is received (1-1) When the number of high-order partial data that has not been output is “0” and there is no data in the buffer memory 35 The decoder 33 has received from the timing controller 5 The upper q bits of the transfer image data ID are set to the upper q bits of the output image data, and are set to the upper partial data currently being output. At this time, the number of upper partial data not yet output remains “0” and is not changed.

(1-2) When the number of non-output upper part data is “0” and there is data in the buffer memory 35, the decoder 33 reads the upper part data value and the number of continuous data from the buffer memory 35, The read partial data value is set to the upper q bits of the output image data and set to the upper partial data currently being output. Also, the number obtained by subtracting “1” from the number of read continuous data is set as the number of upper partial data that has not been output.

(1-3) When the number of upper partial data not output is 1 or more The decoder 33 stores the upper q bits of the transfer image data ID received from the timing controller 5 in the buffer memory 35 as an upper partial data value. , “1” is stored as the number of continuous data. Further, the upper part data currently being output is set to the upper q bits of the output image data, and the number of upper part data not yet output is reduced by “1”.

(2) When data in state 2 is received (2-1) When there is no data in the buffer memory 35 The decoder 33 sets the upper partial data currently being output to the upper q bits of the output image data, A number obtained by subtracting “2” from the number represented by the upper q bits of the transfer image data ID received from the timing controller 5 is set as the number of upper partial data not yet output.

(2-2) When there is data in the buffer memory 35 The decoder 33 uses the upper q bits of the transfer image data ID received from the timing controller 5 as the number of continuous data stored last in the buffer memory 35. Rewrite the number represented by. Also, the upper part data currently being output is set to the upper q bits of the output image data, and the number of upper part data that has not been output is reduced by “1”.

(3) When data in state 3 is received or no data is received (3-1) When the number of upper partial data not yet output is “0” and there is no data in the buffer memory 35 Output processing is completed Therefore, the decoder 33 notifies the transfer control unit 31 of a completion notification.

(3-2) When the number of non-output upper part data is “0” and there is data in the buffer memory 35, the decoder 33 reads the upper part data value and the number of continuous data from the buffer memory 35, The read partial data value is set to the upper q bits of the output image data, and is set to the upper partial data currently being output. Also, the number obtained by subtracting “1” from the number of read continuous data is set as the number of upper partial data that has not been output.

(3-3) When the number of non-output high-order partial data is “1” or more The decoder 33 sets the high-order partial data currently being output to the high-order q bits of the output image data, and the non-output high-order partial data Decrease the number by “1”.

(Processing of the decoder 34)
(1) When receiving data of state 1 or state 2 The decoder 34 sets the lower q bits of the transfer image data ID received from the timing controller 5 to the lower q bits of the output image data.

(2) When Data in State 3 is Received The decoder 34 stores the upper q bits of the transfer image data ID received from the timing controller 5 in the buffer memory 36 and stores the lower q bits in the buffer memory 36. . The lower partial data value is read from the buffer memory 36, and the read partial data value is sequentially set to the lower q bits of the output image data.

(3) When no data is received (3-1) When there is data in the buffer memory 36 and the completion notification of the decoder 33 is not received from the transfer control unit 31. The decoder 34 is a buffer memory. The lower partial data value is read from 36, and the read partial data value is set in the lower q bits of the output image data.

(3-2) When there is no data in the buffer memory 36 or when the completion notification of the decoder 33 is received from the transfer control unit 31, the output process by the decoder 34 is completed.
(Concrete example)
Hereinafter, a series of processing by the data signal receiving unit 3a of the present embodiment will be described in detail with a specific example. Of the upper part data processing by the decoder 33 and the lower part data processing by the decoder 34, the processing of the decoder 33 will be described.

(Processing of the decoder 33)
When the transfer image data ID shown in FIG. 7 is input to the decoder 33, the upper partial data value shown in FIG. 8 is output. This procedure will be described in detail as follows.

  Prior to the start of transfer, the number of upper partial data not yet output is initialized to “0”.

  First, the decoder 33 receives the data “001 110” in the state 1 as the first transfer image data. At this time, the number of upper partial data not output is “0”, and there is no data in the buffer memory 35. Therefore, “001” that is the upper 3 bits of the data “001 110” is set as the upper 3 bits of the output image data. Also, the upper part data currently being output is also set to “001”.

  Next, the decoder 33 receives the data “111 101” in the state 2 as the second transfer image data. At this time, there is no data in the buffer memory 35. Therefore, “001”, which is the upper partial data currently being output, is set as the upper 3 bits of the output image data. Further, the upper 3 bits of the received value is “7”, and “5”, which is the number obtained by subtracting 2 from 7 is set as the number of upper partial data that has not been output.

  Further, the decoder 33 receives the data “000 111” in the state 1 as the third transfer image data. At this time, the number of upper partial data not output is “5”, which is 1 or more. Therefore, “000”, which is the upper 3 bits of the data “000 111”, is stored in the buffer memory 35 as the upper partial data value. Further, “1” is stored as the number of continuous data. Further, “001”, which is the upper partial data currently being output, is set as the upper 3 bits of the output image data. The number of upper partial data that has not been output is set to “4”, which is a number obtained by subtracting 1 from “5”.

  Further, the decoder 33 receives the data “001 100” in the state 1 as the fourth transfer image data. At this time, the number of upper partial data not output is “4”, which is 1 or more. Therefore, “001”, which is the upper 3 bits of the data “001 100”, is stored in the buffer memory 35 as the upper partial data value. Further, “1” is stored as the number of continuous data. Further, “001”, which is the upper partial data currently being output, is set as the upper 3 bits of the output image data. The number of upper partial data that has not been output is set to “3”, which is the number obtained by subtracting “1” from “4”.

  Further, the decoder 33 receives the data “100 110” in the state 2 as the fifth transfer image data. At this time, two data are stored in the buffer memory 35. The number of continuous data “1” last stored in the buffer memory 35 is rewritten to “4” expressed by the upper 3 bits of the received value. Further, “001”, which is the upper partial data currently being output, is set as the upper 3 bits of the output image data. The number of upper partial data that has not been output is set to “2”, which is the number obtained by subtracting “1” from “3”.

  Further, the decoder 33 receives the data “010 000” in the state 3 as the sixth transfer image data. At this time, the number of upper partial data not output is “2”, which is 1 or more. Therefore, “001”, which is the upper partial data currently being output, is set as the upper 3 bits of the output image data. The number of upper partial data not yet output is set to “1”, which is a number obtained by subtracting “1” from “2”.

  Further, the decoder 33 receives the data “111 010” in the state 3 as the seventh transfer image data. At this time, the number of upper partial data not yet output is “1”, which is 1 or more. Therefore, “001”, which is the upper partial data currently being output, is set as the upper 3 bits of the output image data. The number of upper partial data that has not been output is set to “0”, which is a number obtained by subtracting “1” from “1”.

  Further, the decoder 33 receives the data “011 010” in the state 3 as the eighth transfer image data. At this time, the number of upper partial data that has not been output is “0”, and data is stored in the buffer memory 35. Therefore, the upper partial data value “000” and the number of consecutive data “1” are read from the buffer memory 35, and the read partial data value “000” is set as the upper 3 bits of the output image data. Are set as the upper partial data currently being output. The number “0” obtained by subtracting “1” from the number of read continuous data “1” is set as the number of upper partial data not yet output.

  Further, the decoder 33 receives the data “100 000” in the state 3 as the ninth transfer image data. At this time, the number of upper partial data that has not been output is “0”, and data is stored in the buffer memory 35. Accordingly, the upper partial data value “001” and the number of consecutive data 4 are read from the buffer memory 35, and the read partial data value “001” is set as the upper 3 bits of the output image data. Are set as the upper partial data currently being output. A number “3” obtained by subtracting “1” from the number of consecutive data read “4” is set as the number of upper partial data not yet output.

  At the next timing, the data reception by the decoder 33 is completed. At this time, the number of upper partial data not output is “3”, which is 1 or more. Therefore, “001”, which is the upper partial data currently being output, is set as the upper 3 bits of the output image data. The number of upper partial data that has not been output is set to “2”, which is the number obtained by subtracting “1” from “3”.

  Furthermore, the data reception by the decoder 33 is completed at the next timing. At this time, the number of upper partial data not output is “3”, which is 1 or more. Therefore, “001”, which is the upper partial data currently being output, is set as the upper 3 bits of the output image data. The number of upper partial data that has not been output is set to “1” obtained by subtracting “1” from “2”.

  Furthermore, the data reception by the decoder 33 is completed at the next timing. At this time, the number of upper partial data not yet output is “1”, which is 1 or more. Therefore, “001”, which is the upper partial data currently being output, is set as the upper 3 bits of the output image data. The number of upper partial data not yet output is set to “0” obtained by subtracting “1” from “1”.

  Furthermore, data reception is completed at the next timing. At this time, the number of high-order partial data not yet output is “0”. Therefore, the processing of the decoder 33 is completed, and the transfer control unit 31 is notified of the completion of the processing.

(Processing of the decoder 34)
When the transfer image data shown in FIG. 7 is input to the decoder 34, the lower partial data value shown in FIG. 9 is output. This procedure will be described in detail as follows.

  First, the decoder 34 receives the data “001 110” in the state 1 as the first transfer image data. As a result, “110”, which is the lower 3 bits of the received value, is set as the lower 3 bits of the output image data.

  Next, the decoder 34 receives the data “111 101” in the state 2 as the second transfer image data. As a result, “101”, which is the lower 3 bits of the received value, is set as the lower 3 bits of the output image data.

  Further, the decoder 34 receives the data “000 111” in the state 1 as the third transfer image data. As a result, “111” which is the lower 3 bits of the received value is set as the lower 3 bits of the output image data.

  Further, the decoder 34 receives the data “001 100” in the state 1 as the fourth transfer image data. As a result, “100” which is the lower 3 bits of the received value is set as the lower 3 bits of the output image data.

  Further, the decoder 34 receives the data “100 110” in the state 2 as the fifth transfer image data. As a result, “110”, which is the lower 3 bits of the received value, is set as the lower 3 bits of the output image data.

  Further, the decoder 34 receives the data “010 000” in the state 3 as the sixth transfer image data. At this time, “010” that is the upper 3 bits of the received value is stored in the buffer memory 36, and then “000” that is the lower 3 bits of the received value is stored in the buffer memory 36. The lower partial data value “010” is read from the buffer memory 36, and the read partial data value “010” is set as the lower 3 bits of the output image data.

  Further, the decoder 34 receives the data “111 010” in the state 3 as the seventh transfer image data. At this time, “111”, which is the upper 3 bits of the received value, is stored in the buffer memory 36, and then, “010”, which is the lower 3 bits of the received value, is stored in the buffer memory 36. The lower partial data value “000” is read from the buffer memory 36, and the read partial data value “000” is set as the lower three bits of the output image data.

  Further, the decoder 34 receives the data “011 010” in the state 3 as the eighth transfer image data. At this time, “011” which is the upper 3 bits of the received value is stored in the buffer memory 36, and then “010” which is the lower 3 bits of the received value is stored in the buffer memory 36. The lower partial data value “111” is read from the buffer memory 36, and the read partial data value “111” is set as the lower three bits of the output image data.

  Further, the decoder 34 receives the data “100 000” in the state 3 as the ninth transfer image data. At this time, “100” which is the upper 3 bits of the received value is stored in the buffer memory 36, and then “000” which is the lower 3 bits of the received value is stored in the buffer memory 36. The lower partial data value “010” is read from the buffer memory 36, and the read partial data value “010” is set as the lower 3 bits of the output image data.

  At the next timing, reception of data by the decoder 34 is completed, and data is stored in the buffer memory 36. Therefore, the lower partial data value “011” is read from the buffer memory 36, and the read partial data value “011” is set as the lower three bits of the output image data.

  Further, at the next timing, the reception of data by the decoder 34 is completed, and the data is stored in the buffer memory 36. Therefore, the lower partial data value “010” is read from the buffer memory 36, and the read partial data value “010” is set as the lower three bits of the output image data.

  Further, at the next timing, the reception of data by the decoder 34 is completed, and the data is stored in the buffer memory 36. Therefore, the lower partial data value “100” is read from the buffer memory 36, and the read partial data value “100” is set as the lower three bits of the output image data.

  Further, at the next timing, the reception of data by the decoder 34 is completed and the data is stored in the buffer memory 36, but the transfer control unit 31 notifies the completion of the upper partial data processing of the decoder 33. Therefore, the lower part data processing by the decoder 34 is completed.

  In this manner, 12 pieces of pixel data are restored by the data signal receiving unit 3a from the data received from the data signal transmitting unit 5a with the number of transfer times of nine.

  As described above, according to the present embodiment, on the data sending unit side, the transfer data is separated and handled as each partial data, and the ratio in which the same partial data value continues in the partial data corresponding to the upper bits is high. Thus, the number of signal changes can be reduced. Also, by transmitting the partial data information with the same value as a set of the partial data value and the number of continuous data, the number of partial data transfers corresponding to the upper bits can be reduced. .

  Further, according to the present embodiment, the transmission is completed earlier than the partial data corresponding to the lower bits by reducing the number of transfer times of the partial data corresponding to the upper bits. Therefore, a transmission line used for transferring partial data corresponding to the upper bits can be used for transferring partial data corresponding to the lower bits, thereby reducing the total number of times image data is transferred for one line. it can.

  Further, according to the present embodiment, when the received data is separated into a plurality of partial data on the data reception side, and the partial data and the number of consecutive pieces of data are received, the number of consecutive pieces of the same partial data. By generating only the amount of data, the original data input to the transmission side can be correctly reproduced.

  In addition, as mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to a data transfer device and a data transfer method for transferring a plurality of bits of transfer data through a transmission line, and a frame memory in the field of an image display device such as a matrix type liquid crystal display device using the data transfer device. Without using or performing complex compression / decompression processing, the number of data signal processing times can be reduced and the number of data transfer times can be reduced, reducing the power consumption required for data transfer and extending the operating time of the device. .

It is a block diagram which shows the principal part structural example of the liquid crystal display device which is one Embodiment of this invention. FIG. 2 is an equivalent circuit diagram illustrating a pixel configuration example in the image display apparatus of FIG. 1. (A) is a block diagram illustrating a configuration example of the data signal transmission unit of FIG. 1, and (b) is a block diagram illustrating a configuration example of the data signal reception unit of FIG. It is a figure for demonstrating operation | movement of the image display apparatus of FIG. 1, Comprising: It is a figure which shows the output result of the pixel data transferred and a pixel data separation part. FIG. 5 is a diagram illustrating data stored in a buffer memory for higher-order partial data in a data signal transmission unit in the transfer data example of FIG. 4. FIG. 5 is a diagram illustrating data stored in a buffer memory for lower partial data in a data signal transmission unit in the transfer data example of FIG. 4. FIG. 5 is a diagram illustrating an example of data received by a data signal receiving unit in the transfer data example of FIG. 4. FIG. 5 is a diagram showing upper part data generated by a data signal receiving unit in the transfer data example of FIG. 4. FIG. 5 is a diagram illustrating lower part data generated by a data signal receiving unit in the transfer data example of FIG. 4. It is a block diagram which shows the example of a principal part structure of the conventional image display apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 2 Pixel array 3 Data signal line drive circuit 3a Data signal receiving part 3b Data signal line drive part 4 Scan signal line drive circuit 5 Timing controller 5a Data signal transmission part 5b Timing control part 31, 51 Transfer control part 33, 34 Decoder 35, 36, 55, 56 Buffer memory 52 Pixel data separation unit 53, 54 Encoder 57 Transfer data synthesis unit

Claims (12)

In a data transfer device that transfers multi-bit transfer data from a transmission unit to a reception unit via a transmission line,
The transmitter is
Data separating means for separating each partial data of at least upper bits and lower bits for each transfer data;
Encoding means for converting the continuous data portion into a partial data value and the continuous number when the same transfer data is continuous with respect to the upper partial data of each continuous transfer data;
When the transmission data is sent to the transmission line by combining the information on each partial data, and the transmission of the higher-order partial data is completed, the other partial data for which data transmission has not been completed is replaced with the other partial data. A data transfer apparatus comprising: a transmission line in which partial data is normally used; and a data combining means for sending out the transmission transfer data by simultaneously using the transmission line of the upper partial data.   2. The data separation unit according to claim 1, wherein the data separation unit separates the transfer data into two of the upper part data and the lower part data, or three of the upper part data, the middle part data, and the lower part data. Data transfer device.   3. The data transfer apparatus according to claim 2, wherein the data separation means has the same number of bits for the separated partial data. The encoding means includes
An internal memory for storing the partial data value; and an internal counter for storing the continuous number; comparing the partial data value received from the data separation means with the partial data value stored in the internal memory; If the comparison results are different, the partial data value stored in the internal memory and the counter value of the internal counter are output as a set, and the received partial data value is stored in the internal memory, and the comparison result is the same. 2. The data transfer apparatus according to claim 1, wherein an addition process for adding "1" to the counter value of the internal counter is performed. The data synthesizing means includes
When the transfer data is sent by a normally used transmission line, when the transfer data is a continuous number with the partial data value, and when the partial data for which data transmission has not been completed is normally used; 2. The data transfer apparatus according to claim 1, wherein the additional transfer information indicating whether the data is transmitted simultaneously with the transmission line of the partial data for which the data transmission is completed is generated and transmitted together with the transmission transfer data. . The receiver is
The received data that has received the transmission transfer data is separated into a plurality of partial data, and when the reception of the higher-order partial data is completed, the other partial data that has not yet been received is received by the other partial data. When receiving the transmission line of the normally used transmission line and the transmission line of the higher-order partial data at the same time, and the partial data value and the continuous number are included for the partial data of the continuous transfer data 6. The data transfer apparatus according to claim 1, further comprising: a decoding unit that generates the same upper part data by the number of the continuous parts and combines the upper part data. The decoding means includes
According to the transfer additional information, the transfer data is transmitted by a transmission line that is normally used, or the partial transmission data that has not been transmitted is normally used and the data transmission is completed. 7. The data transfer apparatus according to claim 6, wherein the partial data is separated by discriminating whether the partial data is transmitted using the partial data transmission line at the same time.   8. The decoding unit according to claim 6 or 7, wherein the decoding means determines whether the transfer data is the partial data value and its continuous number based on the transfer additional information, and generates the same partial data by the continuous number. Data transfer device.   The data transfer device according to claim 1, wherein each partial data of the transfer data is represented by a color code or a gray code.   An image display device comprising the data transfer device according to claim 1, wherein each bit of transfer data corresponding to each pixel data is transferred from the transmission unit to the reception unit via the transmission line. . A pixel unit including a switching element arranged near each intersection of a plurality of scanning signal lines and a plurality of data signal lines, and a pixel electrode connected to the switching element, and a data signal on the receiving unit side for driving the data signal line A line driving circuit, a scanning signal line driving circuit for driving the scanning signal line, and a control board having a timing controller on the transmitting unit side for transmitting transfer data to the data signal line driving circuit via the transmission line;
The image display device according to claim 10, further comprising: a counter substrate disposed opposite to the control substrate and sandwiching liquid crystal as a display medium between the control substrate and the control substrate. A data transfer method for transferring multi-bit transfer data from a transmission unit side to a reception unit side via a transmission line,
On the transmission side, when each transfer data is separated into at least upper bit and lower bit partial data, and the same partial data is continuous with respect to the upper partial data of each successive transfer data, When the continuous data portion is converted into a partial data value and the number of continuous data, the information on each partial data is combined, the transmission transfer data is transmitted to the transmission line, and the data transmission of the upper partial data is completed The other part of the data that has not yet been transmitted is transmitted to the receiving unit using the transmission line in which the other partial data is normally used and the transmission line of the upper part data at the same time. Send data,
On the receiving unit side, the received data that has received the transmission transfer data is separated into a plurality of partial data, and when the reception of the higher-order partial data is completed, other partial data that has not yet been received, The other partial data is received by using the transmission line in which the other partial data is normally used and the transmission line of the higher-order partial data at the same time. Is included, the same partial data is generated by the continuous number and the partial data of the transfer data is combined.

Images