JP2006033923A - DC-DC converter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC-DC converter device capable of performing a wide range of power control with high efficiency and low noise while suppressing an excessive increase in a peak value of a current flowing through a switching element even when an input DC power supply voltage range is wide. provide.
A VF table 13 determines a switching frequency corresponding to the voltage of each DC power supply so that the switching frequency increases as the voltage of the DC power supply 1 increases. The switching frequency specifying unit 16 specifies a switching frequency corresponding to the voltage of the DC power supply 1 detected with reference to the VF table 13. The adjustment unit 15 adjusts the phase shift amount with respect to the switching timing of the IGBTs 3a and 3b which are the pair of switching timings of the IGBTs 3d and 3c so that the current flowing through the inductance 7 becomes discontinuous. The signal control unit 17 controls activation of the gate signal based on the switching frequency and the phase shift amount.
[Selection] Figure 1

Description

  The present invention relates to a DC-DC converter device, and more particularly, to a DC-DC converter device configured by connecting a full bridge inverter to a primary side of a transformer and connecting a rectifier circuit to a secondary side of the transformer.

  In recent years, in order to suppress electromagnetic induction noise generated from electronic equipment, research on noise reduction using soft switching technology that switches a switching element to zero voltage switching (ZVS) or zero current switching (ZCS) has been performed. Also in the DC-DC converter, the characteristic is improved by applying a soft switching technique. Moreover, not only the noise can be reduced by soft switching, but also the switching loss of the switching element can be greatly reduced, and the conversion efficiency can be improved.

  As an example of a circuit system of a DC-DC converter to which soft switching is applied, there is a phase shift PMW (Pulse Width Modulator) control system. FIG. 8 shows a conventional example of a phase shift PMW control DC-DC converter to which soft switching is applied. Such a conventional example is disclosed in Patent Document 1, for example.

  Referring to FIG. 8, the conventional DC-DC converter includes a high-frequency transformer 2, a DC power source 1 and a full bridge inverter 29 on the primary side, a reactor 7, a rectifier circuit 30, and an output capacitor 8 on the secondary side. , And a load resistance RL.

  The full-bridge inverter 29 receives the DC power supply 1 and converts it into an AC output by a phase shift control method, and includes IGBTs (Insulated Gate Bipolar Transistors) 3a, 3b, 3c, 3d, and reverse conducting diodes. 4a, 4b, 4c, 4d and snubber capacitors 5a, 5b, 5c, 5d.

  IGBT 3a and IGBT 3b constitute a reference phase (leading phase) leg. The IGBT 3c and the IGBT 3d constitute a control phase (delayed phase) leg. The reverse conducting diodes 4a, 4b, 4c, 4d are connected in parallel to the IBGTs 3a, 3b, 3c, 3d. Snubber capacitors 5a, 5b, 5c, 5d are connected in parallel to IGBTs 3a, 3b, 3c, 3d.

  The high frequency transformer 2 receives the AC output of the full bridge inverter 29.

  The reactor 7 is connected in series to the secondary side of the high-frequency transformer 7.

  The rectifier circuit 30 includes rectifier diodes 6a, 6b, 6c, and 6d, is connected to the secondary side of the high-frequency transformer 7, and rectifies alternating current into direct current.

  Reactor 7 is connected to rectifier circuit 30, and output capacitor 8 is connected to reactor 7. Reactor 7 and output capacitor 8 constitute a filter circuit, and apply a DC voltage to load resistor 8.

  FIG. 9 is a diagram for explaining the operation of a conventional DC-DC converter. Referring to the figure, Ts indicates a switching period and fs indicates a switching frequency.

  The IGBTs 3a, 3b, 3c, and 3d are controlled to be switched on / off according to a fixed switching period Ts (= 1 / fs). The times when the IGBTs 3a, 3b, 3c, and 3d are turned on are the same and are assumed to be Son.

  The IGBT 3a and IGBT 3b constituting the reference phase leg are complementarily turned on in a time having a width of about 180 °. Similarly, the IGBT 3c and IGBT 3d constituting the control phase leg are turned on complementarily in a time having a width of approximately 180 °.

  A fixed dead time td is provided when the IGBT 3a and the IGBT 3b are switched on. Similarly, a fixed dead time td is provided when the IGBT 3c and IGBT 3d are switched on.

  The IGBT 3a constituting the reference phase leg and the IGBT 3d constituting the control phase leg constitute a pair. The time when the IGBT 3a and the IGBT 3d constituting the pair are simultaneously turned on is called an overlap time, and is represented by ton. Similarly, the IGBT 3b constituting the reference phase leg and the IGBT 3c constituting the control phase leg constitute a pair. The time when the IGBT 3b and the IGBT 3c constituting the pair are simultaneously turned on is called an overlap time, and is represented by ton.

  The current flowing through the reactor 7 (hereinafter referred to as the reactor current) changes continuously as shown in FIG. Thus, a mode in which the reactor current continuously changes is called a continuous mode.

  The timing at which the IGBT 3d is turned on is controlled in a phase that is slower by θ than the timing at which the IGBT 3a is turned on. Similarly, the timing at which the IGBT 3c is turned on is controlled by a phase that is slower by θ than the timing at which the IGBT 3b is turned on. θ is referred to as a phase shift amount.

Another example of the phase shift circuit is disclosed in Patent Document 2.
JP 2002-238257 A JP 2001-103755 A

  However, the phase shift control type DC-DC converter described in Patent Document 1 operates in a continuous current mode in which the reactor current is continuous, and thus has the following problems.

  First, there is a problem that recovery loss and electromagnetic induction noise of a rectifier diode connected to the secondary side of the high-frequency transformer 2 occur.

  Second, when the input DC power supply voltage range, that is, the output voltage range of the DC power supply 1, is wide, the rectifier diodes 6a, 6b, 6c, 6d connected to the secondary side of the high-frequency transformer 2 are selected to have a high withstand voltage. There is a problem that the efficiency decreases as the forward voltage increases.

  In order to avoid such a problem, it is conceivable to operate in a current discontinuous mode in which the reactor current is discontinuous.

  However, even when operated in the current discontinuous mode, the switching frequency of the switching elements IGBT 3a, 3b, 3c, and 3d is fixed. Therefore, when the input DC power supply voltage range is wide, the reactor current peaks when the input voltage is high. The value is quite high. This is because the slope of the reactor current is proportional to the input voltage.

  Phase shift amount during phase shift PMW control so that the current flowing through switching elements IGBT3a, 3b, 3c, 3d does not exceed the current rating of switching elements IGBT3a, 3b, 3c, 3d due to the high peak value of the reactor current Although it is necessary to limit θ (conduction period), there is a problem that if the phase shift amount θ is limited, it is difficult to control power over a wide range, and efficiency is lowered due to an increase in current peak value. This problem becomes more pronounced when operated in the current discontinuous mode than when operated in the current continuous mode.

  Therefore, an object of the present invention is to perform a wide range of power control with high efficiency and low noise while suppressing an excessive increase in the peak value of the current flowing through the switching element even when the input DC power supply voltage range is wide. It is to provide a DC-DC converter device that enables the above.

  In order to solve the above problems, a DC-DC converter device according to an aspect of the present invention includes a DC power supply, a phase shift control type full-bridge inverter that inputs a DC power supply and converts the DC power into an AC output, and a full-bridge inverter. A transformer that receives AC output at the primary side, a rectifier circuit that rectifies the secondary output of the transformer to DC and outputs a DC voltage to the load, and an inductance connected in series to the primary or secondary side of the transformer And a control means for controlling the full-bridge inverter, the full-bridge inverter comprising two semiconductor switching elements constituting a reference phase leg, two semiconductor switching elements constituting a control phase leg, and a reference phase leg And a capacitor connected in parallel to each of the semiconductor switching elements constituting the control circuit, wherein the control means detects the magnitude of the voltage of the DC power supply. With reference to the input voltage detection means, a table defining the switching frequency of the semiconductor switching element corresponding to the magnitude of the voltage of each DC power supply, so that the switching frequency becomes higher as the voltage of the DC power supply is larger, Switching frequency specifying means for specifying the switching frequency of the semiconductor switching element corresponding to the detected voltage level of the DC power supply, and switching of the semiconductor switching element constituting the control phase leg so that the current flowing through the inductance is discontinuous And adjusting means for adjusting the phase shift amount with respect to the switching timing of the paired semiconductor element switching elements constituting the reference phase leg of the timing, and applying to the gate of the semiconductor switching element based on the switching frequency and the phase shift amount Active gate drive signal And a signal control means for controlling the reduction.

  Preferably, the control means further includes a current detection means for detecting a magnitude of the current flowing through the inductance, and a switching frequency specified by the switching frequency specifying means when the detected current magnitude exceeds a predetermined reference value. A switching frequency increasing means for increasing the switching frequency, and the signal control means controls activation of a gate drive signal applied to the gate of the semiconductor switching element based on the increased switching frequency and the adjusted phase shift amount. .

  Preferably, the transformer is a leakage transformer, and the leakage inductance of the leakage transformer is used instead of the inductance connected in series to the primary side or the secondary side of the transformer.

  Preferably, the semiconductor switching element is a field effect transistor, and a capacitor connected in parallel to each semiconductor switching element constituting the reference phase leg is substituted with the parasitic capacitance of the field effect transistor.

  Preferably, the control means further includes an output voltage detection means for detecting the magnitude of the output voltage, and the adjustment means has a discontinuous current flowing through the inductance so that the magnitude of the output voltage becomes a constant value. The signal control means adjusts the specified switching frequency and / or phase shift amount within the range, and the signal control means activates the gate drive signal applied to the gate of the semiconductor switching element based on the adjusted switching frequency and phase shift amount. Control.

  Preferably, the control means further includes a current detection means for detecting the magnitude of the input current output from the DC power supply, and the adjustment means is the magnitude of the detected input current and the voltage detected by the input voltage detection means. The input power is calculated on the basis of this, and the switching frequency and / or the phase shift amount is adjusted in a range where the current flowing through the inductance is discontinuous so that the input power becomes maximum. The activation of the gate drive signal applied to the gate of the semiconductor switching element is controlled based on the switching frequency and the phase shift amount.

  Preferably, the table includes a critical mode which is a boundary state between a continuous mode in which the current flowing through the inductance continuously changes and a discontinuous mode in which the current flowing through the inductance changes discontinuously at each voltage of the DC power supply. Therefore, the switching frequency corresponding to the magnitude of the voltage of each DC power supply is determined so that the peak value of the current flowing through the inductance becomes substantially the same even if the voltage of the DC power supply is changed.

  According to the DC-DC converter device of the present invention, even when the input DC power supply voltage range is wide, a wide range of power with high efficiency and low noise is suppressed while suppressing an excessive increase in the peak value of the current flowing through the switching element. Control can be performed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
(Constitution)
FIG. 1 is a diagram illustrating a configuration of a DC-DC converter according to the first embodiment. Referring to the figure, this DC-DC converter includes a high-frequency transformer 2, a DC power supply 1 and a full bridge inverter 20 on the primary side, a reactor 7 on the secondary side, a rectifier circuit 30, an output capacitor 8, And a load resistance RL.

  The full bridge inverter 20 receives a DC power supply 1 and converts it into an AC output by a phase shift control method, and includes IGBTs (Insulated Gate Bipolar Transistors) 3a, 3b, 3c, 3d, and reverse conducting diodes. 4a, 4b, 4c, 4d and snubber capacitors 5a, 5b.

  IGBT 3a and IGBT 3b constitute a reference phase (leading phase) leg. The IGBT 3c and the IGBT 3d constitute a control phase (delayed phase) leg. The reverse conducting diodes 4a, 4b, 4c, 4d are connected in parallel to the IBGTs 3a, 3b, 3c, 3d. Snubber capacitors 5a and 5b are connected in parallel to IGBTs 3a and 3b.

  The high frequency transformer 2 receives the AC output of the full bridge inverter 20.

  The reactor 7 is connected in series to the secondary side of the high-frequency transformer 7.

  The rectifier circuit 30 includes rectifier diodes 6a, 6b, 6c, and 6d, is connected to the reactor 7, rectifies AC to DC, and outputs a DC voltage to the load resistor RL.

  The output capacitor 8 is connected to the rectifier circuit 30.

  FIG. 2 is a diagram for explaining the operation of the DC-DC converter according to the first embodiment. Referring to the figure, Ts indicates a switching period and fs indicates a switching frequency.

  The IGBTs 3a, 3b, 3c, and 3d are controlled to be turned on / off according to a variable switching cycle Ts (= 1 / fs). The times when the IGBTs 3a, 3b, 3c, and 3d are turned on are the same and are assumed to be Son.

  The IGBT 3a and IGBT 3b constituting the reference phase leg are complementarily turned on in a time having a width of about 180 °. Similarly, the IGBT 3c and IGBT 3d constituting the control phase leg are turned on complementarily in a time having a width of approximately 180 °.

  A fixed dead time td is provided when the IGBT 3a and the IGBT 3b are switched on. Similarly, a fixed dead time td is provided when the IGBT 3c and IGBT 3d are switched on.

  Son and td satisfy the following relational expression (1).

Son + td = Ts / 2
= 1 / (2 × fs) (1)
The IGBT 3a constituting the reference phase leg and the IGBT 3d constituting the control phase leg constitute a pair. The time when the IGBT 3a and the IGBT 3d constituting the pair are simultaneously turned on is called an overlap time, and is represented by ton. Similarly, the IGBT 3b constituting the reference phase leg and the IGBT 3c constituting the control phase leg constitute a pair. The time when the IGBT 3b and the IGBT 3c constituting the pair are simultaneously turned on is called an overlap time, and is represented by ton. The overlap time ton is expressed by the following equation (2).

ton = D × (Ts / 2)
= D / (2 × fs) (2)
Here, D is called a duty.

  When the duty D exceeds a predetermined value α (about 0.5 in FIG. 2), the reactor current continuously changes as shown in FIG. 9, and when the duty D is less than the predetermined value α, 2, the discontinuous mode in which the reactor current changes discontinuously. Further, when the duty D is a predetermined value α, a critical mode that is a boundary state between the continuous mode and the discontinuous mode is set.

  During the overlap time ton when the IGBT 3a and the IGBT 3d are simultaneously turned on and the overlap time ton when the IGBT 3b and the IGBT 3c are simultaneously turned on, the magnitude of the reactor current increases linearly. On the other hand, during the period other than the overlap time ton, the magnitude of the reactor current decreases linearly. The longer the overlap time ton, the greater the peak value of the reactor current.

  Further, when the voltage of the DC power source 1, that is, the input voltage Vin increases, the gradient Kv of the change in the reactor current shown in FIG. 2 increases.

  The peak value I of the reactor current is expressed by the following formula (3).

I = Kv × ton
= Kv × D × (Ts / 2)
= Kv × D / (2 × fs) (3)
Moreover, since the electric energy of the full bridge inverter 20 is proportional to the reactor current (because the output voltage of the DC-DC converter is assumed to be a constant value), the electric energy P per unit time of the full bridge inverter 20 is This is a constant multiple of the result of dividing the area of two triangles of the two reactor current waveforms by the switching period Ts, and is expressed by the following equation (4).

P = a × (Kv × ton × 2 × ton) / Ts
= A x (2 x Kv x ton ² ) / Ts
= A x (Kv x D ² x Ts) / 2
= A × (Kv × D ² ) / (2 × fs) (4)
Here, a is a constant.

  As apparent from the equation (4), the larger the duty D, the larger the electric energy P per unit time, and the higher the switching frequency fs, the smaller the electric energy P per unit time and the larger the input voltage Vin. As Kv increases, the amount of power P per unit time increases.

  The timing at which the IGBT 3d is turned on is controlled with a phase that is later than the timing at which the IGBT 3a is turned on by a phase shift amount θ. Similarly, the timing at which the IGBT 3c is turned on is controlled by a phase that is delayed by the phase shift amount θ with respect to the timing at which the IGBT 3b is turned on.

  The phase shift amount θ is expressed by the following equation (5).

θ = Son−ton = (Ts / 2) −td−D × (Ts / 2)
= (1-D) * (Ts / 2) -td
= (1-D) / (2 * fs) -td (5)
The IGBTs 3a and 3b constituting the reference phase leg which is the leading phase are zero-voltage switched (ZVS) by the snubber capacitors 5a and 5b.

  On the other hand, the IGBTs 3c and 3d constituting the control phase leg are subjected to zero current switching (ZCS). This is because the waveform of the reactor current shown in FIG. 2 is almost the same as the current flowing in the primary side of the high-frequency transformer 2, that is, the current flowing in the IGBTs 3c and 3d. Thus, since the IGBTs 3c and 3d are zero-current switched (ZCS), no parallel snubber capacitor is provided for the IGBTs 3c and 3d.

  As described above, the switching elements IGBT3a, 3b, 3c, and 3d are all soft-switched to achieve low noise and low switching loss.

  In addition, as for the secondary side rectifier diodes 6a, 6b, 6c, and 6d, the reactor current gradually decreases to zero as shown in FIG. Then, after the reactor current becomes zero, a reverse voltage is applied to the diode and the diode is turned off at zero current. Therefore, the occurrence of recovery loss can be greatly suppressed, and the diode voltage surge during the recovery of the diode, and its Ringing is reduced and switching noise (electromagnetic induction noise and conduction noise) can be significantly suppressed.

  Referring to FIG. 1 again, the DC-DC converter further includes a control circuit 12. The control circuit 12 includes an input voltage detection unit 9, an input current detection unit 11, an output voltage detection unit 10, a V-F table 13, a switching frequency identification unit 16, a switching frequency increase unit 14, and an adjustment unit 15. And a signal control unit 17.

  The input voltage detector 9 detects the input voltage Vin of the DC power source 1 and outputs a voltage detection signal representing the value of the input voltage Vin to the switching frequency specifying unit 16.

  The input current detection unit 11 detects the input current Iin output from the DC power supply 1 and outputs a current detection signal representing the value of the input current Iin to the switching frequency increase unit 14.

  The output voltage detection unit 10 detects the output voltage Vout applied to the load resistor RL, and outputs a voltage detection signal representing the value of the output voltage Vout to the adjustment unit 15.

  The VF table 13 holds a switching lower limit frequency fs0 corresponding to the input voltage Vin.

  FIG. 3 is a diagram showing the relationship between the input voltage Vin stored in the VF table 13 and the switching lower limit frequency fs0. Referring to FIG. 3, switching lower limit frequency fs0 increases in proportion to input voltage Vin between lower limit value f_min and upper limit value f_max. Here, the lower limit value f_min is provided so that the switching frequency fs set based on the switching lower limit frequency fs0 does not exceed the switching speed of the switching elements IGBT3a, 3b, 3c, 3d. Because. The reason why the upper limit value f_max is provided is to prevent the core of the high-frequency transformer 2 from being saturated and to prevent the set switching frequency fs from entering the audible band.

  An example of a method for setting the switching lower limit frequency fs0 for each input voltage Vin in the proportional portion of FIG. 3 will be described. When the critical mode is set for each input voltage Vin, that is, when the duty D becomes a predetermined value α, the peak value I of the reactor current shown in the equation (3) is the same even if the input voltage Vin is changed. The switching frequency for each input voltage Vin is specified, and this is set as the switching lower limit frequency fs0 for each input voltage Vin.

  As a result, even if the switching lower limit frequency fs0 is changed in correspondence with each input voltage Vin, if the duty D is the same, substantially the same power can be supplied, so that it is easy to maintain control continuity.

  However, since the dead time td is constant even if the switching lower limit frequency fs0 changes, strictly speaking, the duty D needs to be finely adjusted.

  Referring again to FIG. 1, switching frequency specifying unit 16 receives a voltage detection signal representing input voltage Vin from input voltage detection unit 9, refers to VF table 13, and corresponds to input voltage Vin. The switching lower limit frequency fs0 is specified and output to the switching frequency increasing unit 14.

  Switching frequency increasing unit 14 receives switching lower limit frequency fs0 from switching standard frequency specifying unit 16, and receives a current detection signal representing the value of input current Iin from current detecting unit 11. When the peak value of the input current Iin does not exceed a predetermined level, the switching frequency increasing unit 14 outputs the value of the switching lower limit frequency fs0 as it is as the switching frequency fs1. When the peak value of the input current Iin exceeds a predetermined level, that is, when the value of the reactor current proportional to the value of the input current Iin exceeds a certain level, the switching frequency increasing unit 14 outputs the reactor current to reduce the reactor current. The value of the switching frequency fs1 is gradually increased from the value of the switching lower limit frequency fs0 to a predetermined upper limit value. Here, the reason for gradually increasing is to prevent the switching frequency fs1 from being excessively increased. The reason why the predetermined upper limit value is provided is that the switching speed of the switching elements IGBTs 3a, 3b, 3c, and 3d has a physical limit.

  As described above, the switching lower limit frequency fs is increased with respect to the increase of the input voltage Vin by the VF table 13 and the switching frequency specifying unit 16, and as a result, the switching frequency fs of the switching elements IGBT 3a, 3b, 3c, 3d. The reason why the switching frequency fs is increased will be described below.

  First, a case where the switching frequency fs is fixed will be described.

When the input voltage Vin increases, the peak value I of the reactor current increases as shown in Expression (3). If the power P per unit time of the full bridge inverter 20 expressed by the equation (4) is to be kept constant, it is necessary to reduce the duty D so that Kv × D ² becomes constant. Thereby, the electric power P per unit time is kept constant, but Kv × D is not kept constant, and the peak value I of the reactor current shown in Expression (3) does not decrease so much. Therefore, when the peak value of the reactor current cannot be allowed to increase due to the ratings of the switching elements IGBT 3a, 3b, 3c, 3d, the duty D must be further reduced, and when the duty D becomes extremely small, There arises a problem that desired power cannot be supplied.

  In addition, even when a certain increase in the peak value of the reactor current can be tolerated, the loss of circuit conduction is proportional to the square of the current value, which causes a problem of reduced efficiency.

  On the other hand, in the present embodiment, in order to keep constant the power P per unit time of the full bridge inverter 20 expressed by the equation (4), the switching frequency fs is increased so that Kv / fs is constant. To do. Thereby, the electric power P per unit time is kept constant, and the peak value I of the reactor current shown in Expression (3) is also kept constant.

  However, if the switching frequency fs is increased, the proportion of the dead time td increases and the power decreases. Therefore, in order to obtain the same power, it is necessary to slightly increase the peak value of the reactor current. However, in the DC-DC converter device of the present embodiment, since the switching element is soft-switched, even if the switching frequency fs is increased, the increase in switching loss is limited and does not cause a significant reduction in efficiency. .

  Referring to FIG. 1 again, adjustment unit 15 receives a voltage detection signal representing the value of output voltage Vout from output voltage detection unit 10, and receives a voltage detection signal representing the value of input voltage Vin from input voltage detection unit 9. Receiving the current detection signal representing the value of the input current Iin from the input current detecting unit 11, receiving the switching frequency fs 1 from the switching frequency increasing unit 14, and adjusting the switching frequency fs and the phase shift amount θ based on these signals. .

  The adjustment unit 15 adjusts and outputs the switching frequency fs and / or the phase shift amount θ in a range where the duty D is a value representing the discontinuous mode (that is, less than the predetermined value α) during normal times.

  When the output voltage Vout is controlled to be a constant value (constant output voltage control), the adjustment unit 15 has a duty D representing a discontinuous mode so that the magnitude of the output voltage Vout is a constant value. In such a range, the switching frequency fs and / or the phase shift amount θ is adjusted and output. The initial value of the switching frequency fs is, for example, the switching frequency fs1 received from the switching frequency increasing unit 14, and the initial value of the phase shift amount θ is, for example, D = 0.45 and fs = fs1, Let θ be a fixed value. This control may be performed, for example, by normal proportional (P) control, or by proportional integral (PI) control.

  The adjustment unit 15 calculates the input power from the input voltage Vin and the input current Iin when the maximum power follow-up control is necessary when the DC power source 1 is a solar battery, so that the input power is maximized. The switching frequency fs and / or the phase shift amount θ are adjusted and output in a range where the duty D is a value representing the discontinuous mode. The initial value of the switching frequency fs is, for example, the switching frequency fs1 received from the switching frequency increasing unit 14, and the initial value of the phase shift amount θ is, for example, D = 0.45 and fs = fs1, Let θ be a fixed value. This control may be performed, for example, by maximum power tracking (MPPT) control.

  The signal control unit 17 receives the switching frequency fs and the phase shift amount θ from the adjustment unit 15 and controls the switching of the IGBTs 3a, 3b, 3c, and 3d based on the switching frequency fs and the gate drive signals Ga, Gb, Gc, and Gd. Control the timing of activation. When the gate drive signals Ga, Gb, Gc, Gd are activated to “H”, the IGBTs 3a, 3b, 3c, 3d are turned on, and the gate drive signals Ga, Gb, Gc, Gd are deactivated to “L”. Then, the IGBTs 3a, 3b, 3c and 3d are turned off.

  As described above, the DC-DC converter device according to the present embodiment operates in the current discontinuous mode in which the reactor current changes discontinuously, and the switching frequency according to the magnitude of the input DC current power supply voltage. By controlling the voltage variably, it is possible to perform a wide range of power control with high efficiency and low noise while suppressing an excessive increase in the peak value of the current flowing through the switching element even when the input DC power supply voltage range is wide. .

[Second Embodiment]
(Constitution)
FIG. 4 is a diagram illustrating a configuration of a DC-DC converter according to the second embodiment. With reference to the figure, the DC-DC converter is different from the DC-DC converter according to the first embodiment shown in FIG. 1 as follows.

  In the first embodiment, the reactor 7 is connected to the secondary side of the high-frequency transformer 2, whereas in the second embodiment, the reactor 7 is connected to the primary side of the high-frequency transformer 2.

(Operation)
The operation of the DC-DC converter according to the second embodiment is the same as the operation of the DC-DC converter of the first embodiment. Therefore, description of the operation will not be repeated.

[Third Embodiment]
(Constitution)
FIG. 5 is a diagram illustrating a configuration of a DC-DC converter according to the third embodiment. With reference to the figure, the DC-DC converter is different from the DC-DC converter according to the first embodiment shown in FIG. 1 as follows.

  In the first embodiment, the reactor 7 is connected to the secondary side of the high-frequency transformer 2, whereas in the third embodiment, the reactor 7 is connected to the primary side of the high-frequency transformer 2.

  In the first embodiment, the rectifier circuit 30 is composed of the rectifier diodes 6a, 6b, 6c, and 6d, whereas in the third embodiment, the rectifier circuit 31 includes the full waveform voltage doubler. The rectifier circuit is composed of rectifier diodes 6a and 6b and voltage doubler capacitors 16a and 16b. Such a rectifier circuit 31 performs voltage doubler rectification.

(Operation)
The operation of the DC-DC converter according to the third embodiment is the same as the operation of the DC-DC converter of the first embodiment except that voltage doubler rectification is performed. Therefore, description of the operation will not be repeated.

[Fourth Embodiment]
(Constitution)
FIG. 6 is a diagram illustrating a configuration of a DC-DC converter according to the fourth embodiment. With reference to the figure, the DC-DC converter is different from the DC-DC converter according to the first embodiment shown in FIG. 1 as follows.

  In the first embodiment, the reactor 7 is connected to the secondary side of the high-frequency transformer 2, whereas in the fourth embodiment, the reactor 7 is connected to the primary side of the high-frequency transformer 2.

  In the first embodiment, the rectifier circuit 30 is composed of the rectifier diodes 6a, 6b, 6c, and 6d, whereas in the fourth embodiment, the rectifier circuit 32 has a half-wave voltage doubler. The rectifier circuit is composed of rectifier diodes 6a and 6b and a voltage doubler capacitor 16a. Such a rectifier circuit 32 performs voltage doubler rectification.

(Operation)
The operation of the DC-DC converter according to the fourth embodiment is the same as the operation of the DC-DC converter of the first embodiment except that voltage doubler rectification is performed. Therefore, description of the operation will not be repeated.

[Fifth Embodiment]
(Constitution)
FIG. 7 is a diagram illustrating a configuration of a DC-DC converter according to the fifth embodiment. With reference to the figure, the DC-DC converter is different from the DC-DC converter according to the fourth embodiment shown in FIG. 6 as follows.

  The full bridge inverter 20 of the fourth embodiment includes IGBTs 3a, 3b, 3c, and 3d as semiconductor switching elements, whereas the full bridge inverter 21 of the fifth embodiment includes FETs as semiconductor switching elements. (Field Effect Transistor) 18a, 18b, 18c, 18d.

  Further, the full bridge inverter 20 of the fourth embodiment includes the snubber capacitors 5a and 5b, whereas the full bridge inverter 21 of the fifth embodiment does not include the snubber capacitors 5a and 5b. This is because the snubber capacitors 5a and 5b can be replaced by the parasitic capacitances of the FETs 18a and 18b in the full bridge inverter 21. Thus, in the fifth embodiment, the number of circuit components can be reduced as compared with the fourth embodiment.

  The DC-DC converter according to the fourth embodiment includes the high-frequency transformer 2, whereas the DC-DC converter according to the fifth embodiment includes the leakage transformer 18. The leakage transformer 18 is intentionally provided with a leakage inductance between the primary winding and the secondary winding.

  Further, the DC-DC converter of the fourth embodiment includes the reactor 7, whereas the DC-DC converter of the fifth embodiment does not include the reactor 7. This is because the reactor 7 can be replaced by the leakage inductance of the leakage transformer 18. Thus, in the fifth embodiment, the number of circuit components can be reduced as compared with the fourth embodiment.

(Operation)
The operation of the DC-DC converter according to the fifth embodiment is the same as the operation of the DC-DC converter of the fourth embodiment. Therefore, description of the operation will not be repeated.

(Modification)
The present invention is not limited to the above embodiment, and includes, for example, the following modifications.

(1) Switching lower limit frequency fs0
In the embodiment of the present invention, the switching lower limit frequency fs0 is increased in proportion to the input voltage Vin between the lower limit value f_min and the upper limit value f_max, but is not limited to increase in proportion. Absent. The switching lower limit frequency fs0 only needs to be monotonically increased with respect to the input voltage Vin between the lower limit value f_min and the upper limit value f_max.

(2) Increase in switching frequency In the embodiment of the present invention, when the peak value of the input current Iin exceeds a predetermined level, the switching frequency fs1 is increased from the value of the switching lower limit frequency fs0. However, the present invention is not limited to this. Alternatively, even when the peak value of the input current Iin is equal to or lower than a predetermined level, the switching frequency fs1 may be increased from the value of the switching lower limit frequency fs0. Further, which one of the above is used can be switched, and a condition for improving the conversion efficiency of the DC-DC converter device may be determined in advance, and may be switched to the one having the higher conversion efficiency in actual use.

  Of course, the value of the switching frequency fs1 may be left as the switching lower limit frequency fs regardless of the peak value of the input current Iin.

(3) Adjustment Unit The adjustment unit 15 adjusts the switching frequency fs and / or the phase shift amount θ in a range where the duty D is a value representing the discontinuous mode. It is also possible to add a condition such that the received switching frequency fs1 or higher.

(4) Control Circuit The control circuit 12 may be configured by a microcomputer or a DSP that holds a program and executes the held program.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a figure which shows the structure of the DC-DC converter which concerns on the 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the DC-DC converter which concerns on the 1st Embodiment of this invention. It is a figure which shows the relationship between the input voltage Vin stored in the VF table 13, and the switching lower limit frequency fs0. It is a figure which shows the structure of the DC-DC converter which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structure of the DC-DC converter which concerns on the 3rd Embodiment of this invention. It is a figure which shows the structure of the DC-DC converter which concerns on the 4th Embodiment of this invention. It is a figure which shows the structure of the DC-DC converter which concerns on the 5th Embodiment of this invention. It is a figure which shows the structure of the conventional DC-DC converter. It is a figure for demonstrating operation | movement of the conventional DC-DC converter.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 DC power supply, 2 High frequency transformer, 7 Reactor, 8 Output capacitor, 9 Input voltage detection part, 10 Output voltage detection part, 11 Input current detection part, 12 Control circuit, 13 VF table, 14 Switching frequency increase part, 15 Adjustment unit, 16 switching frequency specifying unit, 17 signal control unit, 18 leakage transformer, 20, 21, 29 full bridge inverter, 30, 31, 32 rectifier circuit, 3a, 3b, 3c, 3d IGBT, 4a, 4b, 4c, 4d reverse conducting diode, 5a, 5b snubber capacitor, 6a, 6b, 6c, 6d rectifier diode, 16a, 16b double voltage capacitor, 18a, 18b, 18c, 18d FET, RL load resistance.

Claims (7)

DC power supply,
A phase shift control type full-bridge inverter that inputs the DC power source and converts it into an AC output;
A transformer that receives the AC output of the full-bridge inverter on the primary side;
A rectifier circuit that rectifies the secondary output of the transformer to direct current and outputs a direct current voltage to a load;
An inductance connected in series to the primary or secondary side of the transformer;
Control means for controlling the full-bridge inverter,
The full bridge inverter is
Two semiconductor switching elements constituting a reference phase leg;
Two semiconductor switching elements constituting a control phase leg;
A capacitor connected in parallel to each semiconductor switching element constituting the reference phase leg,
The control means includes
Input voltage detecting means for detecting the magnitude of the voltage of the DC power supply;
A table that defines the switching frequency of the semiconductor switching element corresponding to the magnitude of the voltage of each DC power supply so that the switching frequency becomes higher as the voltage of the DC power supply is larger;
With reference to the table, switching frequency specifying means for specifying the switching frequency of the semiconductor switching element corresponding to the detected magnitude of the voltage of the DC power supply,
A phase shift amount of the switching timing of the semiconductor switching elements constituting the control phase leg with respect to the switching timing of the paired semiconductor element switching elements constituting the reference phase leg so that the current flowing through the inductance becomes discontinuous Adjusting means for adjusting
A DC-DC converter device comprising: signal control means for controlling activation of a gate drive signal applied to the gate of the semiconductor switching element based on the switching frequency and the phase shift amount. The control means further includes
Current detection means for detecting the magnitude of the current flowing through the inductance;
Switching frequency increasing means for increasing the switching frequency specified by the switching frequency specifying means when the magnitude of the detected current exceeds a predetermined reference value;
2. The DC according to claim 1, wherein the signal control unit controls activation of a gate drive signal to be applied to a gate of the semiconductor switching element based on the increased switching frequency and the adjusted phase shift amount. -DC converter device. The transformer is a leakage transformer,
The DC-DC converter device according to claim 1, wherein a leakage inductance of the leakage transformer is used instead of the inductance connected in series to the primary side or the secondary side of the transformer. The semiconductor switching element is a field effect transistor,
2. The DC-DC converter device according to claim 1, wherein a capacitor connected in parallel to each semiconductor switching element constituting the reference phase leg is substituted with a parasitic capacitance of the field effect transistor. The control means further includes
Output voltage detection means for detecting the magnitude of the output voltage,
The adjusting means adjusts the specified switching frequency and / or the phase shift amount in a range where the current flowing through the inductance is discontinuous so that the magnitude of the output voltage becomes a constant value,
2. The DC-DC according to claim 1, wherein the signal control unit controls activation of a gate drive signal applied to a gate of the semiconductor switching element based on the adjusted switching frequency and the phase shift amount. Converter device. The control means further includes
Current detection means for detecting the magnitude of the input current output from the DC power supply,
The adjustment means calculates input power based on the magnitude of the detected input current and the voltage detected by the input voltage detection means, and the current flowing through the inductance is such that the input power is maximized. Adjust the switching frequency and / or the phase shift amount in a discontinuous range,
2. The DC-DC according to claim 1, wherein the signal control unit controls activation of a gate drive signal applied to a gate of the semiconductor switching element based on the adjusted switching frequency and the phase shift amount. Converter device.   The table is a critical mode that is a boundary state between a continuous mode in which the current flowing through the inductance continuously changes and a discontinuous mode in which the current flowing through the inductance changes discontinuously at each voltage of the DC power supply. The switching frequency corresponding to the magnitude of the voltage of each DC power supply is determined so that the peak value of the current flowing through the inductance is substantially the same even when the voltage of the DC power supply is changed. The DC-DC converter apparatus according to claim 1.

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