JP2006033522A - Interpolator, variable gain amplifier using the interpolator and current generating method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interpolator capable of easily improving the operation characteristics of a variable gain amplifier by facilitating its adjustment. <P>SOLUTION: The interpolator is provided with a constant-current source 34, a plurality of transistors 33 each connected to the constant-current source 34, and a control voltage generating circuit 35 for applying a voltage for controlling the current amount to each of the transistors 33. The interpolator 22 shunts a constant-current formed by the constant current source 34, in correspondence with the difference in voltage for controlling the current amount, and applies the shunted current to each of the transistors 33. In the interpolator, the circuit 35 is provided with a circuit 32 for making the difference in the voltage for controlling current amount to be applied to each of the transistors 33 increase. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an interpolator, a variable gain amplifier using the interpolator, and a current generation method.

A variable gain amplifier (VGA) is a signal processing system that is not affected by the subsequent circuit when a signal with a large amplitude difference is input or the level of the input signal changes due to environmental changes. This is a circuit for managing the amplitude of an input signal so that it can be used in various devices such as communication devices, audio devices, and measuring devices. A configuration example of such a variable gain amplifier is disclosed in, for example, Patent Document 1 below.
US Pat. No. 5,077,541

FIG. 6 is a diagram showing a circuit configuration of the variable gain amplifier disclosed in Patent Document 1. In FIG. As shown in the figure, the variable gain amplifier includes first differential amplifiers 100-1 to 100-n, a second differential amplifier 104, and a ladder resistor 102. The signal extracted at each node of the ladder resistor 102 is input to one input terminal of each first differential amplifier 100, and the output of the second differential amplifier 104 is fed back to the other input terminal. Have been entered. The output of each first differential amplifier 100 is connected in parallel to the second differential amplifier 104. Constant currents I _{E1 to} I _En controlled by the control voltage Vagc flow through the first differential amplifiers 100, respectively. The gains of the first differential amplifiers 100 are controlled by controlling the magnitudes of the constant currents I _{E1 to} I _En . Here, the control voltage Vagc corresponds to, for example, the level of the input signal.

FIG. 7 is a diagram illustrating the relationship between the control voltage Vagc and the constant current amounts I _{E1 to} I _En flowing through the first differential amplifiers 100. In the figure, the sum of the constant current amounts I _{E1 to} I _En is constant, and to which first constant amplifier 100 a large amount of constant current is shunted out of the constant amount according to the control voltage Vagc. Is changing. Specifically, as the control voltage Vagc decreases, the most current flows in the order of the first differential amplifier 100-1, the first differential amplifier 100-2, ..., the first differential amplifier 100-n. The first differential amplifier 100 is alternated. At this time, each first differential amplifier 100 is supplied with a current indicating a Gaussian function type change that approaches a peak as the control voltage Vagc approaches a predetermined value and approaches zero as the control voltage Vagc approaches the predetermined value.

FIG. 8 is a diagram showing a configuration of an interpolator (inserter) for generating the current shown in FIG. As shown in the figure, in the interpolator, the bases of a plurality of npn transistors 106 are sequentially connected via resistors, and a constant current source 110 that supplies a current of a common magnitude is connected to each base. Has been. The collectors are connected to the first differential amplifier 100, respectively. Further, each emitter is connected to a constant current source 108, and in particular, the bases of the transistors at both ends are used as terminals for applying the control voltage Vagc and its inverted voltage. According to the interpolator shown in the figure, according to the voltage applied to the base of each transistor 106, the current I _gm drawn by the constant current source 108 is different from that of one or more transistors like a differential amplifier. 106 flows intensively.

That is, a large collector current flows for the transistor 106 to which the highest voltage is applied and a transistor 106 to which the equivalent voltage is applied (if any), and the other transistors 106 have a collector current. Only a small amount flows, or only a negligible collector current flows. When the control voltage Vagc takes a large value (positive value), the base voltage of the leftmost transistor 106-1 in FIG. 8 is increased, and is supplied from the constant current source as the control voltage Vagc approaches 0. The voltage drop due to the current flowing through the resistor becomes dominant, and therefore the base voltage of the transistor 106 in the central portion becomes the highest. When the control voltage Vagc takes a small value (negative value), the base voltage of the rightmost transistor 106-n in FIG. 8 becomes high. In this way, the transistor 106 through which most of the current _Igm drawn by the constant current source 108 flows is shifted in accordance with the control voltage Vagc in FIG.

  In the variable gain amplifier, input signals attenuated by different attenuation amounts are input to the first differential amplifiers 100, and one or more of the first differential amplifiers 100 selectively generate an amplified signal. Therefore, the signal can be amplified with various gains by setting the control voltage Vagc. Further, each first differential amplifier 100 does not operate alternatively, but the adjacent first differential amplifiers 100 always cooperate. That is, as indicated by hatching in FIG. 7, a considerable amount of constant current always flows in two to three first differential amplifiers 100 out of the first differential amplifiers 100-1 to 100-n. Two to three first differential amplifiers 100 are always operating in an overlapping manner. Therefore, the variable gain controller can smoothly change the gain according to the control voltage Vagc.

  In the above-described conventional variable gain amplifier, the constant current flowing through each first differential amplifier 100 is adjusted by adjusting various circuit constants of the interpolator, thereby improving various operating characteristics of the variable gain amplifier. However, the conventional configuration has few adjustment elements and cannot sufficiently improve the operation characteristics. For example, by changing the hatched portion in FIG. 7, it is possible to control the number of first differential amplifiers 100 through which current flows simultaneously, the magnitude of these currents, etc., thereby improving various operating characteristics. As expected, the conventional configuration could not make such an improvement easily.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an interpolator and a current generator that can easily adjust the constant current and thereby easily improve the operating characteristics of the variable gain amplifier. It is an object to provide a method and a variable gain amplifier using the method.

  In order to solve the above problems, an interpolator according to the present invention includes a constant current source, a plurality of transistors connected to the constant current source, and a control voltage for applying a voltage for controlling the amount of current to each of the transistors. An interpolator that splits a constant current formed by the constant current source in accordance with a difference in voltage for controlling the amount of current applied to each transistor, and flows the current to each transistor. The control voltage generation circuit includes a circuit that increases a difference between the current amount control voltages applied to the transistors.

  A variable gain amplifier according to the present invention includes the interpolator.

  Furthermore, in the current generation method according to the present invention, a voltage for controlling the amount of current is applied to each of a plurality of transistors connected to a common constant current source via an amplifier, and is applied to each of the transistors. In accordance with a difference in voltage for controlling the amount of current, the current is divided from the constant current formed by the constant current source, and flows to each transistor.

  According to the present invention, the constant current formed by the constant current source connected to the transistors is shunted according to the difference in voltage for controlling the amount of current applied to each transistor, and the current flowing through each transistor is split. Since the porator is equipped with a circuit that increases the difference in voltage for controlling the amount of current applied to each transistor, the number of transistors through which current flows simultaneously can be reduced, or the amount of current can be suppressed. can do.

  In one aspect of the present invention, the control voltage generation circuit includes a plurality of amplifiers connected to a portion to which a voltage for controlling the amount of current of each transistor is applied. By so doing, it is possible to increase the difference in voltage for suppressing the amount of current applied to each transistor with a simple configuration. In this case, the plurality of amplifiers or resistors may have a common gain.

  In one embodiment of the present invention, the control voltage generation circuit applies the highest current control voltage to one of the plurality of transistors that is selected in a predetermined order according to an increase in a given control voltage. . If it carries out like this, it can be set as an interpolator suitable for a variable gain amplifier.

  In one embodiment of the present invention, the control voltage generation circuit includes a plurality of resistors connected in series, and a plurality of second constant current sources connected to connection portions of the resistors. A given control voltage is applied to both ends of the plurality of resistors connected in series, and the voltage at each connection portion is amplified by each amplifier. In this way, the highest current amount control voltage can be applied to one selected in a predetermined order according to an increase in a given control voltage with a simple configuration.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram showing a circuit configuration of a variable gain amplifier according to an embodiment of the present invention. As shown in the figure, this variable gain amplifier is centered on the first differential amplifiers 10-1 to 10-n, the attenuators 12-2 to 12-n, the interpolator 22 and the second differential amplifier 16. It is configured. In the circuit shown in the figure, except for the wiring from the first differential amplifiers 10-1 to 10-n to the interpolator 22, it should be drawn with two lines originally, but is drawn with one line for simplicity. In other words, except for the wiring from the first differential amplifiers 10-1 to 10-n to the interpolator 22, two signals having a phase-inverted relationship with each other are allowed to flow.

The first differential amplifier 10-1 is directly input with a signal (configured from the input signal itself and its inverted signal) input from the input terminal 20 without going through the attenuators 12-2 to 12-n. The signal is amplified by a gain corresponding to a constant current I _E1 drawn from the interpolator 22.

  On the other hand, the input signals attenuated by the attenuators 12-2 to 12-n are respectively input to the first differential amplifiers 10-2 to 10-n, and the constant currents IE2 to IE2 drawn from the interpolator 22 are input. These signals are amplified with a gain according to IEn.

  FIG. 2 shows a circuit configuration of the first differential amplifier 10-n (n = 1, 2,...). As shown in the figure, the first differential amplifier 10-n includes npn transistors Tr1 to Tr4 and a current amplifier circuit 24. The current amplifying circuit 24 generates three constant currents corresponding to the current IEn drawn from the interpolator 22, and outputs them as a differential amplifier composed of a transistor Tr3 and a transistor Tr4, an emitter of the transistor Tr1, and an emitter of the Tr2 From, it comes to draw each.

  The base of the transistor Tr1 is connected to the non-inverting input terminal 23p, and a non-inverting signal is applied to the signal input from the input terminal 20 or the signal attenuated by the attenuator 12-n. Yes. The collector of the transistor Tr1 is connected to the power supply Vcc, and the emitter is connected to a constant current source in the current amplifier circuit 24. The signal input to the non-inverting input terminal 23p is amplified and is then converted into an npn type. The voltage is applied to the transistor Tr3. Similarly, the base of the transistor Tr2 is connected to the inverting input terminal 23m, and an inverted signal is applied to the signal input from the input terminal 20 or the signal attenuated by the attenuator 12-n. ing. The collector of the transistor Tr2 is connected to the power supply Vcc, and the emitter is connected to a constant current source (not connected to the emitter of the transistor Tr1) in the current amplifier circuit 24, and the inverting input terminal The signal input to 23m is amplified and applied to the npn transistor Tr4. The transistors Tr3 and Tr4 constitute a differential amplifier, and each emitter is connected to a constant current source in the current amplifying circuit 24 (separate from that connected to the emitters of the transistors Tr1 and Tr2). The collector of the transistor Tr3 is connected to the non-inverting input of the second differential amplifier 16 via the non-inverting terminal 25p. The collector of the transistor Tr4 is connected to the inverting input of the second differential amplifier 16 via the inverting terminal 25m. As shown in FIG. 1, a power source Vcc is connected to each input of the second differential amplifier 16 through a resistor, and the collector currents of the transistors Tr3 and Tr4 are converted into voltages. It is designed to be entered.

  Returning to FIG. 1, the attenuators 12-2 to 12-n are set so that the amount of attenuation increases in this order. The attenuators 12-2 to 12-n attenuate the signal input from the input terminal 20 and the attenuated signal. Are input to the corresponding first differential amplifiers 10-2 to 10-n. The attenuators 12-2 to 12-n are specifically configured as ladder resistors as shown in FIG. That is, the attenuators 12-n (n = 2, 3,...) Are provided between the input terminal 20 and the first differential amplifier 10-n, and n−1 ladder elements 26-1 to 26-1 are installed. 26- (n-1) is connected in series. For this reason, the attenuation amount of the attenuator 12-n is n-1 times the attenuation amount of the attenuator 12-2.

  The input signal itself is input from the non-inverting terminal 28p provided in the ladder element 26-1, and the inverted signal of the input signal is input from the inverting terminal 28m provided in the ladder element 26-1. The non-inverting terminal 30p provided in the ladder element 26- (n-1) is connected to the non-inverting terminal 23p of the first differential amplifier 10-n and provided in the ladder element 26- (n-1). The inverting terminal 30m is connected to the inverting input terminal 23m of the first differential amplifier 10-n. Ladder elements 26-1 to 26- (n-1) include a non-inverting signal resistor R, an inverting terminal 28m, and an inverting terminal 30m provided on a wiring connecting the non-inverting terminal 28p and the non-inverting terminal 30p, respectively. It is comprised from the inversion signal resistor R provided on the wiring to connect, and bridge resistance 2R which connects the edge part of each resistor R. FIG.

Returning to FIG. 1 again, the second differential amplifier 16 includes, for example, a known operational amplifier circuit, has an inverting input and a non-inverting input, and outputs an amplified signal from the output terminal 18. Circuit. The first differential amplifiers 10-1 to 10-n are connected in parallel to the inputs of the second differential amplifier 16, and their output signals are synthesized and input to the second differential amplifier 16. . The interpolator 22 pulls the constant currents I _{E1 to} I _En from the first differential amplifiers 10-1 to 10-n at a rate corresponding to the control voltage Vagc applied to the control terminal 14. . At this time, the sum of the constant currents I _{E1 to} I _En is fixed to _Igm .

  The interpolator 22 having the circuit configuration shown in FIG. 4 is used. The interpolator 22 shown in the figure includes n + 1 resistors connected in series and having a common resistance value, and a constant current source 31 that forms a constant current having a common magnitude is connected to each connection portion. Has been. Further, terminals 14 for applying the control voltage Vagc and its inverted voltage are provided at both ends of these resistor groups.

  Further, an amplifier 32 (input) having a common gain is further connected to each connection portion of the resistor group. These amplifiers 32 are mounted using, for example, a known operational amplifier. The outputs of the amplifiers 32 are connected to the bases of the transistors 33-1 to 33-n. The current amplification circuits 24 provided in the first differential amplifiers 10-1 to 10-n are connected to the collectors of the transistors 33-1 to 33-n, respectively. The emitter is connected to a constant current source 34.

The n + 1 resistors, the constant current source 31 and the amplifier 32 connected in series are circuits for applying a voltage for controlling the magnitude of the constant currents I _{E1 to} I _En to the base of each transistor 33. The control voltage generation circuit 35 will be called.

The circuit configuration of the interpolator 22 shown in FIG. 4 is similar to the interpolator shown in FIG. 8, and the amplifier 32 is connected to the bases of the transistors 33-1 to 33-n, which are connected in series. It is characteristic that each connection portion of the resistor R is connected to the bases of the transistors 33-1 to 33-n via the amplifier 32. The interpolator 22 shown in FIG. 4 also has a current I _gm drawn by the constant current source 34 according to the voltage applied to the base of each transistor 33, so that the current I _gm is one or more transistors 33. It is designed to flow intensively.

That is, for the transistor 33 to which the highest voltage is applied and the transistor 33 to which the equivalent voltage is applied (if any), the constant currents I _{E1 to} I _{En that} are collector currents flow largely. For the other transistors 33, only a small amount of collector current flows or only a negligible collector current flows. When the control voltage Vagc takes a large value (positive value), the base voltage of the leftmost transistor 33-1 in FIG. 4 is increased, and is supplied from the constant current source as the control voltage Vagc approaches 0. The voltage drop due to the current flowing through the resistor becomes dominant, and therefore the base voltage of the transistor 33 in the central portion becomes the highest. When the control voltage Vagc takes a small value (negative value), the base voltage of the rightmost transistor 33-n in FIG. 4 becomes high. Thus, the transistor 33 through which most of the current Igm drawn by the constant current source 34 flows is shifted in accordance with the control voltage Vagc in FIG.

At this time, in the control voltage generation circuit 35 of the interpolator 22 shown in FIG. 4, the amplifier 32 is connected to the base of each transistor 33, and the voltage at the connection portion of the resistor R is multiplied by a predetermined value before the transistor 33. The voltage is applied to the base. The gain of the amplifier 32 connected to the base of each transistor 33 is the same, and the amplifier 32 acts to expand the voltage difference appearing at each connection portion of the resistor group. For this reason, compared to the case where the amplifier 32 is not provided, it is difficult for a current having the same magnitude to flow through the collectors of the plurality of transistors 33. FIG. 5 shows this state. This figure corresponds to FIG. 7, and shows the control voltage Vagc and the constant current I _En−1 flowing through the collectors of the adjacent transistor 33- (n−1), transistor 33-n and transistor 33- (n + 1). , I _En and I _{En + 1} . In the figure, a broken line indicates a case where the amplifier 32 is not provided (or a case where the gain of the amplifier 32 is 1), and a solid line indicates a case where the gain of the amplifier 32 is 1 or more. As shown in the figure, due to the presence of the amplifier 32, the constant currents I _En−1 , I _En , I _{En + 1,} etc. suddenly rise from zero to peak with respect to the change of the control voltage Vagc, and then return to zero again. Come back. As a result, when most of the current flows through the collector of a certain transistor 33, the amount of current flowing through the other transistors 33 can be reduced. Further, by further increasing the gain of the amplifier 32, the maximum number of transistors 33 in which current is flowing simultaneously through the collector can be reduced from 3 to 2 at the minimum.

According to the present embodiment, the control voltage generation circuit 35 of the interpolator 22 is provided with the plurality of amplifiers 32. Therefore, by adjusting the gain, the constant current I flowing through each first differential amplifier 10 is adjusted. adjust the _E1 ~I _En, thereby to improve the various operating characteristics of the variable gain amplifier.

  The present invention is not limited to the above embodiment. For example, in the above description, the circuit is configured around npn transistors, but the circuit may be configured using other types of semiconductor elements. Further, as the amplifier, not only a differential amplifier but also other types of amplifiers may be used.

It is a figure which shows the circuit structure of the variable gain amplifier which concerns on embodiment of this invention. It is a figure which shows the circuit structure of a 1st differential amplifier. It is a figure which shows the circuit structure of an attenuator. It is a figure which shows the circuit structure of the interpolator which concerns on embodiment of this invention. It is a figure which shows operation | movement of the interpolator which concerns on embodiment of this invention. It is a figure which shows the circuit structure of the conventional variable gain amplifier. It is a figure which shows the relationship between the constant current amount and control voltage which are sent through each 1st differential amplifier. It is a figure which shows the circuit structure of the interpolator used for the conventional variable gain amplifier.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 1st differential amplifier circuit, 12 Attenuator, 14 Control terminal, 16 2nd differential amplifier, 22 Interpolator, 24 Current amplifier circuit, 31, 34 Constant current source, 32 Amplifier, 33 Transistor, 35 Control voltage generation circuit.

Claims (7)

A constant current source;
A plurality of transistors connected to the constant current source;
A control voltage generation circuit for applying a voltage for controlling the amount of current to each of the transistors;
In an interpolator that shunts a constant current formed by the constant current source according to a difference in voltage for controlling the amount of current applied to each transistor, and flows the current to each transistor.
The control voltage generation circuit includes a circuit that increases a difference between the current amount control voltages applied to the transistors.
An interpolator characterized by that. The interpolator according to claim 1, wherein
The control voltage generation circuit includes a plurality of amplifiers connected to a portion to which a voltage for controlling the amount of current of each transistor is applied.
An interpolator characterized by that. The interpolator according to claim 1 or 2,
The plurality of amplifiers or resistors have a common gain;
An interpolator characterized by that. The interpolator according to any one of claims 1 to 3,
The control voltage generation circuit applies the highest current control voltage to one of the plurality of transistors selected in a predetermined order according to an increase in a given control voltage.
An interpolator characterized by that. The interpolator according to any one of claims 1 to 3,
The control voltage generation circuit includes:
A plurality of resistors connected in series;
A plurality of second constant current sources connected to each connection portion of each resistor;
A given control voltage is applied to both ends of the plurality of resistors connected in series, and the voltage at each connection site is amplified by each amplifier.
An interpolator characterized by that.   A variable gain amplifier comprising the interpolator according to claim 1. A voltage for controlling the amount of current is applied to each of a plurality of transistors connected to a common constant current source via an amplifier,
According to the difference in voltage for controlling the amount of current applied to each transistor, the current is shunted from the constant current formed by the constant current source, and the current flows through each transistor.
A current generation method characterized by the above.

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