JP2006032846A - Manufacturing method of semiconductor device using CMP - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress excessive film reduction such as dishing and erosion due to excessive polishing as much as possible in the manufacture of a semiconductor device using chemical mechanical polishing.
A step of forming a patterned first insulating film on a semiconductor substrate, a step of forming a groove using the first insulating film as a mask, and a second insulating film are formed so as to fill the formed groove. Removing a part of the second insulating film by the first CMP using the first slurry until the surface of the first insulating film is exposed, and removing the first CMP by the second CMP using the second slurry. And a step of removing the second insulating film and the first insulating film on the first insulating film that have not been formed, wherein the first slurry and the second slurry satisfy a specific relationship. Thus, the above problem is solved.
[Selection] Figure 10

Description

  The present invention relates to a method for manufacturing a semiconductor device using chemical mechanical polishing (CMP), which can suppress excessive film loss such as dishing and erosion due to excessive polishing as much as possible.

  Conventionally, a floating gate of a flash memory has been processed by photolithography and etching. However, along with the miniaturization of flash memory, the minimum dimension of the design rule becomes 0.13 μm or less, which leads to a problem of overlay accuracy with the pn junction, and the floating gate of the flash memory uses CMP. Processing by self-alignment is mainstream. Examples of the manufacturing process are shown in FIGS.

  First, as shown in FIG. 1, a silicon oxide film 2 and a silicon nitride film 3 are sequentially deposited on a silicon substrate 1. Further, a silicon oxynitride film 4 is deposited on the silicon nitride film 3 as an antireflection film. In FIG. 1, a second silicon oxynitride film 4 'is provided as a second antireflection film in order to enhance the antireflection effect.

Next, as shown in FIG. 2, a part of the silicon oxynitride film 4 ′, the silicon oxynitride film 4, the silicon nitride film 3, and the silicon oxide film 2 is removed by a photoetching process. The groove 5 is formed by removing the portion.
Thereafter, as shown in FIG. 3, a silicon oxide film 6 for element isolation is deposited so as to completely fill the groove 5 by high density plasma CVD.

  Next, as shown in FIG. 4, the element isolation silicon oxide film 6 on the silicon oxynitride film 4 is removed by first CMP, and polishing is further performed. As shown in FIG. 3 The silicon oxynitride film 4 is completely removed from above. At this time, excessive silicon oxide film loss such as dishing due to excessive polishing occurs. A recess in the vicinity of FIG. 6 in FIG. 5 and a recess between the silicon nitride films 3 correspond to this loss.

  In the first CMP, the element isolation silicon oxide film 6 on the silicon oxynitride film 4 is removed (see FIG. 4), and further polishing is performed to completely remove the silicon oxynitride film 4 from the silicon nitride film 3. (See FIG. 5). Since there is no method of removing the silicon nitride film 3 and the silicon oxynitride film 4 simultaneously while leaving the element isolation silicon oxide film 6, the oxynitride film 4 is removed by the first CMP in order not to increase the number of steps. ing. However, since the polishing rate of the silicon oxynitride film is much lower than the polishing rate of the silicon oxide film, the silicon oxide film 6 for element isolation several times that of the silicon oxynitride film 4 is excessively polished, resulting in a depression. End up.

Next, as shown in FIG. 6, only the silicon nitride film 3 is selectively removed by isotropic etching, and the silicon oxide film 2 on the silicon substrate 1 is removed by another isotropic etching.
Thereafter, a process such as ion implantation necessary for forming a semiconductor element is performed, and as shown in FIG. 7, a tunnel silicon oxide film 8 is formed only in a specific region where the silicon substrate 1 is exposed, and a silicon nitride film is further formed. A polycrystalline silicon film 9 is deposited so as to completely fill the groove 7 formed by removing 3.

  Next, as shown in FIG. 8, the polycrystalline silicon film 9 on the element isolation silicon oxide film 6 is removed by second CMP. At this time, in the element isolation region (region of FIG. 6) having a large area, a polishing residue 9 ′ is generated due to the effect of the recess formed by the first CMP dishing and the slow polishing rate of the second CMP. In order to remove the polishing residue 9 ', further polishing is required. As a result, as shown in FIG. 9, there arises a problem that the film thickness of the polycrystalline silicon 9 serving as the floating gate becomes too thin.

  In the second CMP, the polycrystalline silicon film 9 on the element isolation silicon oxide film 6 is completely removed. Here, in order to suppress the loss amount of the element isolation silicon oxide film 6 and selectively remove only the polycrystalline silicon film 9 on the element isolation silicon oxide film 6, the polishing rate of the polycrystalline silicon film 9 is set to the element rate. Conditions that are much larger than the polishing rate of the silicon oxide film 6 for separation are used. If the polishing residue 9 'shown in FIG. 8 is to be removed under such conditions, the polycrystalline silicon film 9 is excessively polished and the film thickness becomes thin. That is, the polycrystalline silicon film 9 of the polishing residue 9 'is surrounded by the wide element isolation silicon oxide film 6 region, so that the force supported by the silicon oxide film is strong and the polishing rate is low. On the other hand, a region where the polycrystalline silicon film 9 is dense like a memory cell has a low polishing rate because the density of the element isolation silicon oxide film 6 region is low and the supporting force of the silicon oxide film is weak. Relatively fast. For this reason, the above results are produced.

A method for manufacturing the floating gate as described above is disclosed in, for example, Japanese Patent Laid-Open No. 2002-299479 (Patent Document 1).
As described above, the conventional technique has a problem that the film thickness of the floating gate is reduced due to excessive film reduction such as dishing and erosion due to excessive polishing in the CMP process. When the thickness of the floating gate is reduced, the contact area between the sidewall of the floating gate and the ONO film is reduced, and as a result, the ONO capacity as a capacitor is reduced. As is generally known, when the ONO capacity is reduced, the writing and erasing speeds are lowered, and the device performance as a flash memory is lowered.

On the other hand, in order to obtain a floating gate having a desired film thickness, it is conceivable to increase the film thickness of the silicon nitride film 3 in FIG. 1, but the pattern processing in FIG. 2 becomes difficult and the processing performance decreases. End up.
Therefore, in order to form a floating gate without deteriorating element performance and processing performance, it is important to suppress excessive film loss in CMP.

JP 2002-299479 A

  An object of the present invention is to suppress excessive film reduction such as dishing and erosion due to excessive polishing as much as possible in the manufacture of a semiconductor device using chemical mechanical polishing.

  The inventor of the present invention, as a result of intensive studies to solve the above problems, by selectively using two or more types of slurry having different selectivity (polishing rate) in accordance with the chemical mechanical polishing process, It has been found that excessive film reduction such as dishing and erosion due to excessive polishing can be suppressed, and the present invention has been completed.

According to the present invention,
Forming a patterned first insulating film on the semiconductor substrate;
Forming a groove using the first insulating film as a mask;
Forming a second insulating film so as to fill the formed trench;
Removing a part of the second insulating film by first CMP using the first slurry until the surface of the first insulating film is exposed;
Removing the second insulating film and the first insulating film on the first insulating film that have not been removed by the first CMP by the second CMP using the second slurry, and the first slurry and the second slurry are of the formula :
(R2 / R1)> (R4 / R3)
(Where R1 is the polishing rate of the first slurry for the first insulating film, R2 is the polishing rate of the first slurry for the second insulating film, and R3 is the polishing rate of the second slurry for the first insulating film) Yes, R4 is the polishing rate of the second slurry for the second insulating film)
A semiconductor device manufacturing method characterized by satisfying the above relationship is provided.

According to the present invention, in the manufacture of a semiconductor device using chemical mechanical polishing, specifically, formation of a floating gate by self-alignment, excessive film reduction such as dishing and erosion due to excessive polishing can be suppressed as much as possible. Therefore, it is possible to easily provide a desired floating gate film thickness, and it is possible to provide a flash memory having excellent device performance without a decrease in writing or erasing speed due to a decrease in ONO capacity.
The present invention is suitable for forming shallow trench isolation (STI).

The semiconductor device manufacturing method of the present invention is characterized in that two or more types of slurries having different polishing rates are selectively used in accordance with the chemical mechanical polishing process.
The slurry that can be used in the present invention is a chemical abrasive having a controlled pH containing abrasive grains such as alumina, and examples thereof include known slurries in semiconductor production. Specifically, it contains abrasive grains such as silica (silicon dioxide: SiO ₂ ), alumina (aluminum oxide: Al ₂ O ₃ ), and ceria (cerium oxide: CeO), and pH is adjusted with an alkali such as KOH or NH ₄ OH. Controlled slurry, organic amine-based slurry and the like can be mentioned.

In the present invention, the “polishing rate” generally refers to the distance (depth or thickness) from the surface before polishing of the material to be polished to the vertical polishing arrival surface per minute in the polishing step, that is, the polishing rate (Å / Min). The polishing rate varies depending on the particle size distribution and concentration of abrasive grains in the slurry, the type of slurry such as the pH of the slurry, and polishing conditions related to the CMP apparatus such as the wafer rotation speed, pad rotation speed, pressure, and slurry flow rate.
In the present invention, the ratio of the polishing rate of two or more types of slurry to the material to be polished is important. In polishing, the type of slurry and the polishing conditions may be appropriately set depending on the type of material to be polished and the processing shape. .

Hereinafter, although the manufacturing method of the semiconductor device of this invention is demonstrated based on FIGS. 1-4 and FIGS. 10-14, this invention is not limited from this. 1 to 4 are the same as in the prior art.
Note that the method for manufacturing a semiconductor device of the present invention is characterized by its manufacturing process, and the material of each component of the semiconductor device is not particularly limited, and can be formed of a known material.

First, as shown in FIG. 1, a silicon oxide film 2 having a thickness of about 100 mm is formed on a silicon substrate (semiconductor substrate) 1 by, eg, thermal oxidation. A silicon nitride film 3 having a thickness of 1000 to 2500 mm is deposited thereon by, eg, CVD. Further thereon, a silicon oxynitride film 4 (first insulating film) having a thickness of about 300 mm is deposited as an antireflection film by, eg, CVD. In order to enhance the antireflection effect, it is preferable to form a second silicon oxynitride film (first 'insulating film) 4' having a different refractive index as the second antireflection film.
Here, the first insulating film and the second insulating film mean one or more insulating films made of one or more materials.

Next, as shown in FIG. 2, the silicon oxynitride film 4 ′, the silicon oxynitride film 4, the silicon nitride film 3, and the silicon oxide film 2 are partially removed by, for example, a photoetching process. A portion of 1500 to 3000 mm is removed to form the groove 5.
Thereafter, as shown in FIG. 3, an element isolation silicon oxide film (second insulating film) 6 having a thickness of 4000 to 6000 mm is deposited so as to completely fill the groove 5 by, for example, high-density plasma CVD.

Next, as shown in FIG. 4, for the element isolation on the silicon oxynitride film 4 under the conditions shown in Table 1 by the first CMP using the ceria slurry added with the surfactant that satisfies the relationship of the following formula: The silicon oxide film 6 is removed. That is, in the first CMP from the initial stage of polishing until a part of the surface of the silicon oxynitride film 4 is exposed, the polishing rate of the silicon oxide film is much larger than the polishing rate of the silicon oxynitride film and the density of the underlying pattern is low. The first slurry and polishing conditions that are not easily affected by the above are used.
R2 / R1 = polishing rate of silicon oxide film / polishing rate of silicon oxynitride film = 30/1

After the completion of the first CMP, the silicon substrate 1 is continuously taken out of the CMP apparatus and then subjected to oxynitridation on the silicon nitride film 3 under the conditions shown in Table 1 by second CMP using a silica slurry satisfying the relationship of the following formula: The silicon film 4 is completely removed. That is, in the second CMP from when a part of the surface of the silicon oxynitride film 4 is exposed to the end of polishing, the difference in the polishing rate between the silicon oxynitride film and the silicon oxide film is small, or the polishing rate of the silicon oxide film is low. A second slurry and polishing conditions are used.
R4 / R3 = polishing rate of silicon oxide film / polishing rate of silicon oxynitride film = 2/1

As described above, the first slurry and the second slurry satisfy the relationship (R2 / R1)> (R4 / R3).
By this series of polishing, as shown in FIG. 10, the polishing loss amount of the element isolation silicon oxide film 6 can be suppressed as compared with the prior art.
According to the inventor of the present invention performing polishing under the above conditions, the amount of polishing loss was about 600 mm compared to about 1500 mm of the prior art.

  When the first insulating film and the second insulating film are a silicon oxynitride film and a silicon oxide film, respectively, it is preferable that the first slurry and the second slurry are a ceria slurry and a silica slurry, respectively.

The method for manufacturing a semiconductor device of the present invention further includes a step of forming a third insulating film between the first insulating film and the second insulating film, and is not removed by the first CMP by the second CMP using the second slurry. Alternatively, the third insulating film may be removed together with the second insulating film on the first insulating film. At this time, the first slurry and the second slurry have the formula:
(R2 / R5)> (R4 / R6)
(Where R5 is the polishing rate of the first slurry for the third insulating film, R2 is the polishing rate of the first slurry for the second insulating film, and R6 is the polishing rate of the second slurry for the third insulating film) Yes, R4 is the polishing rate of the second slurry for the second insulating film)
It is preferable to satisfy this relationship. The third insulating film means one or more insulating films made of one or more materials.

Next, as shown in FIG. 11, only the silicon nitride film 3 is selectively removed by, for example, a wet etching method using phosphoric acid, and further, on the silicon substrate 1 by, for example, a wet etching method using hydrofluoric acid. The silicon oxide film 2 is removed. Thereafter, processing such as ion implantation necessary for element formation is performed by a known method. In the figure, 7 indicates a groove formed by removing the silicon nitride film 3.
Next, as shown in FIG. 12, a tunnel silicon oxide film 8 having a film thickness of about 100 mm is formed only on the silicon substrate 1 in the region where the silicon substrate 1 is exposed, for example, by thermal oxidation. As a semiconductor film, a polycrystalline silicon film 9 having a thickness of about 1500 mm is deposited so as to completely fill the trench 7.

Next, as shown in FIG. 13, by the third CMP using the organic amine slurry that satisfies the relationship of the following formula, a large number of silicon oxide films 6 on the element isolation serving as the memory cell region are formed under the conditions shown in Table 1. The crystalline silicon film 9 is removed. In the third CMP from the initial stage of polishing until a part of the surface of the element isolation silicon oxide film 6 is exposed, a third slurry and polishing conditions in which the polishing rate of the polycrystalline silicon film is much larger than the polishing rate of the silicon oxide film. Is used.
R8 / R7 = Polycrystalline silicon film polishing rate / Silicon oxide film polishing rate = 200/1
After the above polishing, there is a polishing residue 9 'of the polycrystalline silicon film on the surface of the wide element isolation region.

After the completion of the third CMP, the silicon substrate 1 is continuously removed without being taken out from the CMP apparatus, and the fourth CMP using the silica slurry satisfying the relationship of the following formula is performed for element isolation that becomes the memory cell region under the conditions shown in Table 1. The polycrystalline silicon film 9 (polishing residue 9 ′) on the silicon oxide film 6 is completely removed. That is, in the fourth CMP from when a part of the surface of the element isolation silicon oxide film 6 is exposed to the end of polishing, the fourth slurry and the polishing conditions with a small difference in polishing rate between the silicon oxide film and the polycrystalline silicon film are used. Thereby, the influence of the difference in density of the underlying pattern is reduced, and the polishing rate 9 of the polycrystalline silicon film 9 and the polishing rate of the polycrystalline silicon 9 on the element isolation silicon oxide film 6 serving as the memory cell region are substantially the same. .
R10 / R9 = Polycrystalline silicon film polishing rate / silicon oxide film polishing rate = 3/1

As described above, the third slurry and the fourth slurry satisfy the relationship of (R8 / R7)> (R10 / R9).
By this series of polishing, as shown in FIG. 14, the amount of polishing loss of the polycrystalline silicon film 9 on the tunnel silicon oxide film 8 which becomes the memory cell region can be suppressed.
According to the inventor of the present invention performing polishing under the above conditions, the amount of polishing loss is about 4.5 mm, compared with about 300 mm of the conventional technique using only the third slurry, and the amount of polishing loss. Was reduced to 3/200.

As described above, after removing the second insulating film and the first insulating film on the first insulating film,
Forming a groove;
Forming a semiconductor film on the entire surface of the semiconductor substrate so as to fill the groove;
Removing a part of the semiconductor film by third CMP using the third slurry until the surface of the second insulating film is exposed;
A step of removing a semiconductor film on the second insulating film that has not been removed by the third CMP may be further included by the fourth CMP using the fourth slurry. At this time, the third slurry and the fourth slurry have the formula:
(R8 / R7)> (R10 / R9)
(Where R7 is the polishing rate of the third slurry for the second insulating film, R8 is the polishing rate of the third slurry for the semiconductor film, and R9 is the polishing rate of the fourth slurry for the second insulating film, R10 is the polishing rate of the fourth slurry for the semiconductor film)
It is preferable to satisfy this relationship.

  When the second insulating film and the semiconductor film are a silicon oxide film and a polycrystalline silicon film, respectively, the third slurry and the fourth slurry are preferably an organic amine slurry and a silica slurry, respectively.

  In the above-described series of steps, the first CMP, the second CMP, and the third CMP and the fourth CMP are continuously performed on the same platen, or are continuously performed on another platen using the same apparatus. Is preferred. Here, the “platen” means a wafer holding plate used in the wafer processing step.

It is a schematic sectional drawing which shows the 1st step of the semiconductor element formation process by a prior art and this invention. It is a schematic sectional drawing which shows the 2nd step of the semiconductor element formation process by a prior art and this invention. It is a schematic sectional drawing which shows the 3rd step of the prior art and the semiconductor element formation process by this invention. It is a schematic sectional drawing which shows the 4th step of the prior art and the semiconductor element formation process by this invention. It is a schematic sectional drawing which shows the 5th step of the semiconductor element formation process by a prior art. It is a schematic sectional drawing which shows the 6th step of the semiconductor element formation process by a prior art. It is a schematic sectional drawing which shows the 7th step of the semiconductor element formation process by a prior art. It is a schematic sectional drawing which shows the 8th step of the semiconductor element formation process by a prior art. It is a schematic sectional drawing which shows the 9th step of the semiconductor element formation process by a prior art. It is a schematic sectional drawing which shows the 5th step of the semiconductor element formation process by this invention. It is a schematic sectional drawing which shows the 6th step of the semiconductor element formation process by this invention. It is a schematic sectional drawing which shows the 7th step of the semiconductor element formation process by this invention. It is a schematic sectional drawing which shows the 8th step of the semiconductor element formation process by this invention. It is a schematic sectional drawing which shows the 9th step of the semiconductor element formation process by this invention.

Explanation of symbols

1 Silicon substrate (semiconductor substrate)
2 Silicon oxide film 3 Silicon nitride film 4 Silicon oxynitride film (first insulating film: antireflection film)
4 ′ second silicon oxynitride film (first ′ insulating film: second antireflection film)
5, 7 Groove 6 Element isolation silicon oxide film (second insulating film)
8 Tunnel silicon oxide film 9 Polycrystalline silicon film (semiconductor film)
9 'Unpolished

Claims (6)

Forming a patterned first insulating film on the semiconductor substrate;
Forming a groove using the first insulating film as a mask;
Forming a second insulating film so as to fill the formed trench;
Removing a part of the second insulating film by first CMP using the first slurry until the surface of the first insulating film is exposed;
Removing the second insulating film and the first insulating film on the first insulating film that have not been removed by the first CMP by the second CMP using the second slurry, and the first slurry and the second slurry are of the formula :
(R2 / R1)> (R4 / R3)
(Where R1 is the polishing rate of the first slurry for the first insulating film, R2 is the polishing rate of the first slurry for the second insulating film, and R3 is the polishing rate of the second slurry for the first insulating film) Yes, R4 is the polishing rate of the second slurry for the second insulating film)
A semiconductor device manufacturing method characterized by satisfying the relationship:   2. The semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are a silicon oxynitride film and a silicon oxide film, respectively, and the first slurry and the second slurry are a ceria slurry and a silica slurry, respectively. Production method. The method further includes a step of forming a third insulating film between the first insulating film and the second insulating film, and the second insulating on the first insulating film that has not been removed by the first CMP by the second CMP using the second slurry. Removing the third insulating film along with the film, wherein the first slurry and the second slurry are of the formula:
(R2 / R5)> (R4 / R6)
(Where R5 is the polishing rate of the first slurry for the third insulating film, R2 is the polishing rate of the first slurry for the second insulating film, and R6 is the polishing rate of the second slurry for the third insulating film) Yes, R4 is the polishing rate of the second slurry for the second insulating film)
The method according to claim 1 or 2, satisfying the relationship: Forming a groove after removing the second insulating film and the first insulating film on the first insulating film;
Forming a semiconductor film on the entire surface of the semiconductor substrate so as to fill the groove;
Removing a part of the semiconductor film by third CMP using the third slurry until the surface of the second insulating film is exposed;
A step of removing the semiconductor film on the second insulating film that has not been removed by the third CMP by the fourth CMP using the fourth slurry, and the third slurry and the fourth slurry are represented by the formula:
(R8 / R7)> (R10 / R9)
(Where R7 is the polishing rate of the third slurry for the second insulating film, R8 is the polishing rate of the third slurry for the semiconductor film, and R9 is the polishing rate of the fourth slurry for the second insulating film, R10 is the polishing rate of the fourth slurry for the semiconductor film)
The method for manufacturing a semiconductor device according to claim 1, wherein the relationship is satisfied.   5. The semiconductor device according to claim 4, wherein the second insulating film and the semiconductor film are a silicon oxide film and a polycrystalline silicon film, respectively, and the third slurry and the fourth slurry are an organic amine-based slurry and a silica slurry, respectively. Production method.   6. The first CMP, the second CMP, and the third CMP and the fourth CMP are sequentially performed on the same platen or continuously performed on the different platen using the same apparatus. A method for manufacturing a semiconductor device.

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