JP2006032365A - Forming method of electroluminescent display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a dielectric layer of an electroluminescent laminate. <P>SOLUTION: The dielectric layer is made of a ceramic material as a thick film layer. The dielectric layer has a withstanding voltage of about 1.0×10<SP>6</SP>V/m, and the ratio of the dielectric constant of the dielectric material to a phosphorescent layer is larger than 50:1, and the ratio of the thickness of the dielectric layer to that of the phosphorescent layer ranges between 20:1 and 500:1. The dielectric layer is compatible with the phosphorescent layer having a surface contacting with the phosphorescent layer which is smooth enough for making the phosphorescent layer totally and uniformly emit light at a prescribed exciting voltage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electroluminescent laminate and a method for producing an electroluminescent laminate. The present invention also relates to an electroluminescent display panel that provides electrical connection from the electroluminescent laminate to the voltage drive circuit. The invention further relates to a laser that engraves a pattern in a flat laminate. The pattern is, for example, an address line of a transparent electrode of an electroluminescent laminate.

  Electroluminescence (EL) is the emission of light from a phosphor by applying an electric field. The electroluminescent element is useful as a lamp or display. Recently, electroluminescent elements are used in flat panel display elements. This element has a predetermined characteristic shape or individually addressable pixels in a rectangular matrix.

  A pioneering study of electroluminescence was done at GTE Sylvania. An alternating voltage is supplied to the powder or scattering type EL element. In this device, light emitting phosphor powder is embedded in an organic adhesive, which is deposited on a glass substrate and covered with a transparent electrode. These powder or scattering type EL elements generally have a low luminance and have a drawback of hindering a wide range of applications.

  Thin film electroluminescent (TFEL) devices were developed in the 1950s. The basic structure of the AC thin film EL laminate is well known, and is described in, for example, Non-Patent Document 1 and Patent Document 1. The phosphor layers are sandwiched between electrode pairs and are separated from the electrodes by respective insulating / dielectric layers. Most commonly, the fluorescent material is ZnS containing Mn as an activator (dopant). ZnS: MnTFEL emits yellow light. Other color phosphors have been developed.

  Conventional TFEL laminate films are deposited on a substrate, usually glass. Film deposition is effected by substantially known thin film techniques such as electron beam vacuum deposition or sputtering. Recently, it is performed by atomic film epitaxy (ALE). The total thickness of the TFEL laminate is only on the order of 1 or 2 microns.

  Various insulating / dielectric materials are known to separate and electrically insulate the fluorescent layer from the electrodes and are used as described in detail later.

  Each of the two electrodes is different depending on whether it is on the “rear” or “front” side (in the viewing direction) of the element. A reflective material such as aluminum is typically used for the rear electrode. A relatively thin and optically transparent indium tin oxide (ITO) is typically used for the front electrode. When applied to a lamp, the two electrodes take the form of a continuous film, whereby the entire phosphor layer is exposed to an electric field between the electrodes. In a typical display application, the front and rear electrodes are appropriately patterned with conductive address lines that define row and column electrodes. Pixels are defined where the row and column electrodes overlap. Various electronic display elements are known that address individual pixels by simultaneously applying a voltage to one row electrode and one column electrode.

  Although simple in concept, there are a number of practical difficulties in developing thin film electroluminescent devices. The first difficulty is that the elements are formed from individual laminates deposited by thin film technology. This is because thin film technology is time consuming and costly. Very small defects in the membrane can also cause failure. Secondly, these thin film devices are typically operated at relatively high voltages (eg, 300-450 V at peak peak). In fact, this voltage is enough to cause the phosphor layer to operate beyond its breakdown voltage, making it conductive. A thin film dielectric layer on either side of the phosphor layer is required to limit or prevent conduction between the electrodes. Application of a large electric field causes dielectric breakdown between the electrodes and causes device failure.

  In particular, the present invention prevents discharge through the insulating / dielectric and fluorescent layers of the electroluminescent device. In order for the electroluminescent element to operate well, it is necessary that the electrodes (address lines) be insulated from the fluorescent layer. This is done by an insulating / dielectric layer. Typically, an insulating / dielectric layer is provided on both sides of the phosphor layer and is formed from alumina, yttria, silicon dioxide, silicon nitride or other dielectric material. During device operation, electrons from the interface between the insulating layer and the phosphor layer are accelerated by the electric field so that they pass through the phosphor layer, collide with dopant atoms in the phosphor layer, and emit light as a result of the collision process. To do. In conventional TFEL elements, the dielectric layer is usually thinner or as thick as the phosphor layer to ensure that the electric field strength through the phosphor is sufficiently high. If the dielectric layer is too thick, most of the voltage supplied between the address lines will pass through the dielectric layer rather than the fluorescent layer.

  It is important that the dielectric layer is compatible with the fluorescent layer. By “compatible” is meant in the present description and claims that a good injection interface is formed first. That means that the source of “thermal” electrons is at the fluorescent interface and can be promoted and tunneled to the fluorescent conduction band to initiate conduction and light emission in the fluorescent layer based on the application of an electric field. Secondly, in a compatible sense, it means that the dielectric material must be chemically stable so that it does not react with adjacent layers (ie phosphors and electrodes).

  In order to obtain sufficient light emission in a typical TFEL, the supplied voltage is very close to the voltage at which dielectric breakdown occurs. Therefore, manufacturing control regarding the thickness and quality of the dielectric layer and the fluorescent layer must be strictly performed to prevent dielectric breakdown. This demand, on the other hand, makes it difficult to get a high yield.

  A typical TFEL structure is formed from the front side to the rear side (in the viewing direction). The thin film is continuously deposited on a suitable substrate. A glass substrate is used to obtain transparency. A transparent front electrode (ITO address line) is deposited on the glass substrate to a thickness of about 0.2 microns by sputtering. The substrate dielectric-phosphor-dielectric layer is usually deposited by sputtering or vacuum evaporation. The thickness of the fluorescent layer is typically about 0.5 microns. The thickness of the dielectric layer is typically about 0.4 microns. The phosphor layer is usually annealed after deposition to increase efficiency at about 450 ° C. A back electrode is then added, typically in the form of 0.1 micron thick aluminum address lines. The finished TEFL laminate is encapsulated to protect it from external moisture. Epoxy sheet cover glass or silicone oil capsules are used. Since the initial substrate used for deposit is typically glass, the materials and deposition techniques used in TEFL laminate structures cannot be processed at high temperatures.

  The high electric field strength used to operate the TFEL element places severe demands on the dielectric layer. High dielectric strength is required to avoid dielectric breakdown. A dielectric having a high dielectric constant is advantageous for obtaining luminous efficiency at the lowest possible driving voltage. However, satisfactory results have not been obtained by attempts to use high dielectric constant materials.

In order to lower the driving voltage of the TFEL element, the insulating layer is formed from a high dielectric constant material, for example, SrTiO ₃ , PbTiO ₃ , BaTa ₂ O ₃ . This is described in Patent Document 1. However, these materials do not exhibit good dielectric breakdown strength. Patent Document 1 describes that a dielectric layer is formed by a thin film deposition technique in order to obtain an increased planar orientation (111) from a perovskite crystal structure. In this specification, high dielectric strength (about 8 × 10 ⁵ to about 1.0 × 10 ⁶ V / cm) is about 0.5 micron thick using SrTiO ₃ , PbTiO ₃ , BaTa ₂ O ₃ . It is described that it can be obtained by a dielectric layer. They all have a high dielectric constant and a perovskite crystal structure. This device is complex and difficult to control with thin film deposition techniques on dielectric layers.

Development of a TFEL element using a thin plate ceramic insulating layer and a thin film electrolumine essence has also been performed (see Non-Patent Document 2). This element is formed from a BaTiO ₃ ceramic sheet. The sheet is formed by casting fine BaTiO ₃ powder into a disk (diameter 20 mm) and using a conventional cold press method. The disc is fired in air at 1300 ° C. Next, it is ground into a sheet having a thickness of about 0.2 mm. The emissive layer is deposited as a thin film on the sheet using chemical vacuum deposition or RF magnetron sputtering. A suitable electrode layer is then deposited on either side of the structure using thin film technology. Although this element exhibits the desired characteristics, it is not preferred to produce a commercial TFEL element from a solid ceramic sheet. Polishing a large ceramic sheet to a constant thickness of 0.2 mm is not economically feasible.

  It is also known to use multilayer insulation / dielectric layers on both sides of the phosphor layer. For example, Patent Document 2 discloses a TFEL in which an EL phosphor layer is sandwiched between an insulating deposited body pair. In this case, one or both of the insulating deposits has a first layer of silicon oxynitride (SiON) and a second relatively thick layer of barium tantalate (BTO). The first SiON layer exhibits high insulation, and the second BTO layer has a high dielectric constant. Overall, this structure is characterized by a high brightness of the fluorescent layer at conventional voltages. However, the insulating layer is deposited by RF sputtering, which is disadvantageous for the previously described thin film technology.

  There is a need for a TFEL element that is advantageous to manufacture and has a higher brightness and lower operating voltage than conventional TFEL elements. This requires obtaining a dielectric layer having a dielectric strength higher than the field strength required to drive the device.

  Fabricating electrode patterns in transparent conductive materials such as indium tin oxide often involves large and expensive masking, photolithographic and chemical etching processes. Lasers have been proposed for drawing such transparent conductive materials. Generally, carbon dioxide gas, argon and YAG laser are used. Such lasers produce light in the visible and infrared regions (generally 400 nm or more) of the electromagnetic spectral region. However, the use of such long wavelength light for scribing the electrode pattern is problematic, especially when the transparent conductive material is deposited on another transparent layer. In conventional TFEL displays, a transparent electrode material, typically indium tin oxide (ITO), is deposited before the transparent display is lathed and the other layers of the EL laminate are deposited. Insulating materials or semiconductor materials do not strongly absorb light of wavelengths longer than corresponding to the energy of the electronic band gap in the material. For optically transparent materials, the wavelength corresponding to the band gap is shorter than the wavelength for visible light. Therefore, the transparent electrode material does not absorb much laser light. This is due to the long wavelength of light and the thin layer thickness, which makes it difficult to use laser energy to directly remove electrode address lines.

  Patent Document 3 and Patent Document 4 describe a process for depositing a transparent electrode pattern on another transparent layer in a solar cell. These patents disclose patterning the electrodes using a pulsed YAG laser. However, the wavelength of the YAG laser is too long to be sufficiently absorbed by the transparent layer. In order to compensate for the low absorption rate, a high peak power laser is used to thermally evaporate the transparent electrode. The neodymium YAG laser is operated at 4-5 W, a pulse rate of 36 kHz, and a scanning rate of 20 cm / s. In the embodiment described in the patent specification, an ITO layer is thus deposited on the glass. However, the scribed lines are described as having incomplete removal of ITO, and where melted, the glass has a depth of up to several hundred angstroms. Residual ITO must be removed by a subsequent etching step.

  Another means for forming an electrode pattern on the transparent electrode material is to use an excimer laser. This laser produces light with a relatively short wavelength in the ultraviolet region of the electromagnetic spectrum. At this wavelength, laser energy can be absorbed by the transparent electrode material. It is known that a laser having this property forms a conductive pattern for a liquid crystal display (Patent Documents 5 and 6), an optical voltaic cell (Patent Documents 7 and 8), and an integrated circuit (Patent Document 9). . Patent Document 10 published on August 23, 1990 describes a process of scribing an electrode dot matrix pattern onto a transparent conductor on a transparent substrate with an excimer laser.

  Excimer lasers can be patterned by emitting light of a wavelength short enough to be absorbed by the transparent electrode and removing the electrode directly. However, such lasers are relatively expensive and the scribe process must be carefully controlled so as not to melt or remove the underlying display glass. Furthermore, such a process can lead to excessive or incomplete removal of the transparent electrode material. For example, Patent Document 10 describes that when only a part of the material to be removed is removed, the remaining part can be removed by chemical or plasma etching.

  Another problem in scribing a transparent electrode material on a transparent substrate is described in Patent Document 11. It is described that a diffusion barrier layer is provided at the interface to avoid interlayer diffusion or cross-contamination.

  Another patent specification describes surface treatment of a transparent electrode material to enhance the absorption of laser light. For example, Patent Document 12 describes that a metal film surface is oxidized so as not to be relatively reflected by laser light. Patent Document 13 describes that a transparent layer to be removed is coated with a dye so that laser light is selectively absorbed at a place where removal is desired.

  Control circuits for driving EL displays have been developed. Basically, this circuit converts serial video data into parallel data and supplies voltages to the rows and columns of the display. Such row and column driver elements (chips) are available.

  Asymmetric and symmetric drive techniques are used in EL display technology. In the asymmetric driving method, a driving pulse is supplied to the EL panel by simultaneously applying a negative sub-threshold voltage to one column. During the scan time of each column, a positive voltage pulse is applied to the selected row (i.e., the row to be lit) and the non-selected row (i.e., the row that should not be lit) is supplied with zero voltage. At the selected row and column intersection, a voltage equal to the sum of the subthreshold column voltage and the row positive pulse voltage is supplied through the pixel, causing light emission. After all the columns of the panel are addressed, a positive polarity refresh pulse is applied to all the columns simultaneously and all the rows are held at 0V.

  In the symmetric drive method, the refresh pulse is omitted. Instead, opposite polarity drive pulse sets are supplied to the panel. To keep the panel in operation, the columns are scanned in even and odd frames with alternating polarity pulses. The alternating polarity causes a net zero charge at every display pixel.

  High voltage driver elements (chips) as described above are available with both asymmetric and symmetric drive technologies.

  Elements for alternating drive circuits and EL displays are known and developed. For example, see Non-Patent Document 3, Non-Patent Document 4, and Non-Patent Document 5.

  The above driving method is called a multiplexed (passive) matrix addressing method. Theoretically, other driving methods such as active matrix addressing can also be used for EL displays. However, these have not been developed yet. Such an alternating drive method should be viewed as within the meaning of the phrase voltage drive circuit used herein.

  In a conventional EL display, one means of connecting the row and column address lines to the drive circuit is to use a polymer strip comprising a very large number of metal sheets in close proximity and contact columns connected to the display address lines. The pressure is applied between the contact rows connected to the driver elements of the drive circuit. The drive circuit is arranged on a separate circuit board (see Patent Document 14). Polymerized strips are layered elastomeric elements (LEE) and are known under the trade names STAX and ZEBRA. LEE consists of alternating layers of conductive elastomeric material and non-conductive elastomeric material. The polymerized strip avoids the laborious connecting operation of connecting hundreds of individual wires to the contacts using solder or welding. However, this interconnect technique is impractical and does not work well at high temperatures that cause the polymerized material to creep.

  It is conceivable to use another means commonly used to connect row and column address lines to a liquid crystal display (LCD) drive circuit, namely chip-on-glass technology (COG) for electroluminescence. The driving element (chip) to which the address line must be connected is arranged around the end of the display. In the case of LCDs, address lines deposited on the back side of the display glass extend from the active area of the display. Thus, the address lines terminate in contact pads arranged in the pattern, so that the chip can be bonded to it. Wire bonding requires that the chip be attached to the display glass and that the fine gold wire be individually connected to the chip's output pads and the corresponding contact pads of the address lines.

  The advantage of the COG technology is that the number of contacts between the display glass and the driving circuit can be greatly reduced. This is because there are far more contacts between the driver chip and the address lines. There are typically only 20 to 30 connections between the driver chip and other parts of the drive circuit, but there are as many as 2000 connections between the address lines.

  A major drawback of COG technology is the difficulty of wire bonding the driver chip to the thin film pad of the address line. Therefore, the production yield is bad. Another disadvantage is that space is required around the display to install the driver chip. Thus, the display size increases and multiple display modules cannot be combined in an array to form a large display.

  Through-hole technology for direct circuit connection is widely known in the semiconductor field (see, for example, Patent Document 15). From US Pat. No. 6,057,059, a method and apparatus for through-hole board printing using controlled vacuum is known. However, through-hole printing cannot be successfully applied to EL displays to the knowledge of the inventors.

Patent Document 17 describes a segment storage format of EL elements. Here, the pixels are turned on by light to form a photoelectric layer, and then the phosphor layer becomes conductive. The complexity of the through-hole conductor is described. This specification suggests that normal through-hole connections do not work with high resolution TFEL displays. This is because the conductive material reacts with the phosphor, thereby reducing the display capability.
Tonqvist, R.O., Thin-Film Electroluminescent Displays, Society for Information Display (Socity for Information Display, 198) Symposium Seminar Lecture Notes) US Pat. No. 4,857,802 Miyata, T. et al., “SID 91 Digest”, p. 70-p. 73 and p. 286-p. 289 U.S. Pat. No. 4,897,319 U.S. Pat. No. 4,292,092 US Pat. No. 4,667,058 US Pat. No. 4,980,366 US Pat. No. 4,927,493 US Pat. No. 4,783,421 U.S. Pat. No. 4,854,974 US Pat. No. 5,091,149 International Publication No. 90/0970 Specification US Pat. No. 4,937,129 US Pat. No. 4,909,895 US Pat. No. 4,568,409 K. Shoji et al., Bidirectional Push-Pull Symmetric Driving Method of T.F.E. L Display In Physics (Springer Processings in Physics), Vol. 38, 1989, 324 Sutton et al., Recent Developments and Trends in Thin Films and Trends in Thin-Film Electronic Dispensing, Inspired, Principals , Vol. 38, 1989, 318 Bolger et al., A Second Generation Chip Set for Driving EL Panels, S.I.D. (SID), 1985,229. US Pat. No. 4,508,990 US Pat. No. 3,641,390 US Pat. No. 4,710,395 US Pat. No. 3,504,214

  An object of the present invention is to provide an electroluminescent device that has high luminous efficiency and is easy to manufacture.

According to the present invention, the above-mentioned problem is achieved by the present invention in which the flat layer has a dielectric strength of about 1.0 × 10 ⁶ V / m or more, and the dielectric constant in which the ratio of the dielectric constant of the dielectric material to the dielectric constant of the phosphor is about 50: 1 or more. The dielectric layer has a thickness in which the ratio of the thickness of the dielectric layer to the phosphor layer is in the range of about 20: 1 to 500: 1, the dielectric layer being a surface adjacent to the phosphor layer EL laminate dielectric layer structure having a dielectric layer configured such that the surface is compatible and sufficiently smooth with the phosphor layer, and the phosphor layer generally emits light uniformly under a predetermined excitation voltage It is solved by.

SUMMARY OF THE INVENTION Electroluminescent layers have different dielectric constants. The potential difference between the layers of the laminate is distributed in each layer in proportion to the thickness of each layer and in inverse proportion to the relative dielectric constant of the material. For example, if one layer has twice the thickness and dielectric constant of another layer, the voltage is evenly distributed between these two layers. The present invention utilizes this property to combine a thick dielectric layer having a high dielectric constant with a thin fluorescent layer having a significantly lower dielectric constant. Thus, sufficient voltage across the pixel can exist across the phosphor layer if the dielectric layer has a sufficiently high dielectric constant before conduction by the phosphor layer begins. The present invention provides a new and improved EL laminate having an improved dielectric layer and a method of making the same. The dielectric layer is formed from the following ceramic material as a thick film.
The dielectric strength is about 1.0 × 10 ⁶ V / m or more.
- the ratio of the dielectric constant of the dielectric material and (k ₂₎ the dielectric constant of the phosphor layer (k ₁₎ from about 50: 1 or more (preferably 100: 1 or higher).
The ratio of the thickness of the dielectric layer (d ₂ ) to the thickness of the phosphor layer (d ₁ ) is in the range of about 20: 1 to 500: 1 (preferably 40: 1 to 300: 1).
-The surface adjacent to the fluorescent layer is compatible with the fluorescent layer and is sufficiently smooth, and the fluorescent layer generally emits uniformly at a predetermined excitation voltage.

The laminate comprising the dielectric layer of the present invention is most advantageously a laminate in which the fluorescent layer is a thin film layer. A typical thin film phosphor layer is formed from ZnS: Mn to a thickness of about 0.2 to 2.0 microns, typically about 0.5 microns. The ZnS: Mn material has a dielectric constant of about 5 to 10. Based on this most advantageous phosphor layer in theoretical calculations (see the above guidelines), the dielectric layer of the present invention preferably has a dielectric constant of 500 or more, most preferably about 1000 or more. The thickness is also in the range of about 10 to 300 microns, preferably in the range of 20 to 150 microns. In order to obtain a high dielectric constant, a ferroelectric material is advantageous. Most preferably they have a perovskite crystal structure. For example, the material includes PbNbO ₃ , BaTiO ₃ , SrTiO ₃ , PbTiO ₃ .

  The dielectric layer of the present invention is formed in a laminate, which is constructed from the back surface to the front surface (display surface). The back electrode is therefore deposited on the substrate, most preferably a ceramic such as alumina. This can withstand much higher temperatures than the glass substrate during manufacture (the glass substrate is used from the front side to the back side of the TFEL structure to obtain frontal transparency). The next dielectric layer of the present invention is deposited on the back electrode by thick film technology. It is fired at high temperatures, but it can withstand the substrate and the back electrode. The use of thick film technology and high temperature firing is important for the overall properties of the dielectric layer. This is because a dense layer with a high degree of crystallinity is obtained, which improves the overall dielectric constant and the dielectric strength of the layer.

  In practice, the inventor finds it difficult to produce the desired surface (ie, compatible and smooth) of the dielectric adjacent to the phosphor layer using currently available ceramic materials. Thus, in an advantageous embodiment of the invention, the dielectric layer is formed as two layers, the first dielectric layer being formed on the rear electrode, preferably having a high dielectric strength, with the above dielectric constant value. Is set. The second dielectric layer becomes the surface adjacent to the fluorescent layer as described above.

  In an advantageous embodiment of the invention, the first dielectric layer is deposited by thick film technology (preferably screen printing) and then high temperature firing (preferably at a temperature below the melting point of all lower layers, preferably Is below 1000 ° C.). A paste comprising a ferroelectric ceramic, preferably a perovskite crystal structure, is an advantageous material if the paste composition allows firing at high firing temperatures. The second dielectric layer is preferably deposited by sol-gel technology and then high-temperature fired to obtain a smooth surface. The material used for the second layer preferably has a high dielectric constant (preferably 20 or more, more preferably 100 or more) and a thickness of 2 microns or more (preferably 2 to 10 microns). is there. Ferroelectric ceramics having a perovskite crystal structure are most advantageous.

  The present invention includes a first dielectric layer screen printed from lead niobate to a thickness of 30 microns and a second dielectric layer spin deposited from lead zirconate titanate as a sol to a thickness of 2 to 3 microns. Indicated by. The sol-gel layer was also shown by immersion to form multiple layers with an overall thickness of 6 to 10 microns. Lead lanthanum zirconate titanate was also shown as a sol-gel layer.

  The use of a two-layer dielectric is advantageous but not essential. Whereas the first dielectric layer is formed as a thick film having the required high dielectric strength and high dielectric constant, the second layer is not so limited. If the second layer has the desired compatible and smooth surface, it can be formed from many different materials than the one used in the first layer as a thin film. Much work has been done on changing the properties of the dielectric-fluorescent interface of EL laminates, such as improving chemical stability or implantation. Materials or deposition techniques that include these improvements can be used with the first and / or second dielectric layers of the present invention. Applying a third thin film layer further, for example by changing the surface of the second layer in selecting the material or deposition technique used in the first or second layer, or on top of the first or second layer Can be used.

  Laminates made according to the present invention show good luminous efficiency without breakdown at low operating voltages. Thick film and sol-gel deposition techniques that are advantageous for dielectric layers are generally simpler and less expensive than the thin film techniques previously described. Another advantage of the dielectric layer of the present invention is that the laminate incorporating the layer does not require a separate dielectric layer between the phosphor layer and the second electrode. However, such other dielectric layers can be included if desired.

Accordingly, the present invention applies a dielectric layer in an electroluminescent laminate of the type that includes a fluorescent layer sandwiched between a front electrode and a rear electrode. The rear electrode is formed on the substrate, and the fluorescent layer is separated from the rear electrode by a dielectric layer. The dielectric layer has a flat layer formed from a ceramic material. The dielectric strength of this ceramic material is about 1.0 × 10 ⁶ V / m or more, the dielectric constant which is the ratio of k ₂ / k ₁ is 50: 1 or more, and the dielectric layer has a ratio of d ₂ : d ₁ . Has a thickness in the range of 20: 1 to 500: 1. Furthermore, the dielectric layer is compatible with the fluorescent layer and has a surface adjacent to the fluorescent layer that is sufficiently smooth, and the fluorescent layer generally emits light uniformly at a predetermined excitation voltage.

The invention also relates to a method for producing an electroluminescent laminate of the type comprising a fluorescent layer sandwiched between a front electrode and a rear electrode. The rear electrode is formed on the substrate, and the fluorescent layer is separated from the rear electrode by a dielectric layer. The method of the present invention deposits the rear electrode by thick film technology and then fires the ceramic material. This ceramic material has a dielectric constant with a ratio of k ₂ / k ₁ of about 50: 1 or more, a dielectric strength of about 1.0 × 10 ⁶ V / m or more, and a ratio of d ₂ / d ₁ of about A dielectric layer having a thickness in the range of 20: 1 to 500: 1 is formed. The dielectric layer forms a surface adjacent to the phosphor layer. This surface is compatible with the phosphor layer and is sufficiently smooth that the phosphor layer generally emits light uniformly under a given excitation voltage.

  The invention also relates to a process for laser scribing a pattern into a flat laminate having at least one upper layer and at least one lower layer. This process irradiates the upper layer side of the laminate with a focused laser beam, which has a wavelength such that it is substantially not absorbed by the upper layer but absorbed by the lower layer, thereby At least a portion of the lower layer is removed directly, and the upper layer includes removing it indirectly throughout its thickness.

  In relation to the EL laminate, the upper layer is a transparent conductive material and light emitter, the lower layer is one or more of the dielectric layers, and the pattern is an electrode pattern of address lines arranged in parallel.

  The following definitions apply throughout the specification and the claims.

  Absorption occurs in the material when the amount of radiant energy coincides with an acceptable transition to a high energy state in the material, for example by promotion of electrons through the band gap for the material.

  Direct removal of material by the laser beam occurs when the main cause of removal is decomposition and / or due to absorption of the radiant energy of the laser beam by the material.

  Indirect removal of material by a laser beam occurs when the main cause of removal is evaporation due to heat generation in the material and when it is conveyed from an adjacent material that absorbs the radiant energy of the laser beam.

The present invention relates to an electroluminescent display panel that uses a through-hole connector to make an electrical connection from a flat electroluminescent laminate to the output side of one or more voltage drive elements of a drive circuit. The display panel
An electrolumine essence laminate formed on the back side of the substrate and having a front and rear set of tolerance address lines of known type;
A plurality of through holes formed in a substrate adjacent to the end of the address line;
A conductive path forming means for making an electrical connection between each address line and the voltage driving element of the driving circuit to each end of the address line through each of the through holes of the substrate;

  Advantageously, the electroluminescent laminate of the display panel comprises the thick film dielectric layer of the present invention. With this dielectric layer, a laminate can be formed from the rear substrate to the front side (in the viewing direction), which also allows a through-hole connector and a thick film circuit pattern for connecting the voltage driving element and the address line to the circuit. It becomes possible to form by an alternate combination of a manufacturing step and a manufacturing step for electroluminescence.

  Such a step cannot be easily achieved with conventional electroluminescent laminate structures. This is because the layer is deposited on the front display glass, which cannot withstand the temperature at which the thick film conductive paste is fired.

  According to the present invention, the voltage driving element or the entire driving circuit is formed on the back surface of the rear substrate. By using a through-hole connector, a more direct and reliable interconnection between the address lines and the drive circuit is obtained. There is no need for an inactive perimeter around the display panel (which was necessary in the prior art). This allows large displays to be combined from individual display panels and does not produce dark borders between modules.

  1 and 2 show an EL laminate 10 according to the present invention that combines two dielectric layers. The laminate 10 is formed on the substrate 12 from the back side. The back electrode layer 14 is formed on the substrate 12. As shown in the drawings, for application to a display, the back electrode 14 consists of a row of conductive address lines centered on the substrate 12 and spaced from the substrate edge. An electrical contact tab 16 protrudes from the electrode 14. A first thick dielectric layer 18 is formed on the back electrode 14 followed by a thinner second dielectric layer 20. In addition, a phosphor layer 22 is formed on the second dielectric layer 20 followed by a transmissive front electrode layer 24. Although the front electrode layer 24 is depicted as a solid in the drawing, for practical application to a display, this electrode layer is constituted by a row of address lines arranged perpendicular to the address lines of the back electrode 14. . The laminate 10 is encapsulated with a permeable seal layer 26 to prevent moisture from entering. An electrical contact 28 is provided on the second electrode 24.

  The EL laminate 10 is actuated by connecting an AC power source to the electrode contacts 16, 28. The EL laminate according to the present invention has the most applications in displays, but has applications as lamps or displays.

  Those skilled in the art will appreciate that additional intermediate layers may be provided in the laminate 10 without departing from the scope of the present invention.

  The method according to the invention for forming a double dielectric layer on one EL laminate will now be described together with advantageous materials and process steps.

  The laminate 10 is formed from the back surface to the front surface (display surface). The laminate 10 is formed on a suitable substrate 12. The substrate 12 is preferably a ceramic, which can withstand the high sintering temperatures (typically 1000 ° C.) used in the dielectric layer. Most preferred is alumina.

  A first back electrode 14 is deposited on the substrate 12. Numerous techniques and materials are known for wiring thin columns of address lines. Advantageously, the conductive metal address lines are screen printed with an Ag / Pt alloy paste using a photosensitive emulsion that can be washed off in the area where the paste is to be printed. Thereafter, the paste is dried and fired. Alternatively, the back electrode 14 can be formed of another noble metal such as gold, or other metals such as chromium, tungsten, molybdenum, tantalum or alloys of these metals.

The first dielectric layer 18 is deposited on the back electrode by well-known thick film techniques. In order to produce a dielectric constant higher than that of the phosphorous layer 22, the first dielectric layer 18 is preferably made from a ferroelectric material, most preferably from one having a perovskite crystal structure. This material has a minimum dielectric constant of 500 over the appropriate operating temperature for the laminate, typically over 20 ° C to 100 ° C. Even more advantageously, the dielectric constant of the first dielectric layer material is 1000 or more. Illustrative materials for the first dielectric layer 18 are PbnbO ₃ , Batio ₃ , SrTiO ₃ and PbTiO _3, with PbNBO ₃ being particularly preferred.

  One skilled in the art will understand when selecting a ceramic material for the first dielectric layer 18 (ie, an electrically insulating member having a sufficiently high melting point to prepare another layer of the laminate). In addition, a material known to have a high dielectric constant and a high dielectric strength is selected. These are inherent properties of the material, but values are generally defined for bulk materials that exist in dense and transparent shapes. These properties can be varied depending on the deposit technique used. With respect to the dielectric constant of the material, a thick film deposition technique followed by high temperature sintering (within the range of about 1 micron to about 2 microns) with the aim of not lowering the dielectric constant significantly below that of the starting material. ) Large particle size and high transparency in a dense structure are generally maintained. Similarly, high dielectric strength can be obtained by using thick film deposition technology. However, the dielectric strength of the layer should eventually be measured by applying an operating voltage to the finished laminate.

  The thick film deposition technique is conventionally known as described above. In such a technique, the dielectric material is deposited on the back electrode 14 with a desired thickness in a generally uniform range. Thick film deposition technology is frequently used in the manufacture of electronic circuits on ceramic substrates. Screen printing is the most preferred technique. Commercially available dielectric pastes can be used with the recommended sintering steps performed by the paste manufacturer. The paste should be selected or formed to allow high temperature sintering, typically about 1000 ° C. However, similar results can be obtained with other techniques. An alternative thick film technique is to use a dielectric as a “green tape” so that wiring on the back electrode 14 is possible. The green tape has a polymerized matrix dielectric powder that can be burned during a subsequent sintering process. Prior to sintering, the tape is flexible and can be spread flat on the electrode layer 14 and pressed. One possible advantage of green tape on a screen printed dielectric is that if it is burned, it can be somewhat more dense with fewer holes. Currently, green tape dielectrics are not readily available. Dielectric thick film paste can also be spread flat on back electrode layer 14 or applied with a doctor blade. Increasingly complex techniques such as electrostatic deposition of the dielectric powder and subsequent sintering that occurs immediately before the powder loses its electrostatic charge can also be used.

  As shown, the first dielectric layer 18 is preferably screen printed with a paste. In order to achieve a slight porosity, high crystallinity and minimal disintegration, deposits in multiple layers and subsequent sintering at high temperatures are advantageous. The sintering temperature depends on the particular material used, but does not exceed the temperature that the back electrode 14 or substrate 12 can withstand. For most electrode materials, typically a temperature of 1000 ° C. is the maximum. The thickness of the first dielectric layer 18 varies depending on the dielectric constant of this layer and the dielectric constant and thickness of the phosphorescent layer 22 and the second dielectric layer 20. In general, the thickness of the first dielectric layer 18 is in the range of 10 to 300 microns, preferably in the range of 20 to 150 microns, more preferably in the range of 30 to 100 microns. .

In general, the criteria for determining the thickness and dielectric constant of the dielectric layer should be calculated so that adequate dielectric strength occurs at the minimum operating voltage. These criteria are interrelated as described below. A typical thickness range (d ₁ ) between about 0.2 and 2.0 microns is provided for the phosphor layer, and a dielectric constant range (k ₁ ) between about 5 and 10 for the phosphor layer. And a dielectric strength range of about 10 ⁶ to 10 ⁷ V / m for the dielectric layer, a typical thickness (d ₂ ) and dielectric constant (K ₂ ) for the dielectric layer of the present invention The following equations and calculations can be applied to determine the value of: If these typical ranges are to be changed meaningfully, these equations and calculations can be used as guidelines for determining the values of d ₂ and k ₂ without departing from the scope of the present invention. it can.

The voltage V applied to a double layer having one uniform dielectric layer and one uniform non-conductive phosphor layer sandwiched between two conductive electrodes is defined by Equation 1:
V = E ₂ * d ₂ + E ₁ * d ₁ (1)
In this case, E2 is the electric field strength in the dielectric layer, E1 is the electric field strength in the phosphor layer, d ₂ is the thickness of the dielectric layer, d ₁ is the thickness of the phosphor layer.

  In these calculations, the electric field direction is perpendicular to the intervening region between the phosphorescent layer and the dielectric layer. Equation 1 applies as long as a voltage lower than the threshold voltage is applied. At this threshold voltage, the electric field strength in the phosphor layer is high enough that the phosphor layer begins to breakdown electrically and the device begins to emit light.

According to electromagnetic theory, the component of electrical displacement (electric flux density) D perpendicular to the intervening region between two insulating materials having different dielectric constants is continuous over the intervening region. This electrical displacement component in a material is defined as the product of the dielectric constant and the electric field component in the same direction. From this relationship, Equation 2 is derived for the intervening region in the double layer structure:
k ₂ * E ₂ = k ₁ * E ₁ (2)
In this case, k ₂ is the dielectric constant of the dielectric material, and k ₁ is the dielectric constant of the phosphorescent material.

Formulas 1 and 2 can be synthesized to give Formula 3:
V = (k ₁ * d ₂ / k ₂ + d ₁ ) * E ₁ (3)
In order to minimize the threshold voltage, the first term of Equation 3 needs to be reduced according to practical use. In order to maximize the light emitted by the phosphor layer, the second term is defined by the requirement of the phosphor layer thickness selection. In determining these values, the first term is selected to be one tenth the size of the second term. Substituting this condition into Equation 3 yields Equation 4:
d ₂ / k ₂ = 0.1 * d ₁ / k ₁ (4)
Equation 4 gives the ratio of the thickness of the dielectric layer to its dielectric constant with respect to the properties of the phosphorescent layer. This thickness is uniquely determined from the requirement that the dielectric strength of the insulating layer be sufficient to hold the entire applied voltage when the phosphor layer conducts above the threshold voltage. The thickness is calculated using Equation 5:
d ₂ = V / S (5)
In this case, S is the dielectric strength of the dielectric material.

By using appropriate values for the above equations and d ₁ , k ₁ , S, the dielectric layer thickness and dielectric constant ranges described in the present specification and claims are obtained.

  As described above, the first dielectric layer 18 has a sufficiently smooth surface adjacent to the phosphorescent layer (i.e., the subsequently deposited phosphorescent layer generally emits uniformly at a predetermined excitation voltage). If it has a sufficiently smooth surface) and is compatible with the phosphor layer 22, the second dielectric layer 20 is not necessary. In general, it is sufficient if the surface relief does not change more than about 0.5 microns over about 1000 microns (which is approximately equal to one pixel width). It is even more preferable if the surface undulation is 0.1 to 0.2 microns at this interval. If the first dielectric layer 18 has a sufficiently smooth surface but does not have the desired compatibility with the phosphorescent layer 22, then another layer of material (preferably a dielectric) is preferred for compatibility. Layer, but need not be) may be added, for example, by thin film technology.

  If a second dielectric layer 20 is required, this layer is created on the first dielectric layer. The second dielectric layer 20 can have a dielectric constant that is less than the dielectric constant of the first dielectric layer 18 and is typically thinner (preferably greater than 2 microns and more preferably 2-10. Micron). The desired thickness of the second dielectric layer is generally a function of smoothness, i.e. this layer can be made as thin as possible if a smooth surface is obtained. In order to obtain a smooth surface, a sol-gel deposition technique is preferably used, followed by high temperature sintering. The sol-gel deposition technique is well known in the art, see for example "Fundamental Principles of Sol Gel Technology", R. W. Jones The Institute of Metals, 1989. In general, the sol-gel process allows the material to be mixed at the molecular level in the sol before being removed from solution as a colloidal gel or polymerized polymer network while still retaining the solvent. Removal of the solvent leaves a high level of dense porosity solid. Thus, the value of the surface free energy is increased, and the solid can be sintered and increased in concentration at a lower temperature than is done using most other techniques.

  The sol-gel material is deposited onto the first dielectric layer 18 to obtain a smooth surface. This sol-gel process makes it possible to fill pores on the sintered thick film layer in addition to producing a smooth surface. Spin deposition or immersion is most preferred. These are techniques that have been used in the semiconductor industry for many years, mainly in photolithography processes. In the case of spin deposition, the sol material is dropped onto the first dielectric layer 18 that spins at high speed—typically several thousand revolutions per minute. If desired, the sol can be deposited in several steps. The thickness of layer 20 is controlled by changing the viscosity of the sol-gel and by changing the spin rate. After spinning, a thin layer of wet sol-gel is produced on the surface. In order to produce a ceramic surface, the sol-gel layer 20 is generally sintered at temperatures below 1000 ° C. The sol can also be deposited by immersion. The surface to be coated is immersed in the sol and then withdrawn at a constant rate—usually very slowly. The layer thickness is controlled by changing the viscosity of the sol and the withdrawal speed. Furthermore, the sol may be screen printed or spray coated, but with these techniques it is relatively difficult to control the layer thickness.

  The material used for the second dielectric layer 20 is preferably a ferroelectric ceramic material, which preferably has a perovskite crystal structure in order to produce a high dielectric constant. This dielectric constant is preferably similar to the dielectric constant of the first dielectric layer in order to avoid voltage fluctuations in the two dielectric layers 18, 20. Nonetheless, the thinner dielectric layer used in the second dielectric 20 can use a dielectric constant that is about 20 less, but is preferably greater than 100. Illustrative materials include zirconate-lead titanate (PZT), lanthanate-zirconate-lead titanate (PLZT), and Sr, Pb and Ba titanates used in the first dielectric layer 18. In this case, PZT and PLZT are most preferred.

  In order to produce a smooth ceramic surface suitable for the deposition of the next layer, PZT or PLZT is advantageously obtained by spin deposition and subsequent sintering at temperatures below about 600 ° C. As deposited.

  The next layer to be deposited is typically the phosphor layer 22, but, as described above, for the purpose of further improving the intervening region with the phosphor layer, within the framework of the present invention the second dielectric layer 20 Further layers can be provided on top. For example, a thin film layer of a material known to provide good injectability and compatibility can be used.

  The phosphor layer 22 is deposited by a well-known thin film deposition technique such as vacuum deposition or sputtering using an electron beam evaporator. A preferred phosphorescent material is ZnS: Mn, although other phosphors that emit light of different colors are also known. The phosphor layer 22 typically has a thickness of about 0.5 microns and a dielectric constant of about 5-10.

  A separate transmissive dielectric layer over the phosphor layer 22 is not required, but may be provided if desired.

  The front electrode layer 24 is deposited directly on the phosphor layer 22 (another dielectric layer, if provided). This front electrode is transmissive and is preferably produced from indium tin oxide (ITO) known in thin film deposition techniques such as vacuum evaporation in electron beam evaporators.

  The laminate 10 is typically annealed and then sealed with a sealing layer 26 such as glass.

Advantageous laminates with typical thickness values according to the present invention are as follows from back to front:
Substrate layer Alumina back electrode Ag / Pt address line 10 micron first dielectric layer Lead niobate 30 microns second dielectric layer Zirconate-lead titanate 2 micron phosphorescent layer ZnS: Mn 0.5 micron front electrode ITO 0.1 Micron Seal Layer Glass 10-20 microns For large EL displays, the layer thickness can be varied. For example, the thickness of the sol-gel layer is typically increased by about 6-10 microns to obtain the desired smoothness. Similarly, the thickness of the ITO layer can be increased to 0.3 microns for large displays.

  According to the invention, the connection between the front and back address lines of the electroluminescent laminate and the voltage drive circuit is preferably made by penetrating through holes in the back substrate. Most preferably, the EL laminate has a thick dielectric layer of the present invention—although this is not required.

  The voltage drive circuit has a voltage drive component (typically referred to as a high voltage drive chip). In order to selectively excite the pixels in response to the video input signal, the output side of this component is connected to the individual row and column address lines of the back and front electrodes. Voltage drive circuits and components are generally known in the prior art. To illustrate the present invention, a through-hole connection is provided for a well-known packaged high-voltage drive chip, which is mounted on the back substrate by a well-known reflow soldering technique. Surface mounted. This type of high voltage drive chip is known as a conventional symmetric pulse drive type and asymmetric pulse drive type.

  However, as those skilled in the art will realize, special driver circuits or driver components can be modified, and as such, naturally the pattern of the through-hole and the circuit pattern provided to connect to the driver circuit. May have an effect. As an example, the present invention can mount the entire driver circuit or only a part thereof on the rear substrate. For example, instead of using a high voltage package chip, a bare silicon die (chip) can be used on the substrate using conventional die attach methods, and the chip can be mounted on the substrate using conventional wire bonding techniques. Can be connected to the circuit. In this case, the driver chip occupies only a small area on the substrate, and the entire driver circuit can be arranged on the substrate. As a result, the ultra-thin display panel can be interfaced directly to the video signal and directly connected to a DC power source. Such a display is useful in ultra-thin portable products that require a display. Of course, the ability to mount the driver circuit on the back side of the board is applicable to any size display, and a relatively large display provides more space for providing drive circuitry directly on the back side of the board. be able to.

  The circuit connection state of the present invention is shown in FIGS. As described above, special through holes and circuit patterns are provided for mounting the high voltage driver chip 30 on the opposite side of the rear substrate for purposes of illustration. A special chip selection is for Supertex HV7022PJ for connection to column address line 14 and Supertex HV8308PJ and HV8408PJ (Supertex Corp., Sunnyvale, Calif.) For connection to row address line 24. The latter two chips differ in that one lead pattern is a mirror image of the other lead pattern.

  Referring to the figure, the EL laminate 10 is advantageously (but not necessarily) made up of the two dielectric layers 18 and 20 of the present invention, and thus from the front side of the rear substrate 12. It is constructed toward the viewing side. The rear substrate 12 is perforated with through-holes 32 so that the pattern is such that the substrate 12 and the through-holes 32 are closest to both ends of the address lines 14, 24 (which will be formed later). Has been. Alternatively, additional through holes can be provided along the address lines with a predetermined spacing. This is useful for making connections to the high resistance front ITO address lines. The pattern of FIG. 4 is for connection to the EL laminate 10 on the rectangular substrate 12, and column address lines (rear electrodes) 14 are provided along the relatively long dimension on the rectangular substrate 12, and row address lines are provided. A (front electrode) 24 is provided along a relatively short dimension.

  The through hole 32 is preferably formed by a laser. The hole 32 is typically extended on one side due to the nature of the laser drilling process, which side is on the back side of the substrate 12 to facilitate the passage of conductive material through the hole. is there.

  The substrate 12 used in the EL laminate should be such that the temperature encountered in subsequent processing steps can be reduced. Typically, the substrate used is sufficient to firmly support the laminate and has a temperature of 850 ° C. or higher to withstand subsequent firing and sintering for thin film paste and sol-gel materials. It is stable against. Therefore, the substrate should be impermeable to laser light, so that the through holes 32 can be formed by laser drilling. Finally, the substrate should provide good adhesion of the thin film paste used in subsequent steps. Crystalline ceramic materials and non-conductive glassy materials are used. Alumina is particularly advantageous.

  A circuit pattern 34 of conductive material is printed on the rear side of the substrate 12 in the pattern shown in FIG. In this step, the conductive material is drawn through the through hole 32 as described above. The circuit pattern 34 on the rear side surface of the substrate 12 includes a rear connector pad 36 around each of the through holes 32, a chip connector pad 38 for outputting a high-voltage driver chip (not shown), and a drive circuit (not shown). Connector pads (not labeled) for connection to the rest of the connector pads, and electrical leads (not labeled) between multiple connector pads as shown.

  The conductive material is advantageously a conductive thin film paste applied by screen printing.

  To form a conductive path through each through hole 32, the front side of the substrate 12 is evacuated while the circuit 34 is printed on the back side. This is advantageously achieved by placing the substrate 12 on a vacuum table having a master plate, the master plate having holes drilled in the pattern of FIG. 4 between the substrate 12 and the vacuum. is doing. Each hole in the master plate is aligned and is somewhat larger than the hole in the substrate 12. To ensure that the vacuum is applied uniformly, no vacuum is applied until the circuit is printed. The vacuum is continued until the conductive material is pulled through to the front side of the substrate. At that point, a small amount of conductive material is pulled through the front side of the substrate 12 to cover the through-hole wall. The thin film paste is then fired according to known procedures.

  Following this step, the circuit pad reinforcement pattern 42 is advantageously (but not necessarily) printed as shown in FIG. As with the conductive material, the printing and firing steps are continued.

  Column address lines 14 and connector pads 40a, 40b are then formed on the front side of substrate 12, preferably by screen printing a thin film conductive paste such as a silver / platinum paste. The address line pattern is shown in FIG. 6 and has a row extending along the length of the substrate 12 and ending with a front (row) connector pad 40a. During this same step, the front (row) connector pad 40b is provided to finally connect the row address line to the drive circuit via the through hole 32. The conductive paste is advantageously extracted through the through-hole 32 as described above, with a vacuum being applied from the rear circuit side of the substrate.

  The means for forming the conductive path through the through-hole 32 is described in detail above because it is formed from a thin film conductive paste, but the conductive paste can be used for electroplated through-holes as known in the prior art. Or through the formation of through holes by non-electric plating, thus providing an electroplated material that is properly attached to the substrate, and a subsequent layer on the plate conductor To be attached.

  The thin film dielectric layer 18 of the present invention is then advantageously formed and fired as described above.

  The rear circuit surface of the substrate is then advantageously sealed using a rear sealant 44, in which case, for example, by screen printing using a thin film glass paste, the connector pads for mounting high voltage driver chips, and It is left exposed to attach the connector pin 45 to the rest of the driver circuit (not shown). The sealing pattern is shown in FIG.

  The EL laminate is then complemented by a sol-gel layer 20, a phosphor layer 22 and a front row address line 24. The pattern for the front row address line 24 is shown in FIG. This consists of parallel rows across the thickness of the substrate 12 terminating in the vicinity of the front (row) connector pads 40. Optionally, an electrical interconnect 46 between the row address line 24 and the front (row) connector pad 40 is provided for reliable electrical connection purposes. These are advantageously formed by printing a conductive material such as silver through a shadow mask in the pattern shown in FIG.

  The aforementioned front sealing layer 26 is provided for the purpose of preventing moisture permeation.

According to the present invention, the front ITO address lines 24 of the EL laminate 10 are preferably formed by laser drawing. This laser writing technique is shown in relation to the advantageous EL laminate 10 of the present invention. However, it should be understood that laser lithography techniques are more widely applied when patterning planar laminates having upper and lower layers. In this regard, the ITO and phosphorus layers 24, 22 have an upper layer that does not substantially absorb laser light. Further, the thick film rounded niobium dielectric layer 18 and the zirconate titanate sol-gel layer 20 have a lower layer that absorbs laser light. Other representative materials include SnO ₂ and In ₂ O ₃ as transparent (translucent) conductors.

  Usually, in the idea of the present invention, the upper layer is a material that transmits visible light, and the lower layer is a material that does not transmit visible light. Therefore, the lower material is directly perforated and the upper layer is indirectly perforated. In this case, drilling is performed using a laser beam having a wavelength in the visible region or in the infrared region of the electromagnetic spectrum. This laser drilling method is widely used in semiconductors, liquid crystal displays, solar cells and EL displays.

  Material for the purpose of controlling the accuracy and resolution of laser writing (depth of cut and width), to avoid explosive deflaking of layers, and to minimize interdiffusion between layers The prescribed characteristics and layer thickness should be observed.

  The following relationship is maintained for the two-layer laminate:

Where α _u T _u > α _o T _o ,
α _u = absorption coefficient of the lower layer,
α _o = upper layer absorption coefficient,
T _u = thickness of the lower layer,
T _o = the upper layer thickness,
It is more advantageous if the product α _{u Tu} is significantly larger than the product α _o T _o .

When a plurality of upper transparent layer and / or a plurality of opaque layer is provided, the sum of products alpha _u T _u for each layer, should be greater than the sum of the product alpha _o T _o for each of the layers _Yes , that is, Σ _i α _ui T _ui > Σ _i α _oi T _oi
When the above function is maintained, the steps of the present invention should puncture only a portion of the lower layer directly, without cutting through its entire thickness, It should be drilled indirectly through the thickness.

  Explosive unlaminate may occur if heat or vapor pressure is formed in the lower layer before the upper layer can soften and / or vaporize by indirect perforation. Therefore, the material in the upper layer should melt and vaporize at a lower temperature than the temperature at which the material in the lower layer melts and vaporizes.

  For the purpose of improving the cutting performance with high resolution, it is advantageous if the thermal conductivity of the material in the lower layer is smaller than that of the material in the upper layer. The thermal conductivity of both layers is selected from the area being perforated so that no significant heat is dissipated while this area is being irradiated with the laser light.

  In order to avoid interdiffusion of substances between the layers, the diffusion time for this process should be longer than the time that the area to be drilled is irradiated with the laser beam.

  The aforementioned properties are known for the materials and can be informed in advance which materials are suitable for the laser writing process of the present invention.

  Laser cutting resolution, explosive non-laminate and interdiffusion are also affected by the energy and scanning speed of the laser beam. However, if the aforementioned relationship is observed, these other laser conditions are normally maintained, and these other laser conditions are controlled and achieved to achieve the desired result of direct and indirect drilling. Change is possible.

  Laser beams that supply a laser beam having a wavelength in the visible or infrared region are known. Carbon dioxide laser, argon laser, and YAG laser are examples. All lasers have a wavelength greater than 400 nm. A pulsed wave laser or a continuous wave laser can be used. The latter is advantageous for creating sharp high resolution cuts. The laser beam is focused by a suitable lens device. The purpose is to ensure sufficient local density for complete removal of the upper layer. Usually, the energy density of the laser beam is set so that the groove to be cut is sufficiently larger than the thickness of the upper transparent layer. When the transparent layer includes electrode address lines, this ensures that the address lines are clearly defined and electrically insulated.

  Drawing is performed by moving the laser beam with respect to the material to be drawn. More advantageously, this is done by placing the material to be drawn on an xy coordinate table that is movable relative to the laser beam.

  For drawing the address lines, a table that is movable in the x-direction (ie perpendicular to the address lines to be written) is advantageous, and the laser beam is movable in the y-direction, ie along the address lines.

  The material that is vaporized or decomposed during laser writing can be removed from the material to be drawn by a vacuum provided in the vicinity of the laser beam.

  An advantageous EL laminate 10 according to the invention, a thin layer 24 of indium tin oxide, is deposited on the phosphor layer 22 by known methods. A vacuum deposition method for depositing ITO or a method for depositing ITO is shown in US Pat. Nos. 4,568,578 and 4,849,252. It is also possible to use tin oxide doped with a material other than ITO, for example with fluorine. An optically transparent dielectric layer can be provided between the ITO and the phosphor layers 24 and 22. An advantageous sol-gel layer 20 of PZT and a thick niobium thick film dielectric layer are provided below the phosphorus layer. As described above, the EL laminate 10 is formed in the reverse sequence of the conventional TFEL apparatus. This leaves the ITO layer 24 and the phosphorous layer 22 suitable for laser writing according to the present invention as the upper transparent layer above the lower opaque dielectric layers 18, 20, as is conventional.

  Each row address line 24 is drawn with a laser as described above. The laser beam directly removes at least a portion of the sol-gel layer 20 and a small portion of the thick lower dielectric layer 18 and indirectly removes the ITO and phosphor layers 24, 22 over their thickness. This leaves a reliable isolation gap between adjacent address lines.

  The row address line 24 is connected to the drive circuit described above. Specifically, due to the advantageous through-hole connection described above, the electrical interconnect 46 (prior to laser drawing) eventually forms an address line by depositing silver in the pattern shown in FIG. It is formed at a position overlapping with a part of the ITO layer.

  Next, address lines are drawn as described above.

  The completed EL laminate can be sealed, as described above, by spraying a protective polymer seal on the front visible surface or by adhering a glass plate to the front surface.

  By using indirect perforations for drawing transparent conductor material, several advantages are obtained. Rather than an ultraviolet pulse laser with a high instantaneous output, a very low energy connected wave laser that emits light in the visible region can be used. This laser not only reduces cost, but also creates a smoother line on the deleted notch. This is particularly important for high resolution EL displays. Direct drilling of transparent material requires significantly higher instantaneous laser energy that delivers the energy required for drilling in a time short enough to prevent heat from spreading from the area where the drilling takes place. In prior art attempts to directly drill a transparent conductor provided on a transparent substrate, only a small portion of the laser energy is directly supplied by the transparent conductor material; the majority of light is transparent to both Through different layers. In many cases, indirect perforations minimize the problem of interdiffusion between layers. This is because the heat for vaporizing the transparent layer is generated from the bottom of the transparent layer. This facilitates removal of the perforated material to the exterior rather than diffusion of the material into the underlying layer. This is important to maintain the quality of the dielectric and phosphor layers in the EL display.

The invention is further illustrated by the following variant embodiments.
Example 1
This example shows that simple printing of a barium titanate thick film layer (a material used as a ceramic sheet in Miyata et al.) Depends on electrical breakdown under conditions. .

  A single pixel electroluminescent device was formed on an alumina substrate (5 cm square, 0.1 cm thick) obtained from Coors ceramic (Grand Junction, Colorado, USA). A back electrode layer is in contact with the substrate in the center and away from the edge. The material used is a silver / platinum conductor. In electronics, this is printed as an address line as in the past. In detail, Ceralloy # C4747 (available from Cermalloy, Conshohocken, Pa.) Was screen printed as a thick film paste with a 320 mesh stainless steel screen and coated with a photosensitizer. This photosensitizer was irradiated with ultraviolet rays through a photomask. Its purpose is to expose areas of the photosensitizer that are maintained for printing. Unexposed photosensitizer was removed by dissolving in water. The paste is printed through the screen at this point. The remaining photosensitizer was then further cured by additional light irradiation. The printed paste was dried in an oven at 150 ° C. for several minutes and heated in air in a BTU model TFF142-790A24 belt furnace with a temperature profile recommended by this paste manufacturer. The maximum process temperature was 850 ° C. The resulting thickness of the heated electrode conductor layer was about 9 microns.

  The dielectric layer is formed on the electrode layer as follows. Barium titanate (ESL # 4520-ElEctroscience Laboratories, available from King of Prussia, Pennsylvania, dielectric constant 2500-3000) is printed in a square pattern through a 200 mesh screen. As a result, everything was covered except for the electrical contact pads in the electrode wires. The printed dielectric paste was heated in air in a BTU furnace with a temperature profile recommended by the manufacturer (maximum temperature 900-1000 ° C.). The resulting heated dielectric thickness is in the range of 12-15 microns. The second and third layers of dielectric were then printed and heated on the first layer in the same manner. The combined thickness of the three printed and sintered dielectric layers is 40-50 microns.

  A phosphorus layer was deposited directly onto the dielectric layer by known thin film techniques. Specifically, a 0.5 micron thick layer of copper sulfide doped with 1 mole percent of manganese is deposited onto the dielectric layer using a UHV Instruments Model 6000 electron beam deposition apparatus. These layers are heated under vacuum in a deposition apparatus and maintained at a temperature of 150 ° C. during deposition for about 2 minutes.

  The phosphor layer is coated with a 0.5 micron layer of transparent electrical conductor made of indium tin oxide. This layer is deposited by known thin film deposition techniques, in particular using an electron beam evaporation apparatus at 400 ° C. under vacuum.

  The laminate is then treated for 15 minutes in air at 450 ° C. for the purpose of annealing the indium phosphorus oxide conductor layer. Indium brazing contacts are provided on the ITO layer. This element is sealed with a silicon sealing material (Silicone Resin Clear Lacqver, cat. # 419.MG Chemicals).

  The device is tested by applying a DC voltage between the two electrodes. It is observed whether this device will fail by applying a voltage that causes electrical breakdown of the dielectric layer in the region immediately adjacent to the contact to indium tin oxide.

It is assumed that this device failure occurred because the dielectric layer did not form the smooth surface required for the phosphorous layer. Small cracks may be observed on the surface. However, this may be due to the presence of an obstructing material in commercially available dielectric pastes. Therefore, barium titanate is not an indicator that it cannot be used as a single or first dielectric layer according to the present invention.
Example 2
This example shows that a screen-printed dielectric layer comprising a paste comprising a round niobate--a material known to have a higher dielectric constant and lower sintering temperature than barium titanate--is suitable. It gives a dielectric constant but does not emit light.

  The element is configured in the same manner as in the first embodiment. However, it has a dielectric layer composed of a dielectric paste of niobate, Ceramicloy # IP9333 (dielectric constant is about 3500, thickness is the same as in Example 1). When this device was tested, dielectric breakdown did not occur when a DC voltage of 400V was applied. However, no light was emitted even when an AC voltage was applied.

The fact that it does not emit light is caused by a compatibility problem in connection with the phosphorus layer. This should not be an indication that round niobate cannot be used as a single or first dielectric layer according to the present invention.
Example 3
This example shows a two-layer dielectric constructed in accordance with the present invention. A first dielectric layer of round niobate (as in the second embodiment) and a second dielectric layer of round zirconate. The desired luminescence was achieved.

  The same element as in Example 2 is configured. However, it has the additional step of depositing a rounded zirconate (PZT) layer onto a printed and heated dielectric layer using a sol-gel process before the phosphorus layer is deposited. The sol was prepared as follows. Acetic acid is dehydrated at 105 ° C. for 5 minutes. 12 grams of acetic acid round was melted into 7 ml of 80 ° dehydrated acid in order to form a colorless solution. The solution was cooled and 5.54 g of propoxyzirconium was mixed into the solution to form a blue-yellow solution. The solution was left at 60 ° -80 ° for 5 minutes, after which 2.18 g of isopropoxylated titanium was added with stirring. The resulting solution remains. Stirred in an ultrasonic bath to ensure that the solute melts. Then 1.75 ml of a 4: 2: 1 solution of ethylene glycol, propanol and water was added for the purpose of forming a stable sol. More ethylene glycol was added to adjust the viscosity to the desired value for spin coating or dipping prior to coating. The prepared dielectric layer was spin coated or dipped with sol. In the case of spin coating, the sol was dripped onto the first dielectric layer rotating in a horizontal plane at 3000 rpm. In the case of dipping, a higher viscosity sol was used. The substrate was pulled up from the sol at a rate of 5 cm / min for the dipping process. The resulting coated assembly was then heated in air in a furnace for 30 minutes at a temperature of 600 ° C. to convert the sol to PZT. The thickness of the PZT layer was about 2-3 microns. The surface of the PZT layer was observed to be significantly smoother than the surface of the first dielectric layer that was screen printed and sintered.

  Following deposition of the PZT layer, a phosphorous layer and a transparent layer are deposited as in Example 1.

The finished laminate was produced with properties similar to or better than those reported by Miyata et al. In luminescence-voltage characteristics. The threshold voltage for minimum brightness for the display was 110V. The luminous intensity at 50 V above the threshold (ie 160 V, 60 Hz) was 57 foot lamber.
Example 4
In this embodiment, changes in the thickness of the dielectric layer affect the operating voltage and display brightness.

  The display was configured as in Example 3. The difference was that only two screen printed dielectric layers were deposited instead of three. The thickness of the first dielectric layer was correspondingly reduced to 25-30 microns.

A threshold voltage for the minimum luminance of 70 V (110 candles in Example 3) was expected from theoretical considerations. The brightness at 50 V above the threshold was also reduced to 35 foot lambertes (57 candlelight foot lamber, Example 3).
Example 5
This embodiment shows an advantageous embodiment of connecting the EL laminate row and column address lines to a drive circuit using through holes.

  The addressable EL display is constructed using the same sequence of layer deposition shown in Example 3. The substrate was rectangular alumina with a thickness of 0.025 inches. The alumina was obtained from Coors Ceramics (Grand Junction, Colorado, USA) having dimensions of inches long and 2 inches wide. The substrate was drilled with a 0.006 inch diameter through hole using a carbon dioxide laser in the pattern shown in FIG. The substrate was inspected to ensure that all holes were clear. The hole was found to be about 0.008 inch in diameter on the side facing the laser and about 0.006 inch on the opposite side. The side with the larger hole was chosen as the back side of the substrate for the purpose of facilitating the insertion of the conductive material into the through hole.

  Following this, the circuit pattern shown in FIG. 5 was printed with a 325 mesh stainless steel screen using Cermalloy # 4740 silver platinum paste. During this printing process, the substrate is centered with a master plate having 0.040 inch holes drilled in the same pattern as shown in FIG. 4 and pulls the conductive pace through the through holes in the substrate. Therefore, a vacuum is applied under the master plate (that is, the entire surface as viewed from the paper side of the substrate). This step formed the circuit pattern of FIG. 5 with conductive paths through each of the through holes in the substrate. In order to ensure uniformity in the application of the vacuum, the vacuum is applied only after the substrate is printed. This part ensures that the through hole is filled.

  Following printing, the substrate is heated in a BTU model TFF142-790A24 with a temperature profile advanced by the paste manufacturer. The maximum temperature was 850 ° C.

  Following this step, the circuit reinforcement pattern shown in FIG. 7 is printed and the circuit back side of the substrate is heated (using the same Cermalloy conductive paste). This step makes the circuit pattern thicker in certain areas where electrical connections are to be made substantially.

  The column address lines and front column and row connector pads were then screen printed onto the front side of the substrate. The lines extended over the length of the substrate to the column connector pads shown in FIG. The row connector pads shown in FIG. 5 are printed in this same step. Column address lines and connector pads were formed from the same conductive paste (Cermalloy # 4740) using the same printing and heating conditions. The substrate was positioned on the same master plate by the through hole of FIG. 4, and a vacuum was applied from below to draw the conductive paste through the through hole to the back side of the substrate. The thickness of the heated electrode layer was about 8 micrometers. 52 address lines were formed per inch, and the total number of address lines was 68. This part was inspected to ensure that the through hole was filled.

  A three layer dielectric paste (Cermalloy # IP9333) was printed and heated as shown in Example 3 to form a dielectric layer having a thickness of about 50 micrometers.

  The circuit back side of the substrate was then sealed. Thick film glass paste (Heraeus IP9028, Heraeus-Cermalloy, Conshohocken, Pa.) Was screen printed using a 250 mesh screen in the pattern shown in FIG. Connector pads for connection to the high voltage drive chip and other drive circuits were not covered. The glass seal layer was then heated at a maximum temperature of 700 ° C. in a BTU belt furnace using a temperature profile recommended by the manufacturer.

  During the aforementioned heating, the substrate was supported on a ceramic material member in order to avoid contact between the printed material on the circuit side and the furnace belt.

  The sol-gel layer is formed substantially by immersion as described in Example 3. Three or four sol-gel layers are typically used. For example, it is used with a pooling rate of 10-25 sec / in from a blend having a viscosity of approximately 100 cP measured by a falling ball viscometer. Between the immersion layers, the sol-gel is dried at 110 ° C. for 10 minutes. The vacuum chuck is performed over the active area of the laminate, and the sol-gel is washed out of the remaining area. The layer is then sintered in a belt furnace at about 660 ° C. for 25 minutes. This achieves a total sol-gel thickness of between 3 and 10 μm. This is carried over by the phosphor layer of Example 3 doped with 1% manganese and using 0.5 to 1.0 μm thick zinc sulfide.

  The address line rows are deposited with indium-tin-oxide as previously described in Example 3 (pattern shown in FIG. 9). There are about 52 address line rows per inch, and there are 256 rows in total. The spacing between lines is 0.001 inch and the line width is 0.019 inch (center to center).

  As in the pattern shown in FIG. 10, silver is deposited on the substrate through the hole conductor to form the electrical connection of the row of address lines to the row connector pad through a shadow mask.

  The visible surface of the laminate is sealed with a silicone sealant. This silicone sealant is sprayed over the entire front surface of the display. This sealant contains M.I. G. Chemical silicon resin clear lacquer, Cat # 419 is used.

The entire display is inspected by connection to a pulse generator that provides a 60 Hz 160 V square wave signal across a pair of on-circuit column and row pads on the back side of the substrate. Each pixel of the display is based on individual illumination and has the same consistent intensity as measured in Example 3 when supplied with voltage. Functionally defective pixels are found out of all 17408 pixels.
Example 6
This example shows an advantageous embodiment of a laser in which the indium-tin-oxide-address lines of the EL laminate of the present invention are scribed.

  The matrix display that can be called by address is constructed on a ceramic substrate used in the following process. This ceramic substrate is 0.025 inches thick, has a rectangular length of 6 inches long and 2 inches wide and is obtained from Coors Ceramics (Grand Junction, Colorado, USA). A hole having a diameter of 0.006 inch is formed on the substrate using a carbon dioxide laser. This pattern is shown in FIG. Some of these holes are inspected to ensure that all these holes are penetrated.

  Following this step, the circuit pattern shown in FIG. 5 is printed on a 325 mesh stainless steel screen (which uses Cermalloy (Conshohocken Pnsylvania, USA) # 4740 silver platinum paste). ). During the printing process, the substrate is arranged on the master plate. The master plate has a 0.04 inch hole opened with the same pattern as the substrate to facilitate the supply of vacuum to the substrate hole during printing. The vacuum absorbs the paste through the holes to facilitate the formation of a conductive path through the ceramic substrate after some sintering. A portion of this is sintered in the atmosphere in the BTU model TFF142-790A24 belt furnace with temperature data recommended by the paste manufacturer, ie a maximum temperature of 850 ° C.

  Following this step, the circuit reinforcement pattern shown in FIG. 7 is printed and sintered to the circuit side behind the substrate (again, the same “Cellmalloy” conductive paste described above is used). This step results in a relatively thick circuit pattern in a certain area where electrical connection is subsequently made.

  Following this, a set of address line columns and connector pads are printed on the visible front side of the board. These lines extend to the connector pads along the entire length of the board (FIG. 6). Connector pad rows are formed in this step (FIG. 6). The address line row and the column connector pad row are formed from the same silver-platinum paste used in the same print and sintered state. The substrate is located on the same master plate having the through holes of FIG. The vacuum is supplied to extrude the conductive paste from below through the through hole toward the rear side of the substrate. The thickness of the sintered electrode layer is about 8 μm. There are 52 address lines per inch, and the total number of address lines is 68.

  The next three layers of lead-niobate dielectric paste (Cermalloy # IP9333) are then printed and sintered at the top of the address line row with the temperature conditions recommended by the manufacturer in the belt furnace (maximum temperature 850 ° C) Is done. The bond thickness of the dielectric layer is 50 μm.

  Following this step, the circuit side behind the substrate is sealed according to Example 5 whose pattern is shown in FIG.

  Next, a 3-10 μm thick layer of lead-zirconate-titanate (PZT) is deposited on the lead-niobate dielectric paste to form a smooth surface. The sol-gel technique used and immersed according to Example 5 is used. The thin film phosphor layer is deposited by a known method of evaporation using an electromagnetic beam. The phosphorescent layer is zinc sulfate doped with 1% manganese. This is deposited over a thickness of between 0.5 and 1 μm.

  The next step is to deposit a 300 nm thick indium tin oxide (ITO) layer on top of the phosphor layer used in the known manner of electromagnetic beam evaporation.

  The ITO layer is patterned into 256 address lines using an argon ion laser 2 watt CW (continuous wavelength) inverted to a wavelength of 514.5 nm. The EL laminate is mounted on a movable X-axis table. This X-axis table moves the laminate in a direction perpendicular to the line scribed by the laser beam. The laser beam is moved in the Y-axis direction to scribe the line. The laser beam is focused on a 12 macrometer spot and the laser power is adjusted as follows. That is, the indium tin oxide, the underlying phosphor layer and about 10% of the underlying combined dielectric layer are adjusted to be removed at the scanned location of the laser beam (about 1.8 W). . The scanning speed is controlled to about 100 mm / sec and 500 mm / sec to provide an address line with a gap of about 40 μm or 25 μm, respectively, and a depth of 6-8 μm or 3-4 μm. An interval between address lines (for example, between the centers of lines) is about 500 μm. Vacuum near the substrate stops material evaporation and removal. In the transmissive electrode pattern, the removal is performed completely at once as shown in FIG. There are approximately 50 address line rows per inch on all displays, for a total of 256 columns.

  Before the ITO column line is scribed, the silver internal connection between the front (row) connector pad and the first ITO address line is passed from the silver through the shadow mask as shown in the pattern diagram of FIG. Screen printed.

  After laser scribing, the front view side of all displays is sprayed with a protective polymer coating (MG Lysin Clear Lacquer, cat # 419).

  The display is then inspected with the voltage across the selected pixel supplied by connection with a pulsed power supply. This pulse power supply unit supplies a pulse voltage of 160 V at a repetition frequency of 64 Hz. Each pixel illuminates reliably with a light intensity corresponding to the single pixel device of the previous embodiment.

  According to the address line of this embodiment, a higher level than that obtained by the photolithographic technology format is basically obtained.

Typical examples of devices that can be used in practice are ITO address line widths of 180-205 μm and gaps between lines of 65-80 μm. Starting from the above, according to the invention, gaps of 25 μm and 40 μm are produced depending on the scanning speed of the laser. Such a high solution takes into account the relatively high ratio of active area to the entire display. This is because a relatively wide ITO address line can be used with a relatively small gap.
Example 7
This embodiment is represented by two layers dielectrically constructed according to the present invention. However, in this embodiment, the first dielectric layer is formed from a paste having a higher dielectric constant than the paste used in the third and fourth embodiments.

  This device is constructed starting from Example 3 above, however, the first dielectric layer is formed from a lead-niobate paste. This paste is obtained as a high capacitance paste K from electrochemical experiments using the number 4210. The sintered paste has a dielectric constant of about 10,000. The first dielectric layer has a thickness of about 50 μm. A thickness of about 5 μm is applied to the sol-gel layer of PTZ as described in Example 3.

This device works with a threshold voltage of 91V and a luminous intensity of 50 footrun belts at 150V for minimum brightness.
Example 8
This embodiment is represented by two layers configured dielectrically. In this case, the first dielectric layer is formed of a lead / niobate paste, and the second dielectric layer is formed of a lead / lanthanum / zirconate / titanate paste (PLZT). This PLZT has a dielectric constant of about 1000. In this PLZT, the mass ratio of zirconium: titanium: lanthanum is 52:32:16.

  The apparatus constructed as starting from Example 3 has a sol-gel layer produced as follows.

  Dissolve 120 grams of 99.5% pure lead acetate in 50 ml glacial acetic acid. This solution is heated to 90 ° C. It is then held at this temperature for 2 minutes before being cooled to 70 ° C. Then 55.4 grams of zirconium propoxide is added and the solution is heated to 80 ° C. and held at this temperature for 1 minute. After cooling to 70 ° C., 21.8 grams of titanium isopropoxide is added. Next, 11.4 grams of lanthanum nitrate is dissolved in 20 ml of glacial acetic acid and added to the solution. Finally, 10 ml of ethylene glycol, 5 ml of propane-2ol, and 2.5 ml of demineralized water are added to stabilize the solution and adjust the viscosity to a suitable value.

  The PLZT sol-gel layer is used for the first dielectric layer formed by immersion by means similar to those described in Example 3 above. The immersed part is sintered at 600 ° C. for conversion to a second layer for PLZT. Four layers of PLZT are used by continuous dipping and sintering as described above to create a sufficiently smooth surface for the phosphor layer deposition. A total thickness of 5 μm is obtained.

  This device works with a threshold voltage of 75V and a luminous intensity of 37 foot run belts at 150V.

  All statements so far made are indicative of the specific level of skill in the form of skill required for the present invention. All descriptions are embodied with the same scope of references as each individual description is presented in detail and individually to be referred to by relationship herein.

  The technical terms and expressions used in this specification are used as terms for description and are not intended to be limiting. Nor is it so emphasized that the use of such terminology and expressions is excluded so as to exclude those corresponding to the features shown and described hereinbefore. It should be noted that the scope of the present invention is defined and limited in the claims.

EFFECT OF THE INVENTION The present invention provides an improved electroluminescent laminate dielectric layer structure and a method for producing this dielectric layer structure.

1 is a cross-sectional view of a laminate structure including two dielectric layers of the present invention. It is a top view of the laminate structure of FIG. FIG. 3 is a cross-sectional view of a laminate structure cut along a row electrode showing an advantageous embodiment for connecting column and row electrode address lines with voltage driven components of a voltage drive circuit. FIG. 3 is a plan view of a back substrate provided with an advantageous pattern of through holes for electrically connecting the address lines and the voltage drive components of the drive circuit. FIG. 2 is a plan view of an advantageous drive circuit pattern printed on the back side of a back substrate. It is a top view of the column electrode and row path | route printed on the front side of the back substrate. FIG. 6 is a plan view of a circuit path reinforcement pattern advantageously printed on the drive circuit pattern of FIG. 5. FIG. 8 is a plan view of a sealing glass pattern advantageously printed on the drive circuit pattern and the circuit path reinforcing pattern of FIGS. 5 and 7. It is a top view of a row electrode track pattern. FIG. 10 is a plan view of electrical connections printed between the row line of FIG. 9 and the row path of FIG. 6.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Dielectric layer structure 12 Board | substrate 14 Back electrode 18 1st dielectric layer 20 2nd dielectric layer 22 Phosphorescent layer 24 Front electrode 26 Sealing layer

Claims (12)

A method of forming an electroluminescent display panel electrically connected from an EL laminate to a voltage drive circuit, the EL laminate comprising a phosphor layer sandwiched between a front set and a back set of intersecting address lines. An electroluminescent display panel comprising: a back address line formed on a rigid back substrate supporting the laminate, wherein the phosphor layer is separated from the back address line by one or more dielectric layers In the method of forming
(A) providing a rigid back substrate capable of supporting the EL laminate;
(B) forming a plurality of through-holes patterned for connection of address lines to be subsequently formed on the rigid back substrate;
(C) forming electrically conductive paths through each of the through-holes in the rigid back substrate and subsequently firing to electrically connect each address line formed subsequently to the voltage drive circuit;
(D) forming spaced back address lines on the rigid back substrate followed by firing, each end terminating adjacent to a through hole and electrically connected to the conductive path; Forming a back address line; and
(E) forming a dielectric layer on the back address line after forming the through hole, the conductive path, and the back address line, the dielectric layer being formed of a ceramic material on the back electrode by a thick film technique; Forming by depositing, followed by firing;
(F) forming a phosphorescent layer on the dielectric layer;
(G) forming a front address line spaced on the phosphor layer, forming a front address line having one end terminated close to the through hole and electrically connected to the conductive path; ,
A method comprising the steps of: The voltage driving circuit includes a voltage driving component, the voltage driving component is provided in a circuit pattern on the back surface of the substrate, and the output side of the component is connected to a front address line and a back address by a conductive path penetrating each through hole. The circuit pattern is printed on the back of the board in a pattern that is connected to the track,
A conductor path through each of the through holes is formed from a thick film conductive paste printed with a circuit pattern on the back side of the board, and in the board to form a front connector path and a back connector path on both sides of the board. Pulled through the through-hole and fired, the back connector path is electrically connected to the voltage drive circuit, the front connector path is electrically connected to the back address line, and the front address line is 2. The method of claim 1, wherein the second conductive material is used to connect to the front connector path, either by the front address line and one end of the rear address line covering the front connector path.   The method of claim 2, wherein the substrate and the back address line are made of a material that can withstand a temperature of about 850 ° C.   4. The method of claim 3, wherein the substrate is opaque and the through hole is formed by a laser.   The method of claim 4, wherein the substrate is alumina.   The substrate is generally rectangular, and the through hole is formed around a substrate adjacent to a front address line end and a back address line end formed successively on at least two sides of the substrate. The method according to claim 2.   The conductive material in the conductive path, the back circuit pattern, and the front connector path and the back connector path is a baked silver / platinum paste, and the conductive material used to connect the front address line to the front connector path is The method of claim 6, wherein the method is silver.   3. The method according to claim 2, wherein the through hole is patterned so as to be adjacent to one end or both ends of the address line.   9. The method according to claim 2, further comprising forming through holes spaced along the length direction of the address lines. A method of forming an electroluminescent display panel electrically connected from an EL laminate to a voltage drive circuit, the EL laminate comprising a phosphor layer sandwiched between a front set and a back set of intersecting address lines. A back address line is formed on a rigid back substrate supporting the laminate, and the phosphor layer is separated from the back address line and the front address line by one or more dielectric layers, In a method of forming a luminescent display panel,
(A) providing a rigid back substrate capable of supporting the EL laminate;
(B) forming a plurality of through-holes patterned for connection of address lines to be subsequently formed on the rigid back substrate;
(C) forming electrically conductive paths through each of the through-holes in the rigid back substrate and subsequently firing to electrically connect each address line formed subsequently to the voltage drive circuit;
The voltage driving circuit includes a voltage driving component, the voltage driving component is provided in a circuit pattern on the back surface of the substrate, and the output side of the component is connected to a front address line and a back address by a conductive path penetrating each through hole. The circuit pattern is printed on the back of the board in a pattern that is connected to the track,
A conductor path through each of the through holes is formed from a thick film conductive paste printed with a circuit pattern on the back side of the board, and in the board to form a front connector path and a back connector path on both sides of the board. Pulled through the through-hole and fired, the back connector path is electrically connected to the voltage drive circuit, the front connector path is electrically connected to the back address line, and the front address line is Connecting to the front connector path either using a second conductive material or by one end of the front address line and the back address line covering the front connector path;
(D) forming spaced back address lines on the rigid back substrate followed by firing, each end terminating adjacent to a through hole and electrically connected to the conductive path; Forming a back address line; and
(E) forming a dielectric layer on the back address line after forming the through hole, the conductive path, and the back address line, the dielectric layer being formed of a ceramic material on the back electrode by a thick film technique; Forming by depositing, followed by firing;
(F) forming a phosphorescent layer on the dielectric layer;
(G) forming a transparent dielectric layer on the phosphorescent layer;
(H) forming a front address line spaced on the transparent dielectric layer, the front address line having one end terminated adjacent to the through hole and electrically connected to the conductive path; When,
A method comprising the steps of:   The method of claim 10, wherein the through hole is patterned to be adjacent to one end or both ends of the address line.   The method according to claim 10, comprising forming through holes spaced along the length direction of the address lines.

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