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JP2006031697A - 分岐ターゲットバッファと使用方法 - Google Patents

分岐ターゲットバッファと使用方法 Download PDF

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Publication number
JP2006031697A
JP2006031697A JP2005198036A JP2005198036A JP2006031697A JP 2006031697 A JP2006031697 A JP 2006031697A JP 2005198036 A JP2005198036 A JP 2005198036A JP 2005198036 A JP2005198036 A JP 2005198036A JP 2006031697 A JP2006031697 A JP 2006031697A
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JP
Japan
Prior art keywords
word line
branch
instruction
target buffer
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005198036A
Other languages
English (en)
Japanese (ja)
Inventor
Kigo Boku
基 豪 朴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020040055635A external-priority patent/KR100591769B1/ko
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JP2006031697A publication Critical patent/JP2006031697A/ja
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2005198036A 2004-07-16 2005-07-06 分岐ターゲットバッファと使用方法 Pending JP2006031697A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040055635A KR100591769B1 (ko) 2004-07-16 2004-07-16 분기 예측 정보를 가지는 분기 타겟 버퍼
US11/080,986 US7471574B2 (en) 2004-07-16 2005-03-16 Branch target buffer and method of use

Publications (1)

Publication Number Publication Date
JP2006031697A true JP2006031697A (ja) 2006-02-02

Family

ID=39457380

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005198036A Pending JP2006031697A (ja) 2004-07-16 2005-07-06 分岐ターゲットバッファと使用方法

Country Status (3)

Country Link
JP (1) JP2006031697A (zh)
GB (1) GB2416412B (zh)
TW (1) TWI285841B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8595474B2 (en) 2009-06-01 2013-11-26 Fujitsu Limited Information processing apparatus and branch prediction method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8612944B2 (en) 2008-04-17 2013-12-17 Qualcomm Incorporated Code evaluation for in-order processing
CN111627481B (zh) * 2020-05-20 2022-02-01 中国科学院微电子研究所 一种字线译码电路、字线选通方法及存储器和电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07200395A (ja) * 1993-09-27 1995-08-04 Advanced Risc Mach Ltd データメモリ
JPH0926913A (ja) * 1995-07-13 1997-01-28 Toshiba Microelectron Corp キャッシュメモリ
US5740417A (en) * 1995-12-05 1998-04-14 Motorola, Inc. Pipelined processor operating in different power mode based on branch prediction state of branch history bit encoded as taken weakly not taken and strongly not taken states
JPH10111832A (ja) * 1996-10-04 1998-04-28 Hitachi Ltd メモリシステム
JP2000200493A (ja) * 1998-12-08 2000-07-18 Advanced Risc Mach Ltd キャッシュ・メモリ
US20050091479A1 (en) * 2003-10-24 2005-04-28 Sung-Woo Chung Branch predictor, system and method of branch prediction

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02278428A (ja) * 1989-04-20 1990-11-14 Toshiba Corp 分岐制御方式
JP3494484B2 (ja) * 1994-10-12 2004-02-09 株式会社ルネサステクノロジ 命令処理装置
US6011908A (en) * 1996-12-23 2000-01-04 Transmeta Corporation Gated store buffer for an advanced microprocessor
TW357318B (en) * 1997-03-18 1999-05-01 Ind Tech Res Inst Branching forecast and reading device for unspecified command length extra-purity pipeline processor
US6757815B2 (en) * 1999-12-23 2004-06-29 Intel Corporation Single array banked branch target buffer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07200395A (ja) * 1993-09-27 1995-08-04 Advanced Risc Mach Ltd データメモリ
JPH0926913A (ja) * 1995-07-13 1997-01-28 Toshiba Microelectron Corp キャッシュメモリ
US5740417A (en) * 1995-12-05 1998-04-14 Motorola, Inc. Pipelined processor operating in different power mode based on branch prediction state of branch history bit encoded as taken weakly not taken and strongly not taken states
JPH10111832A (ja) * 1996-10-04 1998-04-28 Hitachi Ltd メモリシステム
JP2000200493A (ja) * 1998-12-08 2000-07-18 Advanced Risc Mach Ltd キャッシュ・メモリ
US20050091479A1 (en) * 2003-10-24 2005-04-28 Sung-Woo Chung Branch predictor, system and method of branch prediction

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8595474B2 (en) 2009-06-01 2013-11-26 Fujitsu Limited Information processing apparatus and branch prediction method

Also Published As

Publication number Publication date
GB2416412A (en) 2006-01-25
TW200617777A (en) 2006-06-01
GB0514599D0 (en) 2005-08-24
TWI285841B (en) 2007-08-21
GB2416412B (en) 2006-09-20

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