JP2006019763A - Semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element in which occurrence of deviation of crystal orientation is suppressed.
A low defect formed in a selective growth buried semiconductor layer 3 in which a facet 1 is formed as an inclined surface with respect to an arrangement surface of a base semiconductor layer 2 in which a plurality of facets 1 are arranged, and covers the base semiconductor layer 2. A semiconductor element body is formed in the region to improve the characteristics.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device made of, for example, a group III nitride compound semiconductor.

  In recent years, semiconductor light emitting devices such as semiconductor lasers and light emitting diodes (LEDs) that can emit light from the visible region to the ultraviolet region using group III nitride compound semiconductors such as AlGaInN have been actively developed. It has been broken. Among these, in particular, in the field of optical recording, in order to improve the recording density of an optical disk or the like, there is a demand for practical use of a semiconductor laser capable of obtaining light in a short wavelength region.

  Recently, in an AlGaInN semiconductor laser, a semiconductor layer made of a group III nitride compound semiconductor is formed on a substrate made of sapphire via a buffer layer made of gallium nitride (GaN) by metal organic chemical vapor deposition (Metal Organic Chemical Vapor). Deposition: MOCVD) is used to achieve 300-hour continuous oscillation at room temperature (see Non-Patent Documents 1 and 2).

However, looking at the curve of the dynamic voltage due to use, it can be seen that there is a gradual increase from the initial stage of energization and that the deterioration is gradually progressing. The cause of this deterioration is that a layer made of a group III nitride compound semiconductor formed on the substrate has threading dislocations of about 1 × 10 ⁸ to 1 × 10 ⁹ pieces / cm 2 (dislocation defects are propagated in the crystal). It is conceivable to have a dislocation that penetrates. Therefore, in order to realize a practical life of 10,000 hours or more, it is necessary to reduce the density of threading dislocations, and various studies have been made.

For example, in one of them, a GaN layer is formed on a sapphire substrate via a buffer layer, and a mask made of band-shaped silicon dioxide (SiO ₂ ) having a width of 1 to 4 μm is formed on the sapphire substrate at a pitch of 7 μm. A method has been proposed in which a mask layer having a periodic structure is formed, and a GaN layer is selectively grown on the mask layer in the lateral direction by a halide vapor phase growth method or MOCVD method (Non-patent Document 1). And 2). As described above, when the GaN semiconductor layer is grown laterally across the mask layer by selectively growing GaN from the GaN layer exposed through the openings between the mask layers of the periodic structure, the SiO ₂ mask layer The density of threading dislocations in the GaN layer can be reduced to about 1 × 10 ⁷ pieces / cm ² .

A practical life of 1150 hours or longer can be realized by manufacturing an AlGaInN semiconductor laser element on a substrate prepared using this method (see Non-Patent Document 5).
Jpn.J.Appl.Phys.35L74 (1996) (Jpn.J.Appl.Phys.36L1059 (1997)) Jpn.J.Appl.Phys.36 L899 (1997) (J. Appl. Phys. 71, 2638 (1997)) J. Crystal Growth, vol.189-190 p.820-5 (1998)

  By the way, the semiconductor layer formed by the selective growth method using the mask layer described above has a shift of about 0.4 ° to 0.5 ° in the c-axis crystal orientation between the mask layer and the opening. This has been clarified by the analysis of the present inventors.

  When an element is fabricated on a semiconductor layer having a crystal orientation shift in this way, the crystal plane shift is included in the element active region, and various characteristics of the element, such as a semiconductor laser, emit light. It becomes inconvenient in characteristics such as a decrease in efficiency and a decrease in life.

  That is, as described above, for example, a sapphire substrate or a SiC substrate is used as a growth substrate for a GaN-based semiconductor, and these substrates are composed of a GaN-based semiconductor to be grown thereon and a lattice constant or a thermal expansion coefficient. Therefore, when a GaN-based semiconductor is grown on these substrates, defects such as dislocations are generated in the growth layer, and it is difficult to grow a high-quality single-crystal GaN-based semiconductor.

Therefore, as described above, a GaN layer containing threading dislocations at a high density is formed on a sapphire substrate or SiC substrate via a buffer layer, and a strip-like mask layer made of SiO ₂ is formed on the sapphire substrate or the SiC substrate at a required interval. After the formation, a GaN layer is selectively grown through the opening between the strip mask layers, and the GaN semiconductor layer is formed on the mask layer as a semiconductor layer having a low defect density by lateral growth. As a result of analyzing the above by means of electron diffraction, X-ray diffraction, etc., the c-axis crystal orientation is shifted by about 0.4 ° to 0.5 ° between the mask layer and the opening. Was investigated.
Thus, the deviation in c-axis crystal orientation occurs, when the GaN is laterally grown on the SiO ₂ mask, on the SiO ₂ mask layer, in order to shift the direction of crystal growth as compared to the opening occurs is there.

Then, by structural analysis such as transmission electron microscopy or X-ray diffraction by the present inventors, it is clear that a crystal defect may or may not be introduced due to a shift in the crystal growth direction. It became. In the former case, the direction of the band-like SiO ₂ mask is set in the <11-20> direction, and in the latter case, it is set in the <1-100> direction. However, in any case, the deviation in the crystal growth orientation is mainly caused by the difference between the thermal expansion coefficients of SiO _{2 as the} mask material and GaN. Therefore, if the SiO ₂ mask layer does not exist in the lateral growth, it is good.
However, since this SiO ₂ mask layer has an effect of removing dislocations penetrating from the substrate side, the elimination of the mask layer has a contradiction that the defect density cannot be reduced.

  On the other hand, the present inventors have intensively studied, analyzed, and considered, and as a result, reduced the density of threading dislocations, and can suppress the occurrence of deviation in crystal orientation. I came to find.

  That is, in the above-described lateral growth, the present inventors bent threading dislocations by the growth facets generated along with the growth, and this bending is not only caused by the growth facets but also on artificially formed facet surfaces. We have determined that threading dislocations can be bent, and based on this, the density of threading dislocations is reduced in a specific region, and the occurrence of misalignment of crystal orientation can be suppressed. It constitutes an element.

  A semiconductor device according to the present invention includes a semiconductor device body formed on a semiconductor thin film having a base semiconductor layer in which a plurality of facets are arranged and a selectively grown embedded semiconductor layer covering the base semiconductor layer, and the facet Is formed by a surface inclined with respect to the arrangement surface of the base semiconductor layer.

  The present invention is the above-described semiconductor element, wherein threading dislocations in the selectively grown buried semiconductor layer are bent and extended in a direction substantially along the arrangement surface of the base semiconductor layer from the facet of the base semiconductor layer. It is characterized by being formed by bending and extending in a direction intersecting with the arrangement surface in association with threading dislocations from facets.

  Further, the present invention is the above-described semiconductor element, wherein a deviation in crystal orientation between the base semiconductor layer and the selectively grown embedded semiconductor layer is 0.1 ° or less.

  As described above, a semiconductor device according to the present invention has a structure including a selective growth buried semiconductor layer covering a facet of an underlying semiconductor layer in which a plurality of facets are arranged, that is, a slope, and the threading dislocation generated in the selective growth buried semiconductor layer. However, it bends and stretches in the lateral direction from the facet, that is, in a direction substantially along the placement surface of the underlying semiconductor layer, associates with threading dislocations from the opposite facet, and bends and stretches in the direction intersecting with the placement surface of the underlying semiconductor layer. This is based on the investigation of the occurrence, and forms a low defect density region of threading dislocations in which almost no threading dislocations exist except for the above-mentioned threading dislocation associating portion in the selectively grown buried semiconductor layer having this configuration.

Further, in the present invention, the configuration in which a mask of SiO ₂ or the like is embedded can be avoided, so that the occurrence of the above-described misalignment of crystal orientation and c-axis crystal orientation can be avoided.
The semiconductor device according to the present invention has excellent characteristics by forming a semiconductor device body, that is, an active region (operation region) in the selectively grown buried semiconductor layer itself or in a low defect density region of the semiconductor layer formed thereon. Various semiconductor elements can be configured.

  The slope of the facet in the present invention is not limited to a single inclined plane, and depending on the formation method, the main face is a slope having the angle α described above and a part thereof or a generally curved face. There are cases where

1 illustrates an embodiment of a semiconductor device according to the present invention.
FIG. 1 shows a schematic cross-sectional view of an example of a semiconductor thin film 40 constituting the element of the present invention.
In this case, a base semiconductor layer 2 made of a group III nitride compound semiconductor including, for example, Ga and N (nitrogen) in which a plurality of facets 1 are arranged, and covering the base semiconductor layer 2, for example, Ga and N are similarly formed. And a selectively grown buried semiconductor layer 3 made of a group III nitride compound semiconductor, and the facet 1 has a configuration formed by a surface inclined with respect to the arrangement surface AA ′ of the underlying semiconductor layer 2.

The threading dislocation d indicated by a thin line in the selectively grown embedded semiconductor layer 3 extends from the facet 1 of the base semiconductor layer 2 in a direction substantially along the arrangement surface of the base semiconductor layer 2, and associates with the threading dislocation from the opposing facet. Thus, it is formed to extend in a direction crossing the arrangement surface, that is, in a substantially vertical direction.
As a result, in the selectively grown buried semiconductor layer 3 formed so as to cover the base semiconductor layer 2, a high defect density region 4 having a high threading dislocation density is formed at the meeting portion of the threading dislocation d. In other cases, the low defect density region 5 in which the occurrence of threading dislocations is avoided is formed.

  Another embodiment of the semiconductor thin film constituting the semiconductor device according to the present invention has a substrate 6 made of, for example, C-plane sapphire or SiC, as shown in FIG. The base semiconductor layer 2 in which the facets 1 are arranged is formed on the main surface 6 a via the buffer layer 7.

  Furthermore, another embodiment of the semiconductor thin film constituting the semiconductor element according to the present invention includes a substrate 6 made of, for example, C-plane sapphire or SiC, as shown in FIG. A base layer 12 is formed on the main surface 6a via a buffer layer 7, and a base semiconductor layer 2 in which facets 1 are arranged is formed thereon.

  Further, another embodiment of the semiconductor thin film has a substrate 6 made of a single crystal group III nitride as shown in FIG. 4 as a schematic cross-sectional view of an example thereof, and directly on one main surface 6a thereof. A base semiconductor layer 2 made of a group III nitride in which facets 1 are arranged is formed.

  Further, as shown in FIGS. 5 to 8, other forms of the semiconductor thin film include gallium (Ga), aluminum (on the respective selectively grown embedded semiconductor layers 3 in the configuration shown in FIGS. 1 to 4. A group III nitride compound semiconductor layer 8 containing at least one group III element and nitrogen (N) in the group consisting of Al), boron (B), and indium (In) is epitaxially grown. In this case, the threading dislocations in the selectively grown buried semiconductor layer 3 below are also generated in the compound semiconductor layer 8, but also in the compound semiconductor layer 8, the high defect density region 4 and other threading dislocations are avoided. The low defect density region 5 thus formed is formed.

In the embodiment of the semiconductor device according to the present invention, for example, in the selectively grown buried semiconductor layer of the semiconductor thin film shown in FIGS. 1 to 4, the low defect density region 5 is affected by at least the active region of the semiconductor device, that is, the crystal defect. A region is formed.
Another embodiment of the semiconductor device according to the present invention is affected by at least an active region of the semiconductor device, that is, a crystal defect, in the low defect density region 5 of the compound semiconductor layer 8 of the semiconductor thin film shown in FIGS. The operation area is formed.
2 to 8, parts corresponding to those in FIG.

  The semiconductor thin film according to each configuration described above has a crystal orientation of the base semiconductor layer 2, the selective growth buried semiconductor layer 3, and the compound semiconductor layer 8 epitaxially grown on the base semiconductor layer 2 and the selective growth buried semiconductor layer 3. The deviation, that is, the deviation of the c-axis is kept within 1 °.

Next, an embodiment of a method for manufacturing a semiconductor thin film will be described with reference to FIGS. As shown in FIG. 9A, a substrate 6 made of, for example, C-plane sapphire is prepared, and a buffer layer 7 made of, for example, GaN having a thickness of, for example, 30 nm is formed on one main surface 6a of the C-plane by, for example, MOCVD. grow up. In this MOCVD, for example, the substrate temperature is set to 520 ° C., and trimethyl gallium gas ((CH ₃ ) ₃ Ga) and ammonia gas (NH ₃ ) are used as source gases.

Next, the underlying layer 2 made of GaN is formed to a thickness of 2 μm, for example, on the buffer layer 7 by MOCVD, for example. At this time, the substrate temperature is set to 1050 ° C., for example. Note that threading dislocations d schematically indicated by thin lines in the drawing are present in the underlying semiconductor layer 2 at a high density of, for example, 1 × 10 ⁹ / cm ² .

Subsequently, as shown in FIG. 9B, a mask 9 is formed on the base semiconductor layer 2. The mask 9 is formed, for example, by forming a dielectric SiO ₂ layer, for example, on the entire surface of the underlying semiconductor layer 2 by a CVD method at a substrate temperature, eg, 450 ° C., and pattern-etching the SiO ₂ layer by photolithography. To do. That is, a photoresist layer is applied on the SiO ₂ layer, and a predetermined pattern is exposed and developed thereon, thereby forming a plurality of stripe portions at a predetermined interval. By using this photoresist as a mask, the SiO ₂ layer is etched to form a mask 9 in which stripe-shaped openings 9w are formed. The mask 9 has a configuration in which the stripes are formed, for example, extending in the <1-100> direction (a direction orthogonal to the paper surface in FIG. 9) and arranged in the <11-20> direction with a predetermined interval. be able to.

Then, for example, washing with acetone (CH ₃ COCH ₃ ) and methanol (CH ₃ OH) is performed, and further, for example, immersed in diluted hydrochloric acid (HCl) or diluted hydrofluoric acid (HF) for 10 seconds, and then washed with pure water. To do.
Subsequently, the inside of the opening 9w of the mask 9 is selectively etched by reactive ion etching (RIE). At this time, the SiO ₂ layer mask 9 is also slightly etched, so that the width of the opening 9w is widened as shown in FIG. 9C, and the underlying semiconductor layer 2 is also etched to have a cross section, for example, approximately V-shaped. A groove 10 is formed.

Further, by continuing this etching, the groove 10 is further deepened and widened, so that the mask 9 is eliminated, the upper ends of the adjacent grooves 10 communicate with each other, and the stripe 11 having a triangular cross section is formed. Facets 1 that are arranged in parallel and have inclinations opposite to each other at a required angle are formed on each side. The RIE for forming the groove 10 can be performed, for example, using a parallel plate RIE apparatus, using BCl ₃ and N ₂ , with a power of 15 W and a condition of 20 mTorr. By performing such RIE, the facets 1 formed on both side surfaces of the stripe 11 extending in the <1-100> direction with an inclination of 45 ° with respect to the substrate surface, that is, the underlying semiconductor layer 2 are arrayed. Is done.

Thereafter, the substrate 6 on which each semiconductor layer is laminated is sufficiently immersed in hydrofluoric acid (HF) to sufficiently remove the SiO ₂ film remaining on the surface, and further washed with pure water.
High quality GaN is epitaxially grown by, for example, MOCVD on the underlying semiconductor layer 2 that has been cleaned in this manner and on which the facets 1 are arranged. At this time, this growth is performed selectively from the facet 1 in the lateral direction, that is, in the direction along the <11-20> direction, that is, in the direction along the arrangement surface of the underlying semiconductor layer 2. By continuing this growth, the growth from the opposing facet 1 abuts and the inside of the trench 10 is buried. However, if this growth is further continued, the substrate 10 crosses the arrangement surface of the underlying semiconductor layer 2 and is almost the same as this arrangement surface. The growth is performed in the vertical direction, and the selective growth buried semiconductor layer 3 is formed by covering the entire underlying semiconductor layer 2 and having a flattened surface of GaN. In this vapor phase growth, for example, the substrate temperature is set to 1050 ° C., and ammonia gas and trimethylgallium gas are used as source gases. Specifically, for example, trimethylgallium gas is supplied so that the growth rate is about 4 μm / hour while ammonia gas is supplied at a large flow rate of 10 liters / minute, and the reaction is performed under normal pressure.

In this way, as shown in FIG. 10B, the selectively grown buried semiconductor layer 3 having a flat surface by filling the trench 10 cleanly is formed.
When the selectively grown embedded semiconductor layer 3 formed in this way was observed with a transmission electron microscope, it was confirmed that the dislocation d existing in the underlying semiconductor layer 2 on the facet 1 surface was bent at the facet 1. Therefore, the dislocation d penetrating almost perpendicularly to the c-axis direction in the base semiconductor layer 2 is bent at the facet 1 by artificially formed pseudo facets by the side surface of the groove 10 by etching, that is, the arrangement surface of the base semiconductor layer 2, that is, It runs in a horizontal direction substantially along the plate surface of the substrate 6 and does not penetrate the upper part. Then, when the growth is made from the facets 1 facing each other and the growth hits, the threading dislocations d meet from the facets 1 facing each other, and a part of the penetration dislocations in the direction intersecting the arrangement surface of the base semiconductor layer 2, that is, the stacking direction. As the dislocations bend and extend upward, the defect density in the selectively grown buried semiconductor layer 3 is reduced to 1 × 10 ⁷ / cm ² .

Therefore, a high defect density region 4 in which threading dislocations exist at a high density is generated in this meeting portion, but a low defect density region 5 having a low dislocation density is formed in other portions. The selective growth buried semiconductor layer 3 formed in this way is in direct contact with the underlying semiconductor layer 2 without using a selective growth mask such as a SiO ₂ layer. Became 1 ° or less.

  Thus, since the low defect density region 5 having a low penetration defect density is formed and the deviation of the crystal orientation is suppressed, the semiconductor thin film 40 having the extremely high quality selectively grown embedded semiconductor layer 3 is formed. Could be formed. Therefore, if a semiconductor element body constituting a semiconductor element or semiconductor device is formed on the low defect density region 5 of the semiconductor thin film 40, an extremely reliable semiconductor element or semiconductor device can be constituted.

Next, an example of another embodiment of a method for manufacturing a semiconductor thin film will be described with reference to FIGS.
Also in this example, for example, a C-plane sapphire substrate 1 is prepared, and a buffer layer 7 made of GaN having a thickness of, for example, 30 nm is formed on the main surface 6a by, for example, MOCVD. At this time, as shown in FIG. 11A, the substrate temperature is, for example, 520 ° C., and the source gas is trimethylgallium gas ((CH ₃ ) ₃ Ga) and ammonia gas (NH ₃ ). Next, an underlying layer 12 made of GaN is similarly formed on the buffer layer 7 to a thickness of 2 μm at a substrate temperature of, for example, 1050 ° C., for example, by MOCVD.

The buffer layer 7 is made of a near amorphous crystal layer grown at a low temperature, and serves as a nucleus when the underlayer 12 is grown. The underlayer 12 is made of crystal, the threading dislocation d has 1 × 10 ⁹ / cm ² degree extending in the stacking direction.

In order to form the base semiconductor layer 2 in which facets are arranged on the base layer 12, as shown in FIG. 11B, a selective growth mask 13 made of, for example, SiO ₂ for performing selective growth of a semiconductor is formed with a thickness of, for example, 5 μm. The stripes extend in the <11-20> direction, and are formed in a parallel array with a pitch of 12 μm in the <1-100> direction, for example, a width of 5 μm and an interval of 7 μm. The selective growth mask 13 is formed by, for example, forming a SiO ₂ layer over the entire surface at a substrate temperature of 450 ° C., for example, by CVD, and patterning by pattern etching by photolithography, that is, application of photoresist, pattern exposure, and development. By performing pattern etching using the photoresist layer as an etching mask, the stripe-shaped opening 13w can be formed to form the above-described pattern.

Then, it is washed with acetone (CH ₃ COCH ₃ ) and methanol (CH ₃ OH), further immersed in diluted hydrochloric acid (HCl) or diluted hydrofluoric acid (HF) for about 10 seconds, and then washed with pure water. Do. Further, the substrate is sufficiently immersed in hydrofluoric acid (HF) to completely remove SiO ₂ remaining on the surface of the underlayer 12 exposed to the outside through the openings 13w of the selective growth mask 13, and further washed with pure water.

  Thereafter, using the selective growth mask 13 as a mask, the high-quality base semiconductor layer 2 made of GaN is grown on the base layer 12 exposed to the outside through the opening 13w until just before the mask 13 is covered with the mask 13, for example. Thus, a periodic triangle-shaped stripe 11 extending in the <11-20> direction is arranged on the growth surface, and the both sides of each stripe 11 are in relation to the C plane by {1-101}, that is, the underlying semiconductor layer The underlying semiconductor layer 2 is formed on which the facet 1 having an inclination of about 69 ° with respect to the arrangement surface 2 is formed. In this case, MOCVD is performed, for example, at a substrate temperature of 1050 ° C. and using ammonia gas and trimethyl gallium gas as source gases. Specifically, for example, trimethylgallium gas is supplied at a growth rate of about 4 μm / hour while ammonia gas is supplied at a large flow rate of 10 liters / minute, and the reaction is performed under normal pressure.

Subsequently, as shown in FIG. 12A, the selective growth mask 13 is completely etched away by being sufficiently immersed in hydrofluoric acid (HF). Then, it is washed with acetone (CH ₃ COCH ₃ ) and methanol (CH ₃ OH), and further immersed in diluted hydrochloric acid (HCl) or diluted hydrofluoric acid (HF) for about 10 seconds, and then washed with pure water. Do.

  Thereafter, a selective growth buried semiconductor layer 3 of high quality GaN is selectively grown on the underlying semiconductor layer 2 on which the facets 1 are arranged, for example, by MOCVD. In this growth, for example, the temperature of the substrate 1 is 1050 ° C., and ammonia gas and trimethyl gallium gas are used as the source gas. Specifically, for example, trimethylgallium gas is supplied so that the growth rate is about 4 μm / hour while ammonia gas is flowed at a large flow rate of 10 liters / minute, and the reaction is performed under normal pressure. In this way, selective growth from the facet 1 in the horizontal direction, that is, in the <11-20> direction along the arrangement surface of the underlying semiconductor layer 2 is performed. By continuing this growth, the growth from the opposing facet 1 strikes and the inside of the groove 10 between the stripes 11 is buried, but when this growth is further continued, the growth is made in the direction perpendicular to the arrangement plane, and FIG. As shown in FIG. 2, the selective growth embedded semiconductor layer 3 is formed by covering the entire surface of the underlying semiconductor layer 2 and planarizing the surface of GaN.

Even in this case, according to observation with a transmission electron microscope, it was confirmed that the threading dislocation d was bent in the facet 1 even with respect to the facet 1 formed by this selective growth. That is, dislocations penetrating almost perpendicularly in the c-axis direction in the base layer 12 are bent by the facets 1, run along the placement surface of the base semiconductor layer 2, that is, substantially in the horizontal direction, and do not penetrate to the upper part. That is, in the same manner as described with reference to FIG. 10B, when the growth faces each other from the facets 1 facing each other, the dislocations d from the facets 1 face each other and intersect with the arrangement surface of the underlying semiconductor layer 2. That is, when some dislocations are bent and extend upward in the stacking direction, the defect density in the selectively grown buried semiconductor layer 3 is reduced to 1 × 10 ⁷ / cm ² .

Therefore, a high defect density region 4 in which threading dislocations exist at a high density is generated in this meeting portion, but a low defect density region 5 having a low dislocation density is formed in other portions. The selective growth buried semiconductor layer 3 formed in this way is in direct contact with the base layer 12 without using a selective growth mask such as a SiO ₂ layer, and therefore the deviation of the c-axis from the substrate 6 is not caused. 1 ° or less.

  Thus, since the low defect density region 5 having a low penetration defect density is formed and the deviation of the crystal orientation is suppressed, the semiconductor thin film 40 having the extremely high quality selectively grown embedded semiconductor layer 3 is formed. Could be formed. Therefore, if a semiconductor element or a semiconductor element body constituting a semiconductor device is formed on the low defect density region 5 of the semiconductor thin film 40, an extremely reliable semiconductor element, and thus a semiconductor device can be constituted.

  The semiconductor element according to the present invention can be constituted by, for example, the semiconductor thin film 40 having the structure shown in FIGS. One embodiment of a semiconductor device according to the present invention can constitute a semiconductor light emitting device as shown in a schematic sectional view of an example in FIG. In this example, an SCH (Separate Confinement Heterostructure) type semiconductor laser is configured. In this example, the semiconductor laser device body is formed on the semiconductor thin film 40 shown in FIG. 2, or the semiconductor laser device is formed in the semiconductor layer 8 of the semiconductor thin film 40 shown in FIG.

  In FIG. 13, portions corresponding to those in FIGS. 2 and 6 are denoted by the same reference numerals and redundant description is omitted. In this example, the first conductivity type, for example, n is formed on the selectively grown buried semiconductor layer 3. The first contact layer 21, the first cladding layer 22, and the first guide layer 23 are sequentially epitaxially grown on the active layer 24, the deterioration preventing layer 25, and the second conductivity type second layer. A guide layer 26, a second cladding layer 27, and a contact layer 28 are sequentially stacked.

  On the contact layer 28, an insulating layer 29 of, for example, SiO2 is formed. Then, an etching groove is formed in a part of these epitaxial growths from the insulating layer 29 side to the position where the first contact layer 21 is exposed, and the first electrode 31 is formed ohmic on the exposed portion of the first contact layer 21. Adhere. Further, the stripe-shaped second contact is formed in the insulating layer 29 through a stripe-shaped opening 29w extending in the direction orthogonal to the paper surface in FIG. 13, that is, along the extending direction of the stripe 11 of the facet 1, that is, along the opening 29w. A second electrode 32 is formed in ohmic contact with the layer 28.

  As an example of the manufacturing method of this semiconductor element, in this example, a semiconductor laser element, for example, a base on which facets 1 are arranged on a substrate 6 via a buffer layer 7 by a method similar to that described with reference to FIGS. The semiconductor layer 2 and the selectively grown buried semiconductor layer 3 are formed, and a first contact layer 21 made of an n-type GaN layer, for example, having a thickness of 0.1 μm, is added on the flat surface, for example, by adding an n-type impurity Si having a thickness of 2 μm. A first cladding layer 22 made of n-type AlGaN mixed crystal to which 5 μm Si is added, for example, a first guide layer 23 is successively epitaxially grown using n-type GaN to which Si having a thickness of 0.1 μm is added. Subsequently, for example, an active layer 24 having a quantum well layer of 3 nm thickness and a GaInN mixed crystal multiple quantum well structure of 4 nm thick and 4 nm thick barrier layer is epitaxially grown. Subsequently, a deterioration preventing layer 25 made of AlGaN having a thickness of 20 nm, for example, is epitaxially grown, and a second guide layer 26 made of p-type GaN having a thickness of 0.1 μm, for example, to which Mg of a p-type impurity is added. For example, a second cladding layer 27 made of a p-type AlGaN mixed crystal having a thickness of 0.5 μm, for example, a p-type second contact layer 28 made of a p-type GaN mixed crystal having a thickness of 0.5 μm, for example, is epitaxially grown sequentially.

Each of the semiconductor layers 21 to 28 described above has, for example, a substrate temperature of 800 to 1000 ° C., and trimethyl aluminum ((CH ₃ ) ₃ Al), trimethyl gallium gas ((CH ₃ ) ₃ Ga), monosilane (SiH ₄ ), Bis = methyl synchropentagenyl magnesium gas (MeCp ₂ Mg) or bis = syncropentagenyl magnesium gas (Cp ₂ Mg) can be used.

  The insulating layer 29 is formed by, for example, a CVD method, and a stripe-shaped opening 29w is formed in the insulating layer 29 by, for example, pattern etching by photolithography. The second electrode 32 is ohmicly formed on the contact layer 28 through the opening 29w. The electrode 32 can be formed by, for example, a lift-off method. In this case, for example, a photoresist layer is formed by photolithography in addition to the electrode forming portion, and then, for example, Ni and Au are sequentially deposited on the entire surface, and then the resist layer is removed to deposit on the resist layer. The removed Ni and Au are removed, that is, lifted off to form the second electrode 32.

  Thereafter, in the formation portion of the first electrode 31, the insulating layer 29, the contact layer 28, the second cladding layer 27, the second guide layer 26, the deterioration preventing layer 25, the active layer 24, the first guide layer 23, and The first cladding layer 22 is selectively removed sequentially. Thereafter, Ti, Al and Au are selectively and sequentially deposited on the n-type contact layer 21 to form the first electrode 21.

  As described above, since the density of threading dislocations in the selectively grown buried semiconductor layer 3 is extremely low as described above, the density of threading dislocations is extremely low, and in particular, the low defect density in FIGS. Since a low defect density region is formed in a portion corresponding to the region 5, a laser resonator is configured at a position corresponding to the low defect density region, that is, substantially above the stripe 11.

  That is, in the case of the above-described configuration, a current injection region is formed in the active layer 24 in a limited manner in the active layer 24 under the contact portion to the contact layer 28 through the stripe-shaped openings 29w. Therefore, the contact portion of the second electrode 32, that is, the opening 29 w of the insulating layer 29 is formed above the stripe 11.

  Then, after the electrodes 31 and 32 are formed, cutting is performed, for example, by cleavage so as to set the resonator length to a predetermined length, and a mirror surface that forms the resonator end face is formed on this cut surface.

  In the semiconductor laser having this configuration, a forward current is applied between the first and second electrodes 31 and 32, whereby a current flows into the active layer 24 and light emission occurs due to electron-hole recombination.

  At least the operating part of the semiconductor light emitting device with this configuration, that is, the semiconductor laser, is formed in a region where the threading dislocation density is low, and the deviation of the crystal orientation is avoided, thereby reducing the threshold current and driving voltage. It is possible to achieve reduction, mitigation of characteristic deterioration associated therewith, and thus longer life.

FIG. 14 is a schematic cross-sectional view of another embodiment of a semiconductor device according to the present invention, in this example, a semiconductor laser. In this example, a semiconductor laser is applied to the semiconductor thin film 40 according to the present invention shown in FIGS. In this example, a semiconductor laser having an SCH structure is formed.
In this case, the manufacturing method of the semiconductor thin film 40 can adopt, for example, the method described in FIGS. 11 and 12, and the semiconductor laser body and the manufacturing method thereof have the same configuration and manufacturing method as described in FIG. Can be taken.
14, parts corresponding to those in FIGS. 3, 7, and 13 are denoted by the same reference numerals, and redundant description is omitted.

  Also in this example, as in the semiconductor laser according to FIG. 13, at least the operating part is formed in a region where the threading dislocation density is low, and the deviation of the crystal orientation is avoided, thereby reducing the threshold current, The driving voltage can be reduced, the characteristic deterioration associated therewith can be reduced, and thus the life can be extended.

  In addition, this invention is not limited to the example mentioned above, A various deformation | transformation is possible. For example, when forming the stripe 11, that is, the facet 1 by selective growth in FIG. 11, the extension direction of the stripe 11 is selected as the <1-100> direction, and the C plane by {11-22} is selected. That is, the facet 1 having an inclination of about 58 ° with respect to the arrangement surface of the underlying semiconductor layer 2 can be formed. For example, the extending direction of the facet 1, and thus the extending direction of the high defect density region 4 and the low defect density region 5 Various crystal axis directions can be selected.

  Further, for example, in FIGS. 13 and 14, the conductivity type of each of the semiconductor layers 21 to 28 is a conductivity type opposite to that described above, and the composition thereof is not limited to the above example, but other appropriate ones. The present invention can also be applied to a case where a semiconductor is used. However, in this case, the semiconductor layer includes a group III nitride compound semiconductor, that is, at least one group III element selected from the group consisting of Al, Ga, B, and In, and N (nitrogen). This is particularly effective when each layer is composed of a group III nitride compound semiconductor).

  In the above-described example, the SCH structure, that is, the structure in which the first and second first guide layers 23 and 26 are disposed with the active layer 24 interposed therebetween, is the DH (where the guide layer is not disposed). Semiconductor lasers having various configurations such as Double Hetero) or light emitting elements such as light emitting diodes can be configured.

  Further, the semiconductor element according to the present invention is not limited to the semiconductor light emitting element, and other various semiconductor elements, for example, semiconductor elements such as FET (Field Effect Transistor) can be configured.

  A single semiconductor device having semiconductor elements or an integrated circuit device in which a plurality of semiconductor elements are formed on a common semiconductor thin film according to the present invention can be obtained. In this case, each semiconductor thin film described with reference to FIGS. 1 to 8 is manufactured by the method described with reference to FIGS. 9 to 12, and further, for example, a semiconductor light emitting element is formed with the structure and method described with reference to FIG. 13 or FIG. Or, it can be obtained by forming other semiconductor elements.

  Even in this case, a semiconductor device using a semiconductor element having excellent characteristics can be formed.

  For example, when configuring a semiconductor integrated circuit device, the arrangement of the facets 1 in the common semiconductor thin film 40, and therefore the arrangement interval of the low defect density regions 5 is not limited to being formed at equal intervals.

  In addition, in each of the above embodiments, each semiconductor layer has been described as being grown by MOCVD or halide vapor phase epitaxy, but other features such as molecular beam epitaxy (MBE) are also used. It can also be grown by a phase growth method. For example, the semiconductor layers 21 to 28 can be formed by other vapor phase growth methods such as the MBE method and the halide method.

As described above, in the semiconductor device according to the present invention, threading dislocations bend at the facet 1 in the selectively grown buried semiconductor layer 3 and further bend at the meeting point of the through defect accompanying the epitaxial growth grown from the opposing facet 1. By adopting the structure, it is possible to remarkably reduce the defect density in at least the formation part of the operation part of the semiconductor element body, and the selective growth buried semiconductor layer without interposing a selective growth mask such as SiO ₂ 3 is performed, the deviation in crystal orientation can be suppressed to 0.1 ° or less, so that a high-quality semiconductor thin film, and hence excellent characteristics, high reliability, and long life can be achieved.

It is a schematic sectional drawing of an example of one Embodiment of the semiconductor thin film used for this invention. It is a schematic sectional drawing of an example of other embodiment of the semiconductor thin film used for this invention. It is a schematic sectional drawing of an example of other embodiment of the semiconductor thin film used for this invention. It is a schematic sectional drawing of an example of other embodiment of the semiconductor thin film used for this invention. It is a schematic sectional drawing of an example of other embodiment of the semiconductor thin film used for this invention. It is a schematic sectional drawing of an example of other embodiment of the semiconductor thin film used for this invention. It is a schematic sectional drawing of an example of other embodiment of the semiconductor thin film used for this invention. It is a schematic sectional drawing of an example of other embodiment of the semiconductor thin film used for this invention. FIGS. 4A to 4C are process diagrams (part 1) illustrating an example of an embodiment of a method for producing a semiconductor thin film used in the present invention. A and B are process drawings (the 2) of an example of one Embodiment of the manufacturing method of the semiconductor thin film used for this invention. A to C are process diagrams (part 1) of an example of a method for producing a semiconductor thin film used in the present invention. A and B are process drawings (the 2) of an example of the manufacturing method of the semiconductor thin film used for this invention. It is a schematic sectional drawing of an example of the semiconductor light-emitting device by this invention. It is a schematic sectional drawing of the other example of the semiconductor light-emitting device by this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Facet, 2 ... Base semiconductor layer 2, 3 ... Selective growth embedded semiconductor layer 3, 4 ... High defect density region, 5 ... Low defect density region, 6 ... Substrate, DESCRIPTION OF SYMBOLS 7 ... Buffer layer, 8 ... Compound semiconductor layer, 9 ... Mask, 9w ... Opening, 10 ... Groove, 11 ... Stripe, 12 ... Underlayer, 13 ... Selective growth mask, 21... First contact layer, 22... First cladding layer, 23... First guide layer, 24... Active layer, 25. ... 2nd guide layer, 27 ... 2nd cladding layer, 28 ... 2nd contact layer, 29 ... insulating layer, 29w ... opening, 31 ... 1st electrode 32 ... second electrode, d ... threading dislocation

Claims (9)

  A semiconductor element body formed on a semiconductor thin film having a base semiconductor layer in which a plurality of facets are arranged and a selective growth embedded semiconductor layer covering the base semiconductor layer, and the facet of the base semiconductor layer A semiconductor element formed by a surface inclined with respect to an arrangement surface.   The threading dislocations in the selectively grown embedded semiconductor layer bend and extend from the facets of the base semiconductor layer in a direction substantially along the placement surface of the base semiconductor layer, and are associated with threading dislocations from the opposing facets to form the placement 2. The semiconductor element according to claim 1, wherein the semiconductor element is formed by bending and extending in a direction crossing the surface.   The semiconductor element according to claim 1, wherein a deviation in crystal orientation between the base semiconductor layer and the selectively grown buried semiconductor layer is 0.1 ° or less.   At least one III of the group consisting of gallium (Ga), aluminum (Al), boron (B), and indium (In) is formed on the substrate via the base semiconductor layer and the selectively grown buried semiconductor layer. 2. The semiconductor element according to claim 1, wherein a group III nitride compound semiconductor layer containing a group element and nitrogen (N) is formed.   The semiconductor element according to claim 1, wherein the selectively grown embedded semiconductor layer is made of a group III nitride compound semiconductor containing gallium and nitrogen.   The semiconductor element according to claim 4, wherein the substrate is made of sapphire.   The semiconductor element according to claim 4, wherein the substrate is made of silicon carbide (SiC).   The semiconductor device according to claim 4, wherein the substrate is made of single-crystal gallium nitride.   The semiconductor element according to claim 4, wherein the base semiconductor layer is formed directly on the substrate.

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