JP2006019372A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To again form a self-alignment formation region in order to form a hole having a larger opening width in comparison with a diameter of a contact hole formed in an insulating film in a self-alignment formation region by a self-alignment formation technique. Even if it is necessary to perform an etching process, the self-alignment mask film in the self-alignment formation region is not adversely affected, and it is not necessary to embed and form the connection wiring in a plurality of times in the self-alignment formation region. .
After a first contact hole 16 is formed in a region CB2, a multilayer resist structure 41 having a three-layer structure of a photoresist 38, a coating type oxide film 39, and a photoresist 40 is formed, and a fifth silicon is formed. Holes 24 and 25 are formed in the upper portion of oxide film 23.
[Selection] FIG.

Description

  The present invention relates to a semiconductor device for forming a contact hole using a self-alignment forming technique and a method for manufacturing the same.

  In this type of semiconductor device, a contact plug is embedded in an insulating film in order to electrically connect a semiconductor substrate and a wiring layer or a plurality of wiring layers. In order to embed a contact plug in an insulating film, it is necessary to form a contact hole by etching the insulating film, and to embed and form a contact plug in the contact hole. In recent years, the degree of integration has greatly improved, and a self-alignment forming technique has been established in which contact holes are formed by etching using high and low selectivity of film materials.

An application example of these techniques is disclosed in Patent Document 1. According to Patent Document 1, a contact hole reaching the semiconductor substrate is formed by a self-alignment forming technique. Specifically, a resist pattern for forming a bit line contact is formed on an interlayer insulating film (corresponding to the second insulating film), and the interlayer insulating film is etched using this resist pattern as a mask. The contact hole can be formed by a self-alignment forming technique using the mask.
JP-A-11-284138 (pages 6 to 7, FIGS. 4 and 5)

  However, with the recent reduction in design rules, the contact area between the contact plug (connection wiring) and the upper layer wiring (bit line) embedded in the contact hole is small, and the contact plug embedding property deteriorates. A hole having a larger opening width is formed above the contact hole formed in the insulating film, and a contact plug is embedded in the hole and contact hole having a larger opening width. This improves the embedding property.

Therefore, after forming a contact hole by the process disclosed in Patent Document 1, the resist pattern is peeled off, and a mask pattern is formed and etched again from above to form an upper portion of the interlayer insulating film and the upper portion of the contact hole. In addition, a hole having a larger opening width can be formed.
However, by using a self-alignment forming technique, a condition in which a selectivity is obtained between a film used as a mask (corresponding to a first insulating film: hereinafter referred to as a self-aligning mask film) and an interlayer insulating film. When a contact hole is formed in the interlayer insulating film by etching in the step, and after that process, a large mask pattern is formed to open a hole having a larger opening width with respect to the upper portion of the interlayer insulating film, the mask It is difficult to form a pattern on the self-aligned mask film.

Therefore, if etching is performed without forming a mask pattern on the self-alignment mask film, a load is applied to the self-alignment mask film, and in the worst case, holes may be opened in the self-alignment mask film. Even if the hole is not opened, the self-aligned mask film may not satisfy the desired characteristics.
Therefore, manufacturing as follows is also conceivable. That is, after a contact hole is formed by the process disclosed in Patent Document 1, the resist pattern is peeled off, and a region where a contact hole is formed by a self-alignment formation technique (referred to as a self-alignment formation region) After the connection wiring is buried and formed so as to expose the upper part of the insulating film and protect the self-aligned mask film, a hole having a larger opening width is formed in the upper part of the interlayer insulating film, and this hole and contact hole are further formed. A connection wiring is embedded in the substrate.

By applying this method, a hole having a large opening width can be formed in the interlayer insulating film without adversely affecting the self-aligned mask film. However, the application of this technique is not preferable because a process for embedding and forming connection wirings in the self-alignment formation region is separately required and costs are increased.
The present invention has been made in view of the above circumstances, and its object is to provide a hole having a larger opening width than the diameter of a contact hole formed in an insulating film in a self-alignment formation region by a self-alignment formation technique. Even if the self-alignment formation region needs to be etched again to form a portion on the insulating film, the self-alignment mask region in the self-alignment formation region is not adversely affected, and the self-alignment formation region is further reduced. In contrast, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can be configured without the need to bury and form connection wiring in a plurality of times, and a semiconductor device manufactured by this manufacturing method.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of electrode layers on a semiconductor substrate via an insulating film on the substrate, and a step of forming a first insulating film so as to cover the plurality of electrode layers, respectively. A step of forming a second insulating film made of a material different from the first insulating film on the first insulating film formed between the plurality of electrode layers so as to cover the first insulating film; A step of forming a contact hole by etching and removing the second insulating film formed between the plurality of electrode layers under a condition having a high selection ratio with respect to the insulating film by a self-aligning technique; and sandwiching the patterning stopper film A step of forming a plurality of layers of resist from the upper surface of the second insulating film with respect to the contact hole, a step of patterning the resist formed on the upper layer side of the patterning stopper film, Etching the upper part of the second insulating film through the patterning stopper film and the resist formed on the lower layer side of the stopper film using the turning formed resist as a mask, and forming a hole, and contact holes and holes And a step of embedding and forming a contact plug.

  According to the method of manufacturing a semiconductor device of the present invention, a plurality of first electrode layers are separated and formed in a self-alignment formation region on a semiconductor substrate via an insulating film on the substrate, and at the same time, an insulating film on the substrate is formed on the semiconductor substrate. The step of forming the second electrode layer in the non-self-aligned region, the step of forming the first insulating film so as to cover the first and second electrode layers, and the first insulating film are different. A step of embedding a second insulating film made of a material on the first insulating film formed between the plurality of first electrode layers so as to cover the first insulating film; and forming between the plurality of first electrode layers Forming a contact hole in the non-self-aligned formation region at the same time as forming a contact hole in the self-aligned formation region, and a plurality of resists sandwiching a patterning stopper film Forming a contact hole in the self-alignment formation region and the non-self-alignment formation region from above the upper surface of the second insulating film, patterning a resist formed on the upper layer side of the patterning stopper film, and patterning Using the formed resist as a mask, the patterning stopper film and the upper part of the second insulating film around the self-alignment formation region and the non-self-alignment formation region are simultaneously etched through the resist formed on the lower layer side of the stopper film. And a step of embedding and forming a contact plug in the contact hole and the hole.

  A semiconductor device of the present invention includes a plurality of electrode layers formed on a semiconductor substrate via an insulating film on the substrate, a first insulating film formed so as to cover each of the plurality of electrode layers, A second insulating film formed to cover the first insulating film with a material different from that of the first insulating film, and a contact hole formed in the first and second insulating films between the plurality of electrode layers; A hole portion having a diameter larger than the contact hole with respect to an upper portion of the second insulating film, and a contact plug embedded in the contact hole and the hole portion. This insulating film is characterized by being curved so as to protrude upward in the contact hole formation region.

  According to the present invention, the self-alignment formation technique is used to form a hole having a larger opening width than the diameter of the contact hole formed in the insulating film in the self-alignment formation region by the self-alignment formation technique. Even if the region needs to be etched again, the self-alignment mask film in the self-alignment formation region is not adversely affected, and the connection wiring is embedded and formed in multiple times in the self-alignment formation region. There is an excellent effect that it can be configured without necessity.

(First embodiment)
Hereinafter, a first embodiment in which the present invention is applied to a NAND flash memory device and a method for manufacturing the same will be described with reference to FIGS.
FIG. 3 is a schematic plan view showing a partial structure of the memory cell array Ar in the memory cell region M and the structure of the high breakdown voltage transistor Trm formed in the peripheral circuit region P.

  The NAND flash memory device 1 (nonvolatile memory device, semiconductor memory device, semiconductor device) is partitioned into a memory cell region M and a peripheral circuit region P. FIG. 2 shows one mode of a circuit in the memory cell region M. A memory cell array Ar of the NAND type flash memory device includes select gate transistors Trs and Trs connected to the bit line BL side and the source line S side, and a plurality of select gate transistors Trs and Trs connected in series. The memory cell transistor Trn is configured. These memory cell arrays Ar are arranged in the vertical and horizontal directions as shown in FIG. 2 to form a memory cell region M.

On the other hand, as shown in FIG. 3, a relatively high voltage is applied to the peripheral circuit region P as compared with the configuration of the transistor Trn formed in the memory cell region M to drive each memory cell in the memory cell region M. A circuit including a transistor Trm or the like is formed.
In FIG. 3, GC is a control gate electrode wiring, FG is a floating gate electrode, SG is a selection gate wiring, CB is a bit line contact formation region, BL is a bit line, AA is an active area, STI indicates an element isolation region (Shallow Trench Isolation).

FIG. 1A shows a schematic longitudinal side view along the line AA in FIG. 3, and FIG. 1B shows a schematic longitudinal side view along the line BB in FIG. Furthermore, FIG.1 (c) has shown the typical longitudinal cross-sectional side view which follows the CC line | wire in FIG.
In the present embodiment, for the memory cell region M and the peripheral circuit region P, connection wiring layers 5 and 6 for connecting between the bit line BL and the diffusion layers 3 or 4 formed on the silicon semiconductor substrate 2 (contacts of the present invention). The manufacturing method (corresponding to a plug) has the main characteristics, and the characteristics of the part will be described in detail below.

<About structure>
Hereinafter, the structure of each of the transistors Trn and Trs in the memory cell region M and the structure of the transistor Trm in the peripheral circuit region P will be described with reference to FIG.
As shown in FIGS. 1B and 1C, the gate electrode formation region G of each of the transistors Trm, Trn, and Trs is formed on a p-type silicon semiconductor substrate 2 on a substrate insulating film (gate insulating film, A first silicon oxide film 7 as a tunnel insulating film), a first polycrystalline silicon layer 8, a second polycrystalline silicon layer 9, an ONO (Oxide Nitride Oxide) film 10, a third polycrystalline silicon layer 11, A tungsten silicide (WSi) layer 12 and a first silicon nitride film 13 are stacked in that order from the bottom.

  In the selection gate transistor Trs shown in FIG. 1B and the gate electrode formation region G of the transistor Trm in the peripheral circuit region P shown in FIG. 1C, the first to third polycrystalline silicon layers 8 and 9 are formed. 11 are electrically connected to the outside, but this connection form is not shown. Moreover, although the embodiment formed on the p-type silicon semiconductor substrate 2 is shown, this may be formed in the p-well region, or may be formed on the reverse-conductivity-type silicon semiconductor substrate if necessary. Also good.

The first silicon oxide film 7 in the memory cell region M is formed with a thickness of, for example, 8 nm, and functions as a first gate insulating film of each of the transistors Trs and Trn. The first silicon oxide film 7 in the peripheral circuit region P is formed thicker than the first silicon oxide film in the memory cell region M, and has a thickness of 40 nm, for example.
The first and second polycrystalline silicon layers 8 and 9 are formed to have a thickness of, for example, 100 nm by stacking polycrystalline silicon doped with p-type impurities. In the memory cell region M, the first and second polycrystalline silicon layers 8 and 9 are formed. As shown in FIG. 1A, it functions as a floating gate electrode FG of the transistor Trn.

  The ONO film 10 is also formed on the side wall of the second polycrystalline silicon layer 9 as shown in FIG. The ONO film 10 includes the first and second polycrystalline silicon layers 8 and 2 together with the second silicon oxide film 14 and the first silicon oxide film 7 that function as an element isolation film embedded in the element isolation region (STI). For example, a film thickness of 17 nm (Oxide 5 nm: SiN 7 nm: Oxide 5 nm) is formed so as to cover 9. The ONO film 10 includes the first and second polycrystalline silicon layers 8 and 9, the third polycrystalline silicon layer 11, the tungsten silicide layer 12 (the floating gate electrode FG and the control) in the gate electrode formation region G of the transistor Trn. It is formed to keep the gate electrode GC) electrically high resistance.

At this time, the floating gate electrode FG and the control gate electrode GC formed in the memory cell region are collectively defined as a plurality of first electrode layers. The first and second polycrystalline silicon layers 8 and 9 formed in the peripheral circuit region, the third polycrystalline silicon layer 11 and the tungsten silicide layer 12 are collectively defined as a second electrode layer.
The third polycrystalline silicon layer 11 is formed with a thickness of, for example, 100 nm from polycrystalline silicon doped with p-type impurities. The third polycrystalline silicon layer 11 functions as the control gate electrode GC together with the tungsten silicide layer 12 in the gate electrode formation region G of the transistor Trn. In the gate electrode formation region G of the transistor Trs, the third polycrystalline silicon layer 11 functions as a selection gate electrode SG together with the first and second polycrystalline silicon layers 8 and 9 and the tungsten silicide layer 12, so-called word. Configured as a line. The first to third polycrystalline silicon layers 8, 9, and 11 may each be formed of amorphous silicon instead of polycrystalline silicon.

The tungsten silicide layer 12 is formed with a film thickness of 70 nm, for example. The first silicon nitride film 13 is formed with a film thickness of 300 nm, for example.
In the region CB2 in the memory cell region M, a second silicon nitride film 15 is formed on the side walls of these layers 7-13. This region CB2 corresponds to the formation region of the contact hole 16 of the present invention.

The first and second silicon nitride films 13 and 15 are formed so as to be convex upward in the region CB2 formed between the gate electrode formation regions G, and are self-aligning mask films. Function as.
In the memory cell region M, a third silicon nitride film 20 is formed on the first silicon nitride film 13 in the region CB1, which is a region larger than the region CB2.

  On the other hand, in the peripheral circuit region P, the second silicon oxide film 17 is formed on the side wall of the gate electrode formation region G among the layers 7 to 13, and further, the third silicon oxide film 18 is the second silicon oxide film 18. It is formed so as to cover the silicon oxide film 17. A second silicon nitride film 19 is formed on the outer wall of the third silicon oxide film 18. Further, a third silicon nitride film 20 is formed so as to cover the second silicon nitride film 19 and the third silicon oxide film 18.

  In the memory cell region M, second and third silicon oxide films 17 and 18 are formed on the first silicon nitride film 13 outside the region CB1. A second silicon nitride film 19 is formed on the side wall of the third silicon oxide film 18. A third silicon nitride film 20 is formed so as to cover the layers 7 to 12 (control gate electrode GC, floating gate electrode FG).

  In the memory cell region M, a BPSG film 22 (fourth silicon oxide film: equivalent to the second insulating film of the present invention) is buried between the third silicon nitride films 20 in the plurality of gate electrode formation regions G. Is formed. The BPSG film 22 is buried below the upper surface of the third silicon nitride film 20 covered with the layers 7 to 13, and together with a fifth silicon oxide film 23 described later, a third silicon nitride film. 20 is formed so as to cover 20. On the BPSG film 22 and the third silicon nitride film 20, a fifth silicon oxide film 23 (corresponding to the second insulating film of the present invention) is formed as an interlayer insulating film. The fifth silicon oxide film 23 is formed with a film thickness of 350 [nm], for example.

  In the memory cell region M, a first contact hole 16 is formed in a region CB2 between the plurality of gate electrode formation regions G. The first contact hole 16 has an upper part formed in an elliptical columnar shape, and a lower part formed in an elliptical columnar shape whose diameter is smaller than the diameter of the elliptical column formed in the upper part. A hole 24 is formed in the upper part of the fifth silicon oxide film 23 in the region CB4 including the upper part of the first contact hole 16. As shown in FIG. 1B, the region CB4 is a region including the region CB2.

  On the other hand, as shown in FIG. 1C, a second contact hole 28 is formed in a region CB5 adjacent to the gate electrode formation region G in the peripheral circuit region P. The region CB5 is a region including the region CB3. The second contact hole 28 is formed in a vertically long elliptical column shape from the middle of the fifth silicon oxide film 23 to the silicon semiconductor substrate 2 below the fifth silicon oxide film 23. A hole 25 is formed in the upper part of the second contact hole 28.

  In the memory cell region M and the peripheral circuit region P, a titanium layer 26 is embedded in the holes 24 and 25 and the first and second contact holes 16 and 28. A tungsten layer 27 is embedded on the titanium layer 26. The titanium layer 26 is formed as a barrier metal so that the tungsten layer 27 and other films do not come into contact with each other. Connection wiring layers (contact plugs) 5 and 6 are formed by the titanium layer 26 and the tungsten layer 27. The tungsten layer 27 functions as an electrode material and is electrically connected to an upper wiring (not shown).

<Detailed manufacturing method>
Hereinafter, a detailed manufacturing method will be described with reference to FIGS. In addition, about drawing which attached | subjected the same subscript (a)-(c) in drawing of FIGS. 4-13, the AA line, the BB line, and CC line in the top view of FIG. 3, respectively. The longitudinal side view along line is shown. In addition, as long as the manufacturing method of this invention is realizable, the process demonstrated later may be skipped as needed.

(1) Step of Forming the Structure Shown in FIG. 4 In the memory cell region M, the first silicon oxide film 7 is formed, for example, 8 [nm] on the p-type silicon semiconductor substrate 2, and the peripheral circuit region P In the region where the high breakdown voltage transistor Trm is to be formed, the first silicon oxide film 7 is formed, for example, 40 [nm]. Then, a first polycrystalline silicon film 8 doped with a p-type impurity is formed, for example, by 40 [nm] by low pressure chemical vapor deposition (CVD), and a fourth silicon nitride film 30 is formed, for example, by 90 Then, a sixth silicon oxide film 31 is formed, for example, 230 [nm].

  And a resist (not shown) is apply | coated on it and the said resist is formed in a desired mask pattern (not shown) with a lithography technique. Then, the sixth silicon oxide film 31, the fourth silicon nitride film 30, the first polycrystalline silicon film 8, the first silicon oxide film 7, and the sixth silicon oxide film 31, by the RIE (Reactive Ion Etching) method using the mask pattern as a mask. By forming a groove in the silicon semiconductor substrate 2, a groove portion 32 for forming the element isolation region STI is formed.

  Thereafter, by heating in an oxidizing atmosphere, a seventh silicon oxide film 33 of 6 [nm], for example, is formed on the exposed sidewall of the groove 32. Next, an eighth silicon oxide film 34 of 550 [nm], for example, is deposited so as to be embedded in the groove 32 by HDP (High Density Plasma) method. Then, it is formed as shown in FIG.

(2) Regarding Step of Forming Structure shown in FIG. 5 After completion of the formation step of (1), the eighth and sixth silicon oxide films 34 and 31 are CMP (Chemical) until the fourth silicon nitride film 30 is exposed. It is flattened by a mechanical polishing method and heated in a nitrogen atmosphere at, for example, 900 ° C.

Next, with the fourth silicon nitride film 30 as a mask, the eighth silicon oxide film 34 is etched by, for example, 10 [nm] by buffered hydrofluoric acid (HF) treatment, and then, for example, by phosphoric acid treatment at 150 ° C. The fourth silicon nitride film 30 is removed. In this way, the element isolation region STI mainly composed of the second silicon oxide film 14 is formed.
Further, the second polycrystalline silicon film 9 is formed, for example, by 60 [nm] by the low pressure CVD method, and the ninth silicon oxide film 35 is formed, for example, by 130 [nm], and a resist (not shown) is further formed. It is applied to form a desired mask pattern (not shown) by lithography, and the ninth silicon oxide film 35 is etched by RIE (Reactive Ion Etching) using the mask pattern as a mask.

  At this time, the ninth silicon oxide film 35 is formed on the second polycrystalline silicon film 9 between the element isolation regions STI, and the ninth silicon oxide film formed immediately above the element isolation region STI. The film 35 is removed. Then, after removing the resist, a tenth silicon oxide film 36 is formed, for example, by 45 [nm] by low pressure CVD. Then, it is formed as shown in FIG.

(3) Regarding Step of Forming Structure Shown in FIG. 6 After completion of the formation step of (2), the ninth and tenth silicon oxide films 35 and 36 are etched back by the etch back method. Then, the ninth and tenth silicon oxide films 35 and 36 formed immediately above the element isolation region STI are removed, and the second polycrystalline silicon film 9 is exposed.

Using the ninth and tenth silicon oxide films 35 and 36 formed between the element isolation regions STI as a mask, the second polycrystalline silicon film 9 is etched by the RIE method. Thereafter, the ninth and tenth silicon oxide films 35 and 36 formed as a mask with HF vapor are removed.
Further, an ONO film (second gate insulating film) 10 is formed to 17 nm, for example, by low pressure CVD, and heated in an oxidizing atmosphere. Thereafter, a third polycrystalline silicon film 11 is formed, for example, at 80 [nm] by low pressure CVD, and a tungsten silicide (WSi) layer 12 is formed thereon by PVD (Physical Vapor Deposition). Further, a first silicon nitride 13 is formed thereon, for example, 300 [nm] by low pressure CVD.

  A resist (not shown) is applied thereon, the resist is processed into a predetermined mask pattern by lithography, and the first silicon nitride film 13 is removed by etching using the mask pattern as a mask by RIE. . Specifically, in the memory cell region M and the peripheral circuit region P, the first silicon nitride except for the gate electrode formation region G (see FIGS. 6B and 6C) of the transistors Trs, Trn, and Trm. The ride film 13 is removed.

  Thereafter, the resist is stripped, and the tungsten silicide film 12, the third polycrystalline silicon film 11, the ONO film 10, the second and first polycrystalline silicon films are formed by the RIE method using the first silicon nitride film 13 as a mask. 9 and 8 are processed. Further, by heating in a nitrogen atmosphere at 800 ° C. and subsequently in an oxidizing atmosphere, the second silicon oxide film 17 is formed, for example, 6 [nm]. By this processing step, a structure as shown in FIG. 6 is formed.

  Then, as shown in FIG. 6, the second polycrystalline silicon film 9 formed on the element isolation region STI is removed, and the first and second polycrystalline silicon films 8 and 9 are divided. The floating gate electrode FG is divided into a plurality (formation of a plurality of electrode layers).

(4) Process for forming the structure shown in FIG. 7 After the formation process shown in (3), source / drain diffusion layers 21 are formed by ion implantation of p-type impurities. Further, a third silicon oxide film 18 is formed on the entire surface, for example, 20 [nm], a resist (not shown) is applied thereon, a predetermined resist pattern is formed on this resist, and diluted Bufferd hydrofluoric acid (HF 2), the second and third silicon oxide films 17 and 18 formed in the region CB1 which becomes a part of the bit line contact formation region of the memory cell region M are removed.

Next, the density of the second and third silicon oxide films 17 and 18 is increased by heating in an oxygen atmosphere by RTA (Rapid Thermal Annealing). A second silicon nitride film (see reference numerals 15 and 19) is formed, for example, by 20 [nm] by low pressure CVD, and the entire surface of the second silicon nitride film is etched back by RIE.
Then, as shown in FIG. 7B, in the region CB 1 of the memory cell region M, the first to third polycrystalline silicon films 8, 9, 11, the tungsten silicide film 12, the ONO film 10, the first The second silicon nitride film 15 remains on the outer wall of the silicon nitride film 13. Further, in the region other than the region CB1, the second silicon nitride film 19 remains on the outer wall of the third silicon oxide film 18.

Thereafter, a third silicon nitride film 20 is further formed, for example, at 20 [nm] on the entire surface by a low pressure CVD method, and heated in an oxygen atmosphere at 850 ° C., for example. As a result, the structure shown in FIG. 7 is formed.
(5) Step of forming the structure shown in FIG. 8 After the step of forming (4), a BPSG film 22 (second insulating film of the present invention) is buried and formed by atmospheric pressure CVD. At this time, as shown in FIGS. 8B and 8C, a BPSG film 22 is embedded between the third silicon nitride films 20 between the gate electrode formation regions G of the transistors Trs and Trn. As a result, the BPSG film 22 is also buried in the region CB1.

  Then, the BPSG film 22 is planarized by CMP until the third silicon nitride film 20 is exposed. Then, a fifth silicon oxide film 23 is formed thereon as an interlayer insulating film by a plasma CVD method, for example, with a thickness of 350 nm, and then heated in a nitrogen atmosphere at 970 ° C. As a result, the structure shown in FIG. 8 is formed.

  After forming the structure shown in (5), as shown in FIG. 9, a resist 37 is applied thereon, and the resist 37 is processed into a predetermined mask pattern by a lithography technique. This mask pattern shows a pattern in which the region CB2 for forming the first contact hole 16 is opened in the memory cell region M by the self-alignment forming technique, and the second pattern is formed in the peripheral circuit region P by the non-self-alignment forming technique. A pattern in which a region CB3 (non-self-alignment formation region) for forming the contact hole 28 is opened is shown.

Then, as shown in FIG. 10, the fifth silicon oxide film 23, the BPSG film 22 and the first silicon oxide film 7 are removed by etching using the mask pattern as a mask by the RIE method, and the exposed silicon semiconductor substrate. 2, source / drain diffusion layers 3 and 4 are formed by ion implantation of p-type impurities.
In this case, as shown in FIG. 10B, the first contact hole 16 is formed in the region CB2 by a self-alignment forming technique. Specifically, the fifth silicon oxide film 23 and the BPSG film 22 are etched under conditions that provide a high selectivity with respect to the silicon nitride film. As shown in FIG. 3, the region CB2 is formed in an elliptical shape in a plan view (three-dimensionally elliptical columnar shape). The ellipse has a minor axis of, for example, 90 [nm] (word line formation direction: gate electrode formation direction). This region CB2 corresponds to a self-alignment formation region.

  In this case, in the region CB2 of the memory cell region M, since the fifth silicon oxide film 23 and the BPSG film 22 are etched by the self-alignment forming technique, the second and third silicon nitride films are removed. As shown in FIG. 10, the shoulders A (see FIG. 10 (b)) are removed as shown in FIG. 10, but the films 8, 9, 10, 11 and 12 constituting the gate electrode of the selection gate transistor Trs are removed. The second and third silicon nitride films 15 and 20 remain on the side walls.

On the other hand, in the peripheral circuit region P, as shown in FIG. 10C, the self-alignment forming technique is used for the region CB3 for forming a contact plug between the silicon semiconductor substrate 2 and the upper layer wiring (not shown). The second contact hole 28 is formed in a cylindrical shape without using (hereinafter referred to as a non-self-alignment forming technique).
The region CB2 in the memory cell region M is etched by the self-alignment technique, and the region CB3 in the peripheral circuit region P is etched by the non-self-alignment formation technique. If the etching conditions for the region P match, the etching process may be performed simultaneously as necessary, or may be performed in a separate process.

Thereafter, the resist 37 is removed, a dopant is implanted into the regions CB2 and CB3 by ion implantation, and the dopant is activated by heating in a nitrogen atmosphere at 970 ° C.
By the way, as shown in FIGS. 1B and 1C, the completed structure before the step of forming the upper layer wiring (not shown) is performed. As shown in FIGS. A hole portion 24 of a region CB4 having a larger opening diameter is formed in the upper portion of the region, and a titanium film 26 and a tungsten layer 27 are embedded in the region CB4 to improve the embedding property. Instead of the titanium layer 26, a TiN layer may be formed. The region CB4 is formed in an elliptic cylinder shape having a major axis of 800 [nm].

  Therefore, after forming the structure shown in FIG. 10, a resist (not shown) is formed by patterning on the fifth silicon oxide film 23, and the upper portion of the fifth silicon oxide film 23 is etched in the region CB4. When the hole 24 is simply formed, the silicon nitride film on the shoulder A is further removed even though the shoulder A of the second and third silicon nitride films 15 and 20 is formed thin. Will come to be. When the shoulder A is formed thin, if the silicon oxide film removed by etching in the above-mentioned process remains between the first and second silicon nitride films 13 and 15, the etching process is performed by this silicon oxide film. There is a risk of reaching the tungsten silicide layer 12 through the film.

  Specifically, after the first contact hole 16 is formed by the self-alignment forming technique, the remaining film of the silicon nitride film is only about 300 to 400 [ナ イ ト] in the manufacturing method of the present embodiment. It does not remain. Although it may be possible to maintain the insulation performance by increasing the thickness of the first silicon nitride film 13 that functions as a self-aligning mask film, if the thickness of the first silicon nitride film 13 is excessively increased. Since the aspect ratio becomes high, it becomes difficult to form the first and second contact holes 16 and 28 in a desired shape, and the thickness of the first silicon nitride film 13 cannot be increased.

  That is, when the hole 24 is formed by simply etching the upper portion of the fifth silicon oxide film 23 in the region CB4, in the worst case, the etching is removed up to the tungsten silicide film 12 of the gate electrode of the transistor Trs. It will end up. Thereafter, if the connection wiring layer 5 is embedded in the region CB4, the connection wiring layer 5 is embedded so as to come into contact with the tungsten silicide film 12, which causes a problem.

  Furthermore, another method includes the following method. That is, after the structure shown in FIG. 10 is formed, a polycrystalline silicon layer or the like is previously provided above the shoulder A and below the upper surface of the fifth silicon oxide film 23 with respect to the region CB2 so that the shoulder A is not exposed. A method is also conceivable in which the upper part of the fifth silicon oxide film 23 is opened after the connection wiring (not shown) is buried. However, after that, it is necessary to bury and form the connection wiring further from the upper surface of the fifth silicon oxide film 23, and it is necessary to bury and form the connection wiring layer 5 in a plurality of times. Resulting in.

  Therefore, in this embodiment, the upper portions of the fifth silicon oxide film 23 are opened to form the holes 24 and 25 by the following process. That is, after the structure shown in FIG. 10 is formed, as shown in FIG. 11, while the semiconductor wafer is spun, a photoresist 38 (lower layer resist) is removed from the upper surface of the fifth silicon oxide film 23 (interlayer insulating film), for example, 500 [Nm] Form up to the top. This photoresist 38 is a coating-type resist made of a resin, a photo / acid generator, a mixture of cyclohexane and a crosslinking material, and is formed in the region CB2 of the memory cell region M and the region CB3 of the peripheral circuit region P. And it will also be deposited in the second contact holes 16 and 28.

Further, a coating type oxide film 39 (interresist film: exposure stopper film: patterning stopper film) is formed on the entire surface, for example, by 110 nm. The coating type oxide film 39 is composed of a mixture of polysiloxane, a light / acid generator, propylene glycol monoethyl ether, propylene glycol monopropyl ether, and water.
Further, a photoresist 40 (upper layer resist) is applied thereon. The photoresist 40 is composed of a mixture of polymethacrylate, light / acid generator, ethyl lactate and methoxypropyl acerate. After applying the photoresist 40, the photoresist 40 is exposed by a lithography technique through a mask (not shown). In this case, since the coating type oxide film 39 functions as an exposure stopper film when exposing the photoresist 40, only the photoresist 40 on the upper layer side of the coating type carbon film 39 can be patterned.

  Then, as shown in FIG. 11, the periphery of the self-alignment formation region of the region CB4 having a larger diameter than the region CB2 (corresponding to the self-alignment formation region) is patterned and formed in the photoresist 40, and at the same time, the region CB3 (non-self-alignment). The photoresist 40 is formed by patterning around the non-self-aligned formation region of the region CB5 having a larger diameter than the formation region.

In this manner, a multilayer resist structure 41 is formed by the photoresists 38 and 40 and the coating type oxide film 39. The region CB3 is an elliptical region having a major axis of, for example, 100 to 200 [nm] in plan, the region CB5 is a region including at least the region CB3, and the major axis is, for example, 200 to 300 [ nm] elliptical region.
Thereafter, using the patterned upper resist 40 as a mask, holes 24 and 25 are formed in the region CB4 and the region CB5 over the coating type oxide film 39, the photoresist 38, and the fifth silicon oxide film 23 by the RIE method. Process simultaneously. At this time, as shown in FIG. 12, the depth d of the holes 24 and 25 is processed to be, for example, 200 [nm] (2000 mm).

  Then, although not shown, in the stage before processing the holes 24 and 25, the lower-layer side photoresist 38 formed in the first and second contact holes 16 and 28 is made into the first to third silicon. Since the nitride films 13, 15, and 20 are formed up to the upper side, when the holes 24 and 25 are processed through the lower-layer photoresist 38 thereafter, the lower-layer photoresist 38 is removed from the bottom surfaces of the holes 24 and 25. However, the shoulders A of the second and third silicon nitride films 15 and 20 can be machined to a desired depth without further shaving. Therefore, the first to third silicon nitride films 13, 15 and 20 are not scraped off and the insulating function can be maintained.

Thereafter, the lower photoresist 38 formed in the regions CB2 and CB3 is simultaneously removed, a dopant is implanted into a predetermined region by an ion implantation method, and heated in a nitrogen atmosphere at 800 ° C. for 10 minutes to activate the dopant. As a result, the diffusion layers 3 and 4 are formed.
Further, as shown in FIG. 13B and FIG. 13C, a titanium (Ti) film 26 is formed, for example, by 45 [nm] by the PVD method, and in a nitrogenous atmosphere containing hydrogen at 550 ° C. for 90 minutes. Heat in. Then, a tungsten (W) film 27, for example, 400 [nm] is formed thereon by the PVD method. Then, the titanium layer 26 and the tungsten layer 27 are formed simultaneously with respect to the memory cell region M and the peripheral circuit region P. Thereafter, the tungsten (W) layer 27 is planarized by CMP until the fifth silicon oxide film 23 is exposed, and heated in a nitrogen atmosphere containing hydrogen at 400 ° C. for 30 minutes.

  According to the manufacturing method of the present embodiment, the lower-layer side photoresist 38 is formed above the fifth silicon oxide film 23 so as to cover and protect the first to third silicon nitride films 13, 15 and 20. Then, the coating type oxide film 39 and the upper layer side photoresist 40 are coated thereon, the upper layer side photoresist 40 is patterned and formed, and the upper layer side photoresist 40 is used as a mask to coat the coating type oxide film 39 and the lower layer side photoresist. Since holes 24 and 25 are formed in the upper portion of the fifth silicon oxide film 23 via the resist 38, the opening width is further increased with respect to the first contact hole 16 formed in the region CB2 by the self-alignment forming technique. Even if it is necessary to further etch the inside of the region CB2 when forming the hole 24 in the large region CB4, the lower layer side Since the resist 38 acts to protect the first to third silicon nitride films 13, 15 and 20 in the region CB2, the insulation performance of the first to third silicon nitride films 13, 15, and 20 is improved. It can be held.

Moreover, since the titanium layer (Ti) 26 and the tungsten (W) layer 27 can be simultaneously embedded in the memory cell region M and the peripheral circuit region P, the cost can be reduced without increasing the number of processes. Can be reduced.
Furthermore, according to such a manufacturing method, the first to third silicon nitride films 13, 15 and 20 do not need to be thicker than the conventional film thickness. Thus, when the first contact hole 16 is formed in the BPSG film 22 embedded in the region CB2, the first contact hole 16 can be easily formed because the first contact hole 16 can be formed with a low aspect ratio. Become.

(Second Embodiment)
FIG. 14 shows an explanatory diagram of the second embodiment of the present invention. The difference from the first embodiment is that a coating type antireflection film is applied instead of the coating type carbon film. The same parts as those of the first embodiment are denoted by the same reference numerals and only different parts will be described below.
After the formation process of FIG. 10, a coating type antireflection film 42 is formed in the first and second contact holes 16 and 28. This coating type antireflection film 50 is formed of a film mainly composed of ethyl lactate and methoxypropyl acetate, and is formed at least above the upper surface of the fifth silicon oxide film 23.

  Then, a photoresist 51 is applied thereon, and as shown in FIG. 14, the photoresist 51 is formed in a predetermined pattern by lithography technology so that the regions CB6 and CB7 are opened. At this time, the coating-type antireflection film 50 functions as a patterning stopper film when patterning is performed, and as shown in FIG. 14, the photoresist 51 is opened in the regions CB6 and CB7. The region CB6 is formed by a region including at least the region CB2, and is a region formed with a large diameter (for example, a long diameter of 800 [nm] and a short diameter of 420 [nm]).

Further, the coating type antireflection film 42 and the fifth silicon oxide film 23 are etched by the RIE method using the pattern of the photoresist 51 as a mask, whereby holes 24 and 25 are formed in the upper portion of the fifth silicon oxide film 23. Form. About the process after forming the hole parts 24 and 25, since it is the same as that of 1st Embodiment, the description is abbreviate | omitted.
According to the method of manufacturing a semiconductor device according to the present embodiment, the coating type antireflection film 50 is buried in the first and second contact holes 16 and 28 up to the upper surface of the fifth silicon oxide film 23, Since the photoresist 51 is applied thereon, the photoresist 51 is patterned, and the holes 24 and 25 are formed in the upper portion of the fifth silicon oxide film 23 using the photoresist 51 as a mask. It is possible to avoid formation of holes in the silicon nitride films 13, 15 and 20.

  In addition, when the titanium layer 26 and the tungsten layer 27 are buried in the first and second contact holes 16 and 28 in the regions CB6 and CB7, it is not necessary to bury them in a separate process, and they can be buried at the same time. .

(Other embodiments)
The present invention is not limited to the embodiment described above, and can be modified or expanded as described below, for example.
Although the embodiment applied to the NAND type flash memory device 1 has been shown, it is a semiconductor device having a plurality of electrode layers (for example, gate electrodes of MOS transistors) on a silicon semiconductor substrate 2 via an insulating film on the substrate. Any semiconductor device may be used as long as it is present. That is, the present invention may be applied to a NOR type flash memory device, a nonvolatile memory device, a DRAM semiconductor memory device, an SRAM semiconductor memory device, and the like.
Although the embodiment in which the connection wiring layer 5 is formed by the titanium layer 26 and the tungsten layer 27 has been shown, aluminum (Al), copper (Cu), silver is used instead of the titanium (Ti) layer 26 and the tungsten (W) layer 27. You may form with any material of (Ag).

Schematic sectional view showing the first embodiment of the present invention ((a) is a sectional view taken along line AA in FIG. 3, (b) is a sectional view taken along line BB in FIG. 3, (c) ) Is a cross-sectional view taken along line CC in FIG. Electrical configuration in memory cell area Schematic plan view The figure which shows one manufacturing process (the 1) Diagram showing one manufacturing process (2) Diagram showing one manufacturing process (3) The figure which shows one manufacturing process (the 4) The figure which shows one manufacturing process (the 5) The figure which shows one manufacturing process (the 6) The figure which shows one manufacturing process (the 7) The figure which shows one manufacturing process (the 8) The figure which shows one manufacturing process (the 9) The figure which shows one manufacturing process (the 10) FIG. 11 equivalent view showing the second embodiment of the present invention

Explanation of symbols

  In the drawings, 1 is a NAND flash memory device (semiconductor device), 2 is a silicon semiconductor substrate (semiconductor substrate), 5 is a connection wiring layer (contact plug), 7 is a first silicon oxide film (insulating film on the substrate), 13 is a first silicon nitride film (first insulating film), 15 is a second silicon nitride film (first insulating film), 16 is a first contact hole, and 20 is a third silicon nitride film. Film (first insulating film), 22 is a BPSG film (second insulating film), 23 is a fifth silicon oxide film (second insulating film), 24 and 25 are holes, and 28 is a second contact. Holes 38 are photoresist (lower resist), 39 is a coating type oxide film (patterning stopper film), 40 is photoresist (upper resist), CB2 is a region (self-alignment formation region), CB3 Region (non-self-aligned formation region), GC is a control gate electrode (electrode layer), FG denotes a floating gate electrode (electrode layer).

Claims (5)

Forming a plurality of electrode layers on a semiconductor substrate via an insulating film on the substrate;
Forming a first insulating film so as to cover each of the plurality of electrode layers;
Burying a second insulating film made of a material different from that of the first insulating film on the first insulating film formed between the plurality of electrode layers so as to cover the first insulating film;
Forming a contact hole by etching away the second insulating film formed between the plurality of electrode layers under a condition having a high selectivity with respect to the first insulating film by a self-alignment forming technique; ,
Forming a plurality of resist layers sandwiching a patterning stopper film from above the upper surface of the second insulating film with respect to the contact hole;
Patterning a resist formed on the upper side of the patterning stopper film;
Etching the upper part of the second insulating film through the resist formed on the lower layer side of the patterning stopper film and the stopper film using the patterned resist as a mask, and forming a hole;
And a step of embedding and forming a contact plug in the contact hole and the hole. A plurality of first electrode layers are separated on a semiconductor substrate via an insulating film on the substrate and are formed in a self-alignment formation region, and at the same time, a second electrode layer is non-self formed on the semiconductor substrate via an insulating film on the substrate. Forming in the alignment formation region;
Forming a first insulating film so as to cover each of the first and second electrode layers;
Forming a second insulating film made of a material different from that of the first insulating film on the first insulating film formed between the plurality of first electrode layers so as to cover the first insulating film; When,
Forming a contact hole in the non-self-alignment formation region simultaneously with forming a contact hole by a self-alignment formation technique for the self-alignment formation region formed between the plurality of first electrode layers;
Forming a plurality of resists sandwiching a patterning stopper film from above the upper surface of the second insulating film with respect to the contact holes in the self-alignment formation region and the non-self-alignment formation region;
Patterning a resist formed on the upper side of the patterning stopper film;
The upper part of the second insulating film around the self-alignment formation region and the non-self-alignment formation region through the patterning stopper film and the resist formed on the lower layer side of the stopper film using the patterned resist as a mask Simultaneously etching to form a hole,
And a step of embedding and forming a contact plug in the contact hole and the hole. A plurality of electrode layers formed on a semiconductor substrate via an insulating film on the substrate;
A first insulating film formed so as to cover each of the plurality of electrode layers;
A second insulating film formed to cover the first insulating film with a material different from the first insulating film;
Contact holes formed in the first and second insulating films between the plurality of electrode layers;
A hole formed in a diameter larger than the contact hole with respect to the upper portion of the second insulating film;
A contact plug embedded in the contact hole and the hole, and
The semiconductor device according to claim 1, wherein the first insulating film is curved so as to protrude upward in the contact hole formation region.   The semiconductor device according to claim 3, wherein the first insulating film is formed of a silicon nitride film. 4. The semiconductor device according to claim 3, wherein the second insulating film is formed of a silicon oxide film.

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