JP2006018863A - Semiconductor device, memory card, and storage - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the time required for rewriting of stored information when information storage of binary is performed in place of information storage of multi-values. <P>SOLUTION: The semiconductor device has a control circuit (10) for performing the information storage of binary or the information storage of four value or higher multi-values into a nonvolatile memory cell by performing control to lower the threshold voltage of the nonvolatile memory cell and control to raise the same. The control circuit performs the control in such a manner that the read-out determination level with respect to the non-volatile memory cell to raise the threshold voltage when performing the binary information storage attains the level between the highest threshold voltage distribution and the next highest threshold voltage distribution in the multi-value information storage. The width of the distribution of the lower threshold voltage is approximately 3/4 or over of the entire part of the threshold voltage distribution in the binary information storage and therefore the possibility that such an excessive erase state as to make the threshold voltage lower than the threshold voltage distribution is resulted in an erase processing step is low. If the number of the nonvolatile memory cells in which the excessive erase state is resulted in the erase processing step is small, the time required for a rewriting processing is drastically reduced. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device capable of storing multi-value information such as four values and binary information, and relates to a technique effective when applied to, for example, a nonvolatile memory card.

  Patent Document 1 describes a flash memory that can perform storage information storage using four values and information storage using binary values. According to this, when a binary read operation (direct flash access) is designated by a command, the storage information stored in one memory cell is read as 1-bit storage information. That is, the information storage for the memory cell subject to direct flash access is performed in the erased state (the lowest threshold voltage distribution state) or the third write state with the highest threshold voltage distribution in consideration of a large read operation margin. Select from the following two states. In the read operation, the voltage between the erased state and the third written state is used as a read word line voltage, and the storage information read out as it is used as read data for binary storage information. As a result, the operation of converting the storage information read from the memory cell from multi-value to binary is omitted, and the time until data is read out can be shortened. For example, if the direct flash access target is data in the management area for the sector data of the file, the validity of the sector data, the presence / absence of substitution, and the like can be determined quickly, so that the file access can be speeded up.

WO 03 / 085676A1 International Publication Pamphlet (Fig. 14)

  The present inventor has studied a flash memory capable of storing information with four values and storing information with two values. In particular, studies were made on using binary storage to store data that requires high reliability for information storage or data that requires security, and that it takes less time than quaternary storage.

  The first consideration is to store data in a short time. As described in the above-mentioned patent document, the read threshold level for a nonvolatile memory cell whose threshold voltage is controlled to be high when information is stored in binary, the highest threshold voltage distribution and the lowest threshold voltage in multi-value information storage When the storage information is rewritten, when the memory cell is erased from the highest threshold voltage distribution state to the lowest threshold voltage distribution state, the same processing time as when performing four-level information storage is performed. Is required. The width of the lowest threshold voltage distribution must be as narrow as in the case of multi-value information storage. For this purpose, it is necessary to perform a process of writing back to the over-erased memory cells in units of bits. Because it becomes. It has been found by the present inventor that rewriting to a storage area requiring security is desirably completed in a short time due to its nature, and that the processing time is long and insufficient to satisfy such a requirement. .

  The second consideration is over-erasure measures. As the width of the lowest threshold voltage distribution in the erased state is narrowed, the number of overerased memory cells to be written back in the erase process increases. If the power is cut off before writing back, the over-erased memory cells will remain, and depending on the structure of the memory cell array, not only the information read from the address to be erased but also the read operation from other addresses In this case, there is a possibility that data cannot be read properly. In particular, it is desirable that such defects due to over-erasure are unlikely to occur when storing data that requires high reliability for information storage. It is sufficient to take another over-erase countermeasure such as disabling the memory cell being erased when the power is cut off. However, if such an over-erase countermeasure is taken, it takes time, and the stored information This is contrary to the request for shortening the rewrite processing time. Eventually, even if measures against over-erasure are taken, over-erasure will not occur in the erasure process as much as possible when binary storage with a larger read margin than 4-value storage is used for storing highly reliable data. Has been found by the present inventor. Such power interruption occurs, for example, when the memory card is removed from the card slot during rewriting of the memory card.

  It is an object of the present invention to shorten the time required for erasing or rewriting stored information when performing binary information storage instead of multi-value information storage in a semiconductor device, memory card or storage device.

  Another object of the present invention is to make it difficult to cause an over-erased state in the erasing process when performing binary information storage instead of multi-value information storage in a semiconductor device, memory card or storage device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] The semiconductor device performs a control of lowering and increasing a threshold voltage of the nonvolatile memory cell by performing a memory array including a plurality of nonvolatile memory cells storing information according to a difference in threshold voltage. And a control circuit for storing binary information or multi-value information of four or more values in the memory cell. The control circuit is a level between the highest threshold voltage distribution and the next highest threshold voltage distribution in the information storage having a multi-level read determination level for the nonvolatile memory cell that increases the threshold voltage when storing information in binary. Control to become.

  From the above, there is a higher threshold voltage distribution on the upper side, with the read determination level between the highest threshold voltage distribution and the next higher threshold voltage distribution in multi-value information storage as the boundary, and on the lower side Since the distribution with the lower threshold voltage exists, the width of the distribution with the lower threshold voltage is approximately 3/4 or more of the entire threshold voltage distribution. When rewriting the stored information, when the higher threshold voltage distribution is initialized to the lower threshold voltage distribution, the allowable width of the lower threshold voltage distribution is approximately 3/4 or more of the whole, and during the erasing process, The over-erased state in which the threshold voltage is lower than the lower threshold voltage distribution is not entered, or even if it is, the ratio becomes extremely small. Furthermore, if the number of non-volatile memory cells that are over-erased during the erasing process decreases, the time required for the write-back process for each memory cell is significantly shortened, and the write process time for increasing the threshold voltage for each memory cell is also increased. As a result, the time required for rewriting stored information can be shortened.

  In a specific form of the invention, the control circuit sets the verify level for the non-volatile memory cell that lowers the threshold voltage when information is stored in binary as the upper base level of the next highest threshold voltage distribution. Good. The process for decreasing the threshold voltage is an erasing process for reducing the number of electrons held in the nonvolatile memory cell, and the process for increasing the threshold voltage is a writing process for increasing the number of electrons held in the nonvolatile memory cell.

  A memory card using the semiconductor device includes a card substrate including the semiconductor device, a memory controller connected to the semiconductor device, and an external interface terminal connected to the memory controller.

  For example, the memory controller instructs the semiconductor device to store information in multiple values or read information in multiple values in response to an access instruction to the first storage area of the memory array from the outside. In response to an access instruction to two storage areas, the semiconductor device is instructed to store information in binary or read information in binary. The first storage area is used for storing data, and the second storage area is used for storing management information for the data in the first storage area. The management information is, for example, a decryption key or sector management information.

  [2] The storage device includes a nonvolatile memory and a memory controller connected to the nonvolatile memory. The memory controller controls multi-value information storage or multi-value information read, or binary information storage or binary information read from the nonvolatile memory. The non-volatile memory has a non-volatile memory cell that stores information according to a difference in threshold voltage, and a read determination level for the non-volatile memory cell that increases the threshold voltage when information is stored in binary in the non-volatile memory cell Is controlled to a level between the highest threshold voltage distribution and the next highest threshold voltage distribution in the multi-value information storage.

  As a result, the width of the lower threshold voltage distribution is larger than half of the entire threshold voltage distribution, so when rewriting stored information, when initializing the higher threshold voltage distribution to the lower threshold voltage distribution, The ratio of the overerased state in which the threshold voltage is lower than the lower threshold voltage distribution is small. Furthermore, the time required for the write-back process is significantly shortened, the write process time for increasing the threshold voltage in units of memory cells is shortened, and as a result, the time required for rewriting the stored information can be shortened.

  In a specific form of the present invention, the non-volatile memory has a read determination level for a non-volatile memory cell whose threshold voltage is controlled to be low when information is stored in binary, and the upper threshold level of the next higher threshold voltage distribution. And

  [3] The storage device includes a nonvolatile memory and a memory controller connected to the nonvolatile memory. The memory controller controls multi-value information storage or multi-value information read, or binary information storage or binary information read from the nonvolatile memory. The non-volatile memory has a non-volatile memory cell that stores information according to a difference in threshold voltage, and a read determination level for the non-volatile memory cell that increases the threshold voltage when information is stored in binary in the non-volatile memory cell Is controlled to a level between a plurality of threshold voltage distributions located higher than half of the plurality of threshold voltage distributions in the multi-value information storage.

  As a result, the width of the lower threshold voltage distribution is larger than half of the entire threshold voltage distribution, so when rewriting stored information, when initializing the higher threshold voltage distribution to the lower threshold voltage distribution, The ratio of the overerased state in which the threshold voltage is lower than the lower threshold voltage distribution is small. Furthermore, the time required for the write-back process is significantly shortened, the write process time for increasing the threshold voltage in units of memory cells is shortened, and as a result, the time required for rewriting the stored information can be shortened.

  In a specific form of the present invention, the non-volatile memory has a verify level for a non-volatile memory cell whose threshold voltage is controlled to be low when information is stored in binary, and the upper end of the threshold voltage distribution immediately below the read determination level. Level.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when performing binary information storage instead of multi-value information storage in a semiconductor device, memory card, or storage device, the time required for erasing or rewriting stored information can be shortened.
In addition, when performing binary information storage instead of multilevel information storage in a semiconductor device, memory card, or storage device, an overerased state is unlikely to occur during the erasure process.

<Flash memory>
FIG. 1 illustrates a flash memory as a semiconductor device. The flash memory 1 is formed on a single semiconductor substrate such as single crystal silicon.

  What is indicated by 3 is a memory array (MRY) having a memory mat and a sense latch circuit. The memory mat 3 has a large number of electrically erasable and writable nonvolatile memory cells, and forms an array form such as an AND or NOR type in which data terminals of the nonvolatile memory cells are connected in parallel to the bit lines.

  The external input / output terminals I / O 1 to I / O 16 are also used as address input terminals, data input terminals, data output terminals, and command input terminals, and are connected to the multiplexer 4. The sector address inputted to the external input / output terminals I / O1 to I / O16 is inputted from the multiplexer (MPX) 4 to the sector address buffer (SABUF) 5, and the Y address (column address) is inputted from the multiplexer 4 to the Y address counter (YACUNT). ) Is preset to 6. The write data input to the external input / output terminals I / O1 to I / O16 is supplied from the multiplexer 4 to the data input buffer 7 (DIBUF), and the read data output from the data output buffer (DOBUF) 8 passes through the multiplexer 4. Output from the external input / output terminals I / O1 to I / O16.

  A part of the command code and the address signal supplied to the external input / output terminals I / O 1 to I / O 16 are supplied from the multiplexer 4 to the internal control circuit (IPCNT) 10.

  The sector address supplied to the sector address buffer 5 is decoded by an X decoder (XDEC) 9 and a word line is selected from the memory array 3 according to the decoding result. The Y address counter 6 to which the Y address is preset is not particularly limited, but is an 11-bit counter, performs address counting from the preset value, and selects the Y decoder (YDEC) 11 and the Y gate (YGAT) 12 The signals are output sequentially. The Y gate 12 causes the input node of the 2048-byte data register (DREG) 13 to communicate with the byte output of the input data controller (IDCNT) 15 in units of bytes, or conducts it to the byte input of the data output buffer 8. For example, when an address in the middle of a sector is preset in the Y address counter 6, in the data output operation, the sector data read into the data register 13 is sequentially transferred from the Y gate 12 to the data output buffer in units of bytes starting from the head address. In the data input operation, the data supplied from the input data buffer 7 to the input data controller 15 is latched in the data register 13 in units of bytes from the Y gate 12 starting from the head address.

  The control signal buffer (CSBUF) 18 includes a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal / RE, and a write protect signal as external access control signals. / WP, power on read enable signal PRE, and reset signal / RES are supplied. The symbol “/” attached to the head of a signal means that the signal is low enable.

  The chip enable signal / CE is a signal for selecting the flash memory chip 1 and activates the flash memory chip (device) 1 at a low level and puts the flash memory chip 1 in a standby state at a high level. The read enable signal / RE controls the data output timing from the external input / output terminals I / O1 to I / O16, and data is read in synchronization with the clock change of the signal. The write enable signal / WE instructs the flash memory chip 1 to fetch a command, an address, and data at the rising edge. The command latch enable signal CLE is a signal for designating data supplied from the outside to the external input / output terminals I / O1 to I / O16 as a command, and the data of the output terminals I / O1 to I / O16 is CLE = "H". In the (high level) state, it is taken in synchronization with the rising edge of / WE and recognized as a command. The address latch enable signal ALE is a signal for instructing that the data supplied from the outside to the external input / output terminals I / O1 to I / O16 is an address, and the data of the output terminals I / O1 to I / O16 is ALE = In the "H" (high level) state, it is taken in synchronization with the rising edge of / WE and is recognized as an address. When the write protect signal / WP is at a low level, the flash memory chip 1 is prohibited from being erased and written. The power-on-read enable signal PRE is enabled when the power-on read function for reading data of a predetermined sector without inputting a command and an address after power-on is used. The reset signal / RES instructs the flash memory chip 1 to perform an initialization operation by transitioning from a low level to a high level after power-on.

  The internal control circuit 10 performs interface control according to the access control signal and the like, and controls internal operations such as erasing, writing, and reading according to the input command. The internal control circuit 10 outputs a ready / busy signal R / B and a master reset signal / MRES. The ready / busy signal R / B notifies the busy state to the outside by the low level during the operation of the flash memory chip 1.

  FIG. 2 illustrates an array configuration of nonvolatile memory cells in the memory mat 3. In the figure, typically four volatile memory cells 20 are shown. Although not shown, the nonvolatile memory cell 20 has a stacked gate structure in which a control gate is stacked on a floating gate via an insulating film, or a split gate structure in which a selection transistor and a storage transistor having a silicon nitride film are arranged in series. An appropriate memory cell structure can be adopted. For example, in the case of a stacked gate structure nonvolatile memory cell, the control gate is connected to the word lines WLi and WLj, the drain is connected to the bit lines BLn and BLm, and the source is connected to the source lines SLi and SLj. The erase process for the non-volatile memory cell having the stacked gate structure is not particularly limited. However, the threshold voltage is lowered by applying a positive high voltage to the control gate as an erase bias and releasing electrons of the floating gate. . The writing process for the non-volatile memory cell having the stacked gate structure is not particularly limited, but is a process for increasing the threshold voltage by applying a negative high voltage to the drain as a writing bias and injecting electrons to the floating gate. The read process is a process for selecting a memory cell transistor with a predetermined read determination level as a word line selection level and making it possible to detect stored information based on a change in current flowing in the bit line or a change in level appearing on the bit line.

  FIG. 3 illustrates a threshold voltage distribution by quaternary information storage. FIG. 4 illustrates a threshold voltage distribution by binary information storage. The internal control circuit 10 enables both quaternary information storage and binary information storage for the nonvolatile memory cell 20. Individual erasure commands, write commands, and read commands are prepared for quaternary information storage and binary information storage.

  In FIG. 3, the threshold voltage distribution Drng is an erased state (memory information “00”), the threshold voltage distribution Crng is a first write state (memory information “01”), and the threshold voltage distribution Brng is a second write state (memory information “10”). ), The threshold voltage distribution Arng is in the third write state (stored information “11”). RL1 to RL3 are read determination levels for the nonvolatile memory cells, and are given to the nonvolatile memory cells as word line selection levels when determining stored information. For example, the read determination level RL1 determines whether the nonvolatile memory cell is in an on state or an off state. When the nonvolatile memory cell is in an on state, the read determination level RL0 determines whether the nonvolatile memory cell is in an on state or an off state. For example, it is determined that the threshold voltage distribution Drng is in the erased state (stored information “00”), and if it is in the off state, it is determined that the threshold voltage distribution Crng is in the first write state (stored information “01”). . On the other hand, when the read determination level RL1 determines that the nonvolatile memory cell is in the off state, the read determination level RL2 further determines whether the nonvolatile memory cell is in the on state or the off state. It is determined that the distribution Brng is in the second writing state (memory information “10”), and if it is in the off state, it is determined that the threshold voltage distribution Arng is in the third writing state (memory information “11”).

  In FIG. 4, the threshold voltage distribution B_Drng is in the erased state (memory information “0”), and the threshold voltage distribution Arng is in the written state (memory information “1”). The threshold voltage distribution Arng in FIG. 4 is the same as the threshold voltage distribution Arng in the third write state in FIG. The threshold voltage distribution B_Drng ranges from the lower limit of the threshold voltage distribution Drng in the erased state in FIG. 3 to the upper limit of the threshold voltage distribution Brng in the second written state. The read determination level for binary reading is RL2.

  FIG. 5 illustrates a quaternary erase process flow. An erasing bias of a predetermined voltage is applied to the nonvolatile memory cell for a predetermined time (S1), and an over-erasing (also referred to as over-erasing) check is performed (S2). The over-erase check here is to determine whether the threshold voltage of the nonvolatile memory cell is equal to or higher than the verify level VL0. If it is not excessive erasure, an erasure check is performed (S3). Here, the erase check is to determine whether the threshold voltage of the nonvolatile memory cell is equal to or lower than the verify level VL1. If the verify level is not lower than VL1, the erase bias is applied again (S1). If the erase is excessive, the write bias is applied and the write back is performed (S4). Finally, all the nonvolatile memory cells to be erased are written. The above-described processing of S1 to S4 is repeated until the threshold voltage falls within the erased threshold voltage distribution Drng. The application of the erase bias is performed in units of word lines, and the application of the write bias for writing back is controlled in units of bits.

  FIG. 6 shows a quaternary write processing flow. The writing process is performed after the erasing process. In the write process, the write bias application (S11) for the nonvolatile memory cell to be brought into the third write state (stored information “11”) of the threshold voltage distribution Arng and the verify check (S12) by the verify level VL6 are repeated. Then, the write bias application (S13) for the nonvolatile memory cell to be brought into the second write state (memory information “10”) of the threshold voltage distribution Brng and the verify check (S14) by the verify level VL4 are repeated, and finally the threshold value The write bias application (S15) for the nonvolatile memory cell to be brought into the first write state (memory information “01”) of the voltage distribution Crng and the verify check (S16) by the verify level VL2 are repeated. Whether or not the write bias is actually applied in steps S11, S13, and S15 is controlled by the value of every two bits of the write data. A write bias is applied in S11 to the nonvolatile memory cell whose unit 2 bits are “11”, a write bias is applied in S13 to the nonvolatile memory cell whose unit 2 bits is “10”, and the unit 2 bits is “01”. In step S15, a write bias is applied to the non-volatile memory cell “”, and application of the write bias is suppressed to the non-volatile memory cell in which the unit 2 bits are “00”. Finally, an upper skirt check (S17) is performed. That is, for a nonvolatile memory cell that should be in the second writing state (memory information “10”) of the threshold voltage distribution Brng, the threshold voltage is equal to or lower than the verify level VL5, and the first writing state of the threshold voltage distribution Crng. For the nonvolatile memory cell to be set (memory information “01”), the threshold voltage is equal to or lower than the verify level VL3, and the nonvolatile memory to be set to the erased state (memory information “00”) of the threshold voltage distribution Drng. It is checked that the threshold voltage of the cell is equal to or lower than the verify level VL1. If the threshold voltage is less than or equal to the upper skirt of the target threshold voltage distribution, writing is terminated normally (PASS), and if even one bit exceeds the upper skirt, it is abnormally terminated (FAIL), and the erasing process is repeated.

  FIG. 7 illustrates a binary erase processing flow. An erasing bias of a predetermined voltage is applied to the nonvolatile memory cell for a predetermined time (S1), and an over-erasing (also referred to as over-erasing) check is performed (S2). The over-erase check here is to determine whether the threshold voltage of the nonvolatile memory cell is equal to or higher than the verify level VL0. If it is not excessive erasure, an erasure check is performed (S5). Here, the erase check is to determine whether the threshold voltage of the nonvolatile memory cell is equal to or lower than the verify level VL5. If the verify level is not lower than VL5, an erase bias is applied again (S1), and if it is excessive erase, a write bias is applied to perform write back (S4), and finally all nonvolatile memory cells to be erased are processed. The processes of S1, S2, S4, and S5 are repeated until the threshold voltage of the current value falls within the erased threshold voltage distribution B_Drng.

  Compared with the quaternary erase process of FIG. 5, the threshold voltage distribution B_Drng in the erased state of the binary storage has a width about three times the threshold voltage distribution Drng in the erased state of the quaternary storage. As a result, an over-erased state in which the threshold voltage does not become the target threshold voltage distribution or less during the erasing process is not performed, or the ratio is extremely small. Furthermore, if the number of non-volatile memory cells that are over-erased during the erasure process is reduced, the time required for the write-back process for each memory cell can be significantly shortened. Therefore, the erasure processing time in the binary storage is remarkably shortened compared to the 4-level storage. This processing time shortening effect cannot be obtained because it is simply a binary storage. Between the highest threshold voltage distribution Arn and the next highest threshold voltage distribution Brn in information storage with four-level read determination level for a nonvolatile memory cell that is in a write state with a high threshold voltage when storing information in binary This is because the level RL2 is controlled. When information is stored in binary, as shown in the comparative example of FIG. 9, the highest threshold voltage distribution Arn in information storage in which the read determination level for a nonvolatile memory cell in a write state with a high threshold voltage is four values. When the control is performed so that the level RL1 is between the threshold voltage distribution Drn and the lowest threshold voltage distribution Drn, the threshold voltage distribution in the erased state is narrowed in the same manner as in the case of quaternary storage, so that the erase time can be expected to be shortened. I can't.

  FIG. 8 shows a binary write processing flow. The writing process is performed after the erasing process. In the write process, the write bias application (S11) for the nonvolatile memory cell to be brought into the third write state (stored information “1”) of the threshold voltage distribution Arng and the verify check (S12) with the verify level VL6 are repeated. Whether or not the write bias is actually applied in step S11 is controlled by the value of each bit of the write data. In step S11, a write bias is applied to a nonvolatile memory cell whose unit 1 bit is “1”, and application of a write bias is suppressed to a nonvolatile memory cell whose unit 1 bit is “0”. Finally, an upper skirt check (S18) is performed. Here, it is checked that the threshold voltage of the threshold voltage distribution B_Drng to be erased (stored information “0”) is equal to or lower than the verify level VL5. If the threshold voltage is less than or equal to the upper skirt of the target threshold voltage distribution, writing is terminated normally (PASS), and if even one bit exceeds the upper skirt, it is abnormally terminated (FAIL), and the erasing process is repeated.

  Compared with the four-value write processing of FIG. 6, the write threshold voltage distribution to be set is only one type of Arng, and the upper skirt check only needs to be performed on one type of threshold voltage distribution B_Drng. The write processing time is also shorter than the 4-value storage.

  As a result, by using the binary storage based on the threshold voltage distribution of FIG. 4, the erasure process and the write process required for rewriting the stored information, compared to the 4-value storage of FIG. 3 and the binary storage of the comparative example of FIG. Can be shortened. Furthermore, since the number of non-volatile memory cells that are over-erased during the erasing process is remarkably small, the probability that an over-erased non-volatile memory cell remains due to undesired power interruption can be reduced. When a measure against over-erasure is separately taken, any over-erased nonvolatile memory cell will not remain anyway, but when performing binary storage of FIG. 4, a measure against over-erasure is implemented. The ratio is reduced, and the reliability of information storage is also improved in this respect.

"Memory card"
FIG. 10 shows a memory card to which the flash memory of FIG. 1 is applied. The memory card 31 includes the erasable and writable flash memory (FLASH) 1 and a card controller (CCNT) 35 that performs memory control and external interface control on a mounting board.

  The flash memory 1 is subjected to access control by the card controller 35. In FIG. 1, the card controller 35 performs external interface control with, for example, a host computer (host device). The card controller 35 has an access control function for accessing the flash memory 1 in accordance with an instruction from the host computer. This access control function is a hard disk compatible control function. For example, when the host computer manages a set of sector data as file data, the card controller 35 associates a sector address as a logical address with a physical memory address to correspond to the flash memory. 1 access control is performed. According to FIG. 1, the card controller 35 includes a host interface circuit (HIF) 40, a microprocessor (MPU) 41 as a calculation control means, a flash controller (FCNT) 42, a buffer controller (BCNT) 43, and a buffer memory ( BUFM) 44. The flash controller 42 includes an ECC circuit (not shown). The buffer memory 44 is composed of DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory).

  The MPU 41 includes a CPU (Central Processing Unit) 45, a program memory (PGM) 46, a work RAM (WRAM) 47, and the like, and controls the card controller 35 as a whole. The program memory 46 holds an operation program for the CPU 45 and the like.

  The host interface circuit 40 is a personal computer according to a predetermined protocol such as ATA (ATAttachment), IDE (Integrated Device Electronics), SCSI (Small Computer System Interface), MMC (MultiMediaCard), PCMCIA (Personal Computer Memory Card International Association). Alternatively, it is a circuit that interfaces with a host computer such as a workstation. The MPU 41 controls the host interface operation.

  The buffer controller 43 controls the memory access operation of the buffer memory 44 in accordance with an access instruction given from the MPU 41. The buffer memory 44 temporarily holds data input to the host interface 40 or data output from the host interface 40. The buffer memory 44 temporarily holds data read from the flash memory 1 or data written to the flash memory 1.

  The flash controller 42 controls a read operation, an erase operation, and a write operation for the flash memory 1 in accordance with an access instruction given from the MPU 41. The flash controller 42 outputs read control information such as a read command and read address information in a read operation, outputs write control information such as a write command code and write address information in a write operation, and erases an erase command or the like in an erase operation. Output control information. An ECC circuit (not shown) generates an error correction code (error correction code) for data to be written to the flash memory 1 in accordance with an instruction given from the MPU 41, and adds it to the write data. Further, error detection / correction processing is performed on the read data read from the flash memory 1 using an error correction code added to the read data, and an error within the error correction capability range is corrected.

  The flash memory 1 includes, in its nonvolatile memory array (ARY) 3, a first storage area ARYf) 3A that is a target of quaternary storage and a second storage area (ARYs) 3B that is a target of binary storage. And have. The first storage area 3A is used for storing data, and the second storage area 3B is used for storing management information for the data in the first storage area 3A. For example, the management information is key data necessary for accessing the first storage area 3A, ID information requiring security, logical address information for each sector, flag information indicating the validity of the sector, or the like.

  In response to an access instruction from the host device to the first storage area 3A of the memory array, the flash controller 42 instructs the flash memory 1 to store information in four values or read information in multiple values in response to the instruction. In response to an access instruction from the host device to the second storage area 3B of the memory array, in response to this, the flash memory is instructed to store binary information or read binary information. The host device does not need to recognize the distinction between binary storage and quaternary storage when accessing the memory card. The flash controller 42 holds information on the logical address assigned to the first storage area 3A and the logical address assigned to the second storage area 3B.

  Since the second storage area 3B to be subjected to binary storage can rewrite the stored information in a short time and the reliability of the information storage is high, the storage of the key data and the ID information is possible. Suitable for use in areas.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the flash memory may be configured to include a plurality of memory banks. Each memory bank includes the MRY, DREG, YGAT, YDEC, and XDEC. Nonvolatile memory is not limited to flash memory. It may be an EEPROM or a high dielectric memory. In the memory card, the controller and the flash may be configured by one chip. Such a chip can be positioned as a storage device for a memory card. The quaternary writing procedure is not limited to that shown in FIG. Further, the relationship between the threshold voltage state in quaternary storage and the value of the stored information corresponding to the threshold voltage state in binary storage, and the value of the stored information corresponding to the threshold voltage state in the binary storage can be appropriately changed as limited to the above example.

  From the viewpoint of preventing over-erasure, the present invention is applied to a device having a memory array configuration in which memory cells are arranged in parallel as represented by a NOR type.

1 is a block diagram illustrating a flash memory as a semiconductor device. 2 is a circuit diagram illustrating an array configuration of nonvolatile memory cells in a memory mat. FIG. It is a frequency distribution diagram which illustrates the threshold voltage distribution by 4-value information storage. It is a frequency distribution diagram which illustrates the threshold voltage component distribution by binary information storage. It is a flowchart which illustrates a quaternary deletion processing flow. It is a flowchart which illustrates a 4-value write processing flow. It is a flowchart which illustrates a binary deletion processing flow. It is a flowchart which illustrates a binary write processing flow. The read determination level for the non-volatile memory cell that is set to the write state with a high threshold voltage is controlled to be a level RL1 between the highest threshold voltage distribution Arn and the lowest threshold voltage distribution Drn in the four-value information storage. It is a frequency distribution diagram which illustrates the threshold voltage distribution by the information storage by the binary which concerns on a comparative example. FIG. 2 is a block diagram illustrating a memory card to which the flash memory of FIG. 1 is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Flash memory 3 Memory array 5 Sector address buffer 9 Coder in X 10 Internal control circuit 11 Coder in Y 12 Y gate 13 Data register 20 Non-volatile memory cell Arng Threshold voltage distribution in the third write state (memory information “11”) Brng Threshold voltage distribution in the second write state (memory information “10”) Crng Threshold voltage distribution in the first write state (memory information “01”) Drng Threshold voltage distribution in the erased state (memory information “00”) VL0 to VL6 Verify level VL5 Upper skirt determination level in erased state in binary storage RL0 to RL2 Read determination level RL2 Read determination level in binary storage 31 Memory card 35 Card controller 40 Host interface circuit 41 Processor 42 Flash controller 45 CPU
46 Program memory 47 Work RAM

Claims (10)

A memory array composed of a plurality of nonvolatile memory cells for storing information according to a difference in threshold voltage;
A control circuit that performs control for lowering and increasing the threshold voltage of the nonvolatile memory cell to perform binary information storage or multilevel information storage of four or more values in the nonvolatile memory cell,
The control circuit is a level between the highest threshold voltage distribution and the next highest threshold voltage distribution in the information storage having a multi-level read determination level for the nonvolatile memory cell that increases the threshold voltage when storing information in binary. A semiconductor device that is controlled to be 2. The semiconductor device according to claim 1, wherein the control circuit sets the verify level for the nonvolatile memory cell, which lowers the threshold voltage when storing information in binary, to the upper base level of the next highest threshold voltage distribution. The process for reducing the threshold voltage is an erasing process for reducing the number of electrons held in the nonvolatile memory cell, and the process for increasing the threshold voltage is a writing process for increasing the number of electrons held in the nonvolatile memory cell. 2. The semiconductor device according to 2. A memory card comprising: the semiconductor device according to claim 1; a memory controller connected to the semiconductor device; and an external interface terminal connected to the memory controller. The memory controller instructs the semiconductor device to store information in multiple values or read information in multiple values in response to an access instruction to the first storage area of the memory array from the outside. 5. The memory card according to claim 4, wherein the semiconductor device is instructed to store information in binary or read information in binary in response to an access instruction to the storage area. 6. The memory card according to claim 5, wherein the first storage area is used for storing data, and the second storage area is used for storing management information for data in the first storage area. A storage device having a nonvolatile memory and a memory controller connected to the nonvolatile memory,
The memory controller controls multi-value information storage or multi-value information read, or binary information storage or binary information read from the nonvolatile memory,
The non-volatile memory has a non-volatile memory cell that stores information according to a difference in threshold voltage, and a read determination level for the non-volatile memory cell that increases the threshold voltage when information is stored in binary in the non-volatile memory cell Is controlled so as to be at a level between the highest threshold voltage distribution and the next highest threshold voltage distribution in multi-value information storage. 8. The storage device according to claim 7, wherein when the nonvolatile memory performs binary information storage, the read determination level for the nonvolatile memory cell whose threshold voltage is controlled to be low is set to the upper base level of the next highest threshold voltage distribution. . A storage device having a nonvolatile memory and a memory controller connected to the nonvolatile memory,
The memory controller controls multi-value information storage or multi-value information read, or binary information storage or binary information read from the nonvolatile memory,
The non-volatile memory has a non-volatile memory cell that stores information according to a difference in threshold voltage, and a read determination level for the non-volatile memory cell that increases the threshold voltage when information is stored in binary in the non-volatile memory cell Is a storage device that controls to be at a level between a plurality of threshold voltage distributions located higher than half of a plurality of threshold voltage distributions in multi-value information storage. 10. The memory according to claim 9, wherein the nonvolatile memory uses a verify level for a nonvolatile memory cell whose threshold voltage is controlled to be low when information is stored in binary as an upper foot level of a threshold voltage distribution immediately below the read determination level. apparatus.

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