JP2006013730A - PLL circuit - Google Patents

Abstract

[PROBLEMS] To reliably perform the process from the detection of the reproduction frequency to the setting of the free-running frequency of the extraction clock by digital processing when the frequency of the reproduction data is drawn based on the extraction clock obtained from the reproduction data. A PLL circuit capable of completing frequency acquisition is provided.
When performing frequency pull-in of reproduction data, if frequency pull-in of reproduction data is not completed, a pull-in state determination circuit 11 switches a frequency pull-in operation condition to determine a frequency pull-in state.
[Selection] Figure 1

Description

  The present invention relates to a PLL circuit that performs free-running frequency detection processing by digital processing when generating an extraction clock from playback data in an optical disc playback device such as a CD player or a DVD player.

First, as an application example of a conventional PLL circuit, a case where it is used in an optical disc reproducing apparatus will be described.
FIG. 11 is a block diagram showing a configuration of an optical disc reproducing apparatus using a conventional PLL circuit. In FIG. 11, reference numeral 21 denotes an optical disk such as a CD or a DVD, which is rotationally driven by a spindle motor 26. The pickup 22 irradiates the optical disc 21 with laser, detects return light (reflected light) from the optical disc 21, converts it to a voltage value corresponding to the return light, and outputs it. The voltage output is amplified by the RF amplifier 23 and then binarized by the data slicer 24 to restore the information recorded on the optical disc 21 as a reproduction signal.

  Furthermore, the reproduced signal is decoded and corrected at a later stage (not shown), but an extraction clock synchronized with the disk reproduced signal is required to perform the later stage processing. Based on this, the PLL circuit 25 is configured to generate.

Next, a conventional PLL circuit (for example, see Patent Document 1) will be described.
FIG. 10 is a block diagram showing a configuration of a conventional PLL circuit. In FIG. 10, 1 is a phase difference detection circuit, 2 is a loop filter circuit, 3 is a free-running frequency detection circuit, 4 is an addition circuit, 5 is an extraction clock generation circuit, and the PLL circuit 25 is constituted by the above circuits. Yes.

The operation of the PLL circuit configured as described above will be described below.
The phase difference detection circuit 1 detects the phase difference between the reproduction signal and the extracted clock, and outputs the phase difference as a digital value. The loop filter circuit 2 integrates the phase difference detected by the phase difference detection circuit 1 and outputs it as a phase difference correction output. The free-running frequency detection circuit 3 determines the frequency of the extracted clock by detecting the frequency of the reproduction signal and outputs it as a free-running frequency setting value. The extraction clock generation circuit 5 generates an extraction clock according to the result of adding the free-running frequency setting value and the phase difference correction output by the addition circuit 4.

As described above, an extraction clock synchronized with the reproduction signal can be generated.
JP 2002-64376 A

  However, in the conventional PLL circuit as described above, since the processing from the frequency detection of the reproduction signal to the free-running frequency setting of the extracted clock is executed by the digital processing in the free-running frequency detection circuit 3, the frequency pull-in may not be completed. There is a need for this.

The above problems will be described below.
FIG. 6 is a time chart showing the frequency pulling operation in the conventional PLL circuit. In FIG. 6, A is a time change of the frequency (reproduction frequency) of the reproduction signal, B is a free-running frequency setting value, and C is a phase difference correction output. The adder circuit 4 is set with a free-running frequency set value B which is an output of the free-running frequency detection circuit 3. The phase difference correction output C, which is the output of the loop filter circuit 2, is added to the free-running frequency setting value B. This phase difference correction output C continues to be added until the free-running frequency set value B is updated.

Next, the frequency pull-in operation will be described with reference to FIG.
First, the reproduction frequency A approaches the target frequency. During this time, the free-running frequency setting value B is updated following the reproduction frequency A of the reproduction signal at regular intervals. The phase difference correction output C follows the reproduction frequency A of the reproduction signal until the free-running frequency set value B is updated, and is cleared at the same time as the free-running frequency set value B is updated.

Next, the operation when the pull-in is completed will be described.
FIG. 9 is a time chart showing the operation when the frequency pull-in in the conventional PLL circuit is completed, and is an enlarged view of a portion D in FIG. As shown in FIG. 9, the reproduction frequency A of the reproduction signal is sufficiently close to the target frequency and becomes stable. When the free-running frequency setting value B is sufficiently close to the reproduction frequency A of the reproduction signal and the phase difference correction output C is added, the addition signal of the free-running frequency setting value B and the phase difference correction output C becomes the target frequency. Thus, the reproduction frequency A of the reproduction signal coincides with the frequency of the extraction clock generated by the extraction clock generation circuit 5 based on the addition signal, and the frequency pull-in is completed.

Next, the operation when the frequency pull-in is not completed will be described.
FIG. 7 is a time chart showing the operation when the frequency pull-in is not completed in the conventional PLL circuit. As shown in FIG. 7, the reproduction frequency A is sufficiently close to the target frequency and becomes stable. The free-running frequency set value B is sufficiently close to the reproduction frequency A and attempts to complete the pull-in with the phase difference correction output C. Normally, as shown in FIG. 9, the frequency pull-in operation is completed by adding the phase difference correction output before the free-running frequency set value B is updated, but the phase difference correction output C The self-running frequency setting value B is updated before the frequency pull-in is completed due to a low gain of the signal. The update in this case is executed by digital processing of the free-running frequency detection circuit 3, but since this update processing is digital processing, if the free-running frequency set value B is sufficiently close to the target frequency, it is the same as the previous time. Value. In addition, since the addition of the phase difference correction output C is cleared by updating the free-running frequency setting value B, the pull-in cannot be completed by the addition of the phase difference correction output C. This operation is repeated, and the frequency pull-in is not completed permanently.

  The present invention solves the above-mentioned conventional problems, and when performing reproduction data frequency pull-in based on the extraction clock obtained from the reproduction data, the process from detection of the reproduction frequency to setting the free-running frequency of the extraction clock. Provided is a PLL circuit capable of reliably completing frequency acquisition even when processing is executed by digital processing.

  In order to solve the above problems, a PLL circuit according to claim 1 of the present invention includes a phase difference detection circuit for detecting a phase difference between reproduced data and an extracted clock, and an output of the phase difference detection circuit as a phase difference correction output. A loop filter circuit that converts and outputs the data, a free-running frequency detection circuit that detects a frequency of the reproduction data and outputs a free-running frequency setting value of the extracted clock, a phase difference correction output from the loop filter circuit, and the An adder circuit for adding a free-running frequency setting value from a free-running frequency detection circuit, an extraction clock generation circuit for generating a clock corresponding to an output value of the addition circuit as the extraction clock, and frequency pull-in of the reproduction data is completed And a pull-in state determination circuit for switching the frequency pull-in operation condition to determine the frequency pull-in state when not That.

  The PLL circuit according to claim 2 of the present invention is the PLL circuit according to claim 1, wherein the pull-in state determination circuit has a free-running frequency set value from the free-running frequency detection circuit of two or more times. The configuration is such that a case where the frequency does not change continuously is detected as a state where the frequency pull-in is not completed.

  The PLL circuit according to claim 3 of the present invention is the PLL circuit according to claim 1, wherein the pull-in state determination circuit is configured such that when the number of repetitions of the frequency pull-in operation exceeds a certain number, The present invention is characterized in that a case where a specific value exists as a free-running frequency setting value from the free-running frequency detection circuit a predetermined number of times is detected as a state where the frequency pull-in is not completed.

  The PLL circuit according to a fourth aspect of the present invention is the PLL circuit according to the first aspect, wherein the pull-in state determination circuit includes the self-locking state determination circuit after the extracted clock is within a predetermined range of a target frequency. The present invention is characterized in that when the number of updates of the free-running frequency set value from the running frequency detection circuit exceeds a certain number, it is detected as a state where the frequency pull-in is not completed.

  As described above, when the frequency pull-in of the reproduction data is not completed when the reproduction data frequency pull-in is not completed, the frequency pull-in state can be determined by switching the condition of the frequency pull-in operation.

  As described above, according to the present invention, when the frequency pull-in of the reproduction data is not completed when the reproduction data frequency pull-in is performed, the frequency pull-in state can be determined by switching the condition of the frequency pull-in operation. .

  Therefore, when the frequency of the reproduction data is drawn based on the extracted clock obtained from the reproduction data, even if the processing from the detection of the reproduction frequency to the setting of the free-running frequency of the extraction clock is executed by digital processing, the frequency is surely Retraction can be completed.

Hereinafter, a PLL circuit showing an embodiment of the present invention will be specifically described with reference to the drawings.
(Embodiment 1)
A PLL circuit according to the first embodiment of the present invention will be described.

  FIG. 1 is a block diagram showing the configuration of the PLL circuit according to the first embodiment. In FIG. 1, reference numeral 11 denotes a pull-in state determination circuit (A), and the configuration and operation related to the case where the pull-in state determination circuit (A) 11 does not detect that the frequency pull-in is not completed is shown in FIG. The configuration and operation of the conventional PLL circuit shown in FIG. That is, the difference from the conventional PLL circuit shown in FIG. 10 is that the pull-in state determination circuit (A) 11 is provided.

Next, the operation of the pull-in state determination circuit (A) in the PLL circuit according to the first embodiment will be described.
FIG. 2 is a block diagram showing the configuration of the pull-in state determination circuit (A) in the PLL circuit according to the first embodiment, and this pull-in state determination circuit (A) detects that the frequency pull-in is not completed. To do. In FIG. 2, 6 is a comparison circuit and 7 is a delay circuit. The delay circuit 7 delays the input free-running frequency setting value and outputs it as the previous free-running frequency setting value. The comparison circuit 6 compares the input free-running frequency setting value with the previous free-running frequency setting value that is the output of the delay circuit 7. If they match, the pull-in NG indicating that the frequency pull-in is not completed. Output a signal. Any number of delay circuits 7 in the pull-in state determination times (A) 11 may be prepared as long as they are two or more.

  On the other hand, when receiving the pull-in NG signal from the pull-in state determination time (A) 11, the loop filter circuit 2 increases the gain of the phase difference correction output. As a result, the frequency pull-in is completed before the free-running frequency set value that is the output of the free-running frequency detection circuit 3 is reset.

  FIG. 8 is a time chart showing the frequency pull-in operation in the PLL circuit of the first embodiment, and shows the operation of the adder circuit 4 when there are two delay circuits 6. As shown in FIG. 8, since the set value for the free-running frequency has not changed twice, the loop filter circuit 2 further increases the gain of the phase difference correction output. Its output is E. As a result, before the self-running frequency set value is updated, the reproduction frequency matches the frequency of the extraction clock, and the frequency pull-in is completed.

  Even if the pull-in state determination circuit (A) 11 detects a state where the frequency pull-in is not completed and changes the pull-in condition by a method other than increasing the gain of the phase difference correction output, the free-running frequency detection circuit 3 Any means may be used as long as it can avoid repeating the operation of “update of self-running frequency set value to add phase difference correction output”.

As described above, the pull-in state determination circuit (A) for detecting a state in which the frequency pull-in is not completed is provided, and by switching the pull-in operation conditions such as “increasing the gain of the phase difference correction output”, the reproduction frequency is detected. Even when the processing up to the setting of the free-running frequency of the extraction clock is executed by digital processing, it is possible to ensure the frequency pull-in.
(Embodiment 2)
A PLL circuit according to the second embodiment of the present invention will be described.

  FIG. 3 is a block diagram showing the configuration of the pull-in state determination circuit (A) in the PLL circuit according to the second embodiment. Circuit configurations other than the pull-in state determination circuit (A) are the same as those in the first embodiment. is there.

  The comparison circuit 6 and the delay circuit 7 in FIG. 3 have the same configuration as the pull-in state determination circuit (A) of the first embodiment and operate in the same manner. When the comparison circuit 6 confirms the coincidence, a pulse signal is input to the counter 8. An update count setting value is set in advance in the counter 8, and when the count number exceeds the update count setting value, the counter 8 overflows and outputs a pull-in NG signal. The operation when the pull-in NG signal is output is the same as that of the first embodiment.

  The PLL circuit of the second embodiment detects a situation in which it is difficult to complete the frequency pull-in even when the free-running frequency setting value does not continuously take a constant value due to noise or the like only by adding the counter 8. Therefore, the frequency pull-in can be completed more reliably than in the first embodiment.

As in the first embodiment, any number of delay circuits 7 may be prepared as long as there are two or more.
(Embodiment 3)
A PLL circuit according to the third embodiment of the present invention will be described.

  FIG. 4 is a block diagram showing the configuration of the PLL circuit according to the third embodiment. FIG. 5 is a block diagram showing the configuration of the pull-in state determination circuit (B) in the PLL circuit according to the third embodiment, and is the same as that of the second embodiment except for the pull-in state determination circuit (B) 12. .

Hereinafter, the pull-in state determination circuit (B) 12 of the third embodiment will be described.
In FIG. 5, the update signal pulse is output from the AND circuit 13 when the free-running frequency setting value is updated by the free-running frequency detection circuit 3 and the frequency range OK signal is input from the free-running frequency detection circuit 3. The frequency range OK signal is a signal that is output when the free-running frequency setting value reaches a certain range of the target frequency.

The operation of the pull-in state determination circuit (B) 12 configured as described above will be described below.
When the free-running frequency set value reaches within a certain range of the target frequency, the frequency range OK signal from the free-running frequency detection circuit 3 becomes H. Next, when the free-running frequency setting value is updated by the free-running frequency detection circuit 3, an update signal pulse from the AND circuit 13 is input to the counter 8, and the count value of the counter 8 is set to a preset number of updates. When the value is exceeded, overflow occurs, and a counter NG signal is output from the counter 8. The operation when this pull-in NG signal is output is the same as the operation of the first embodiment. In the third embodiment, the frequency pull-in operation can be reliably performed with a very simple configuration including only the AND circuit 21 and the counter 8.

  When the PLL circuit of the present invention performs the process from the detection of the reproduction frequency to the setting of the free-running frequency of the extraction clock by digital processing when performing the frequency pull-in of the reproduction data based on the extraction clock obtained from the reproduction data However, since the frequency pull-in can be completed with certainty, it can be effectively used to accurately perform the frequency pull-in operation in an optical disc reproducing apparatus such as a CD player or a DVD player.

1 is a block diagram showing a configuration of a PLL circuit according to a first embodiment of the present invention. The block diagram which shows the structure of the drawing-in state determination circuit (A) in the PLL circuit of Embodiment 1 The block diagram which shows the structure of the drawing-in state determination circuit (A) in the PLL circuit of Embodiment 2 of this invention The block diagram which shows the structure of the PLL circuit of Embodiment 3 of this invention The block diagram which shows the structure of the drawing-in state determination circuit (B) in the PLL circuit of Embodiment 3 Time chart showing frequency pull-in operation in a conventional PLL circuit Time chart showing operation when frequency pull-in is not completed in the conventional PLL circuit Time chart showing the frequency pull-in operation in the PLL circuit of Embodiment 1 of the present invention Time chart showing operation when frequency pull-in in conventional PLL circuit is completed Block diagram showing the configuration of a conventional PLL circuit The block diagram which shows the structure of the optical disk reproducing | regenerating apparatus using the PLL circuit of the prior art example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Phase difference detection circuit 2 Loop filter circuit 3 Free-running frequency detection circuit 4 Adder circuit 5 Extraction clock generation circuit 6 Comparison circuit 7 Delay circuit 8 Counter 11 Pull-in state determination circuit (A)
12 Pull-in state determination circuit (B)
13 AND circuit 21 Optical disc 22 Pickup 23 RF amplifier 24 Data slicer 25 PLL circuit 26 Spindle motor A Frequency waveform of playback signal B Free-running frequency set value C Phase difference correction output D Frequency pull-in point E Phase difference correction output

Claims (4)

  A phase difference detection circuit for detecting a phase difference between the reproduced data and the extracted clock; a loop filter circuit for converting the output of the phase difference detecting circuit into a phase difference corrected output; and a frequency of the reproduced data for detecting the extracted clock A free-running frequency detection circuit for outputting a free-running frequency setting value, an addition circuit for adding a phase difference correction output from the loop filter circuit and a free-running frequency setting value from the free-running frequency detection circuit, and the addition circuit An extraction clock generation circuit that generates a clock corresponding to the output value of the output clock as the extraction clock, and a pull-in for determining the frequency pull-in state by switching a condition of the frequency pull-in operation when the frequency pull-in of the reproduction data is not completed A PLL circuit comprising a state determination circuit.   2. The PLL circuit according to claim 1, wherein the pull-in state determination circuit sets a state in which the frequency pull-in is not completed when a free-running frequency setting value from the free-running frequency detection circuit does not continuously change twice or more. A PLL circuit characterized by detecting.   The PLL circuit according to claim 1, wherein the pull-in state determination circuit is specified as a free-running frequency setting value from the free-running frequency detection circuit when the number of repetitions of the frequency pull-in operation exceeds a certain number. A PLL circuit which detects a case where a value exists a predetermined number of times as a state where the frequency pull-in is not completed.   2. The PLL circuit according to claim 1, wherein after the extracted clock is within a predetermined range of a target frequency, the pull-in state determination circuit determines whether the number of updates of the free-running frequency setting value from the free-running frequency detection circuit is A PLL circuit that detects when the frequency exceeds a certain number as a state where the frequency pull-in is not completed.

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