JP2006013205A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

To reduce the thickness and size of a semiconductor device.
A semiconductor device includes a wiring substrate having a plurality of wiring layers on an upper surface and a plurality of base electrode layers that are electrically connected to the wiring layers on a lower surface via through conductors. A semiconductor chip 3 fixed to the upper surface of the wiring substrate 2 and having a plurality of electrodes on the upper surface; an interlayer insulating film 10 formed on the upper surface of the wiring substrate 2 and selectively covering the semiconductor chip 3 and the wiring layer 4; A wiring 13 formed of a conductor layer formed on the semiconductor substrate 10 and connected to the electrode of the semiconductor chip 3 at one end side through the interlayer insulating film 10 and connected to the wiring layer 4 through the interlayer insulating film 10 at the other end side; A sealing body 14 is provided on the upper surface side of the wiring substrate and is made of an insulating material that covers the wiring, and a protruding electrode 7 is provided so as to overlap the base electrode layer 6.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique effective when applied to the manufacture of a surface mount type semiconductor device such as a BGA (Ball Grid Array) structure and an LGA (Land Grid Array) structure.

  As a package structure for improving the degree of integration of semiconductor devices and reducing the size and weight, surface-mount semiconductor devices called BGA structures and LGA structures are known. Moreover, in order to improve productivity, the batch molding method is employ | adopted.

  A semiconductor device manufacturing method employing this batch molding method is as follows. In manufacturing a semiconductor device, a wiring mother board is first prepared. The wiring mother board has a structure in which product forming portions are partitioned and arranged vertically and horizontally. In the product forming portion, the central portion on one side is a portion on which a semiconductor chip is mounted, and a plurality of wiring layers are provided around it. In addition, a base electrode that is electrically connected to the wiring layer via a through conductor is provided on the other surface (back surface) of the product forming portion.

  After preparing such a wiring mother board, a semiconductor chip is mounted on each product forming part on one side of the wiring board, and then each electrode of the semiconductor chip and the wiring layer of the product forming part are connected by a conductive wire. Next, a resin layer is formed on one surface of the wiring board with an insulating resin to cover the wires and the semiconductor chip. Next, a protruding electrode such as a ball electrode is formed on the base electrode surface of each product forming portion on the back surface of the wiring board not covered with the resin layer. Next, the wiring board is cut along with the resin layer at the boundary of the product forming portion to manufacture a plurality of semiconductor devices (for example, Patent Document 1).

JP 2002-110718 A

  The present applicant is also proceeding to reduce the size and thickness of the semiconductor device having the BGA structure. It has been found that the conventional BGA structure semiconductor device has the following problems. (1) The electrode of the semiconductor chip and the wiring layer are connected by a wire, but in the wire connection structure, the wire is stretched so as to draw an arc (loop), so the thickness of the resin layer covering the wire is increased due to the loop structure. The thinning of the semiconductor device is hindered.

  (2) In wire bonding, an impact at the time of connection is applied to the region below the wire connection location. Therefore, in order to prevent element destruction, the wire connection position, that is, the electrode (electrode pad) is off the active region of the semiconductor chip. Placed in a different position. Usually, electrodes (electrode pads) are arranged along each side of the rectangular semiconductor chip and at positions close to each side. For this reason, as the number of pins (number of external electrode terminals) of the semiconductor device increases, the number of wires also increases and the number of electrodes of the semiconductor chip also increases. As a result of the electrodes being arranged side by side along the periphery of the semiconductor chip, the size of the semiconductor chip increases as the number of pins increases as the function of the semiconductor device improves, which hinders the size reduction of the semiconductor device.

  An object of the present invention is to provide a semiconductor device that can be reduced in thickness and size and a method for manufacturing the same.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

(1) The semiconductor device
A wiring board having a plurality of wiring layers on an upper surface, and having a plurality of base electrode layers electrically connected to the wiring layer via through conductors on a lower surface opposite to the upper surface;
A semiconductor chip fixed to the upper surface of the wiring board and having a plurality of electrodes on the upper surface;
An interlayer insulating film formed on an upper surface of the wiring substrate and selectively covering the semiconductor chip and the wiring layer;
From the conductor layer formed on the interlayer insulating film, one end side is connected to the electrode of the semiconductor chip through the interlayer insulating film, and the other end side is connected to the wiring layer through the interlayer insulating film And wiring
A sealing body provided on the upper surface side of the wiring board and made of an insulator covering the wiring;
And a protruding electrode provided on the base electrode layer.

Such a semiconductor device is manufactured by a manufacturing method having the following steps.
(A) a first surface and a second surface that is the opposite surface of the first surface, and a plurality of product forming portions partitioned vertically and horizontally on the first surface; Has a plurality of wiring layers formed on the first surface and a plurality of base electrode layers formed on the second surface and electrically connected to the wiring layers through through conductors. Preparing a wiring mother board;
(B) fixing a semiconductor chip having a plurality of electrodes on the top surface of the first surface of each product forming portion;
(C) detecting a fixed position of the semiconductor chip in each of the product forming portions, and detecting a positional relationship between the electrode and the wiring layer;
(D) forming an interlayer insulating film covering the semiconductor chip and the wiring layer on the first surface of the product forming portion;
(E) forming a contact hole in the interlayer insulating film on the electrode and the wiring layer based on positional relationship detection information between the electrode and the wiring layer to expose the electrode and the wiring layer;
(F) forming a conductor layer formed on the first surface of the product forming portion and filling the contact hole;
(G) Based on the positional relationship detection information of the electrode and the wiring layer, a wiring having one end connected to the electrode through the contact hole and the other end connected to the conductor layer through the contact hole Forming, and
(H) a step of covering the first surface of the product forming portion with an insulating resin layer;
(I) forming a bump electrode overlying the base electrode layer on the second surface of the product forming portion;
(J) cutting the wiring mother board along a partition line of the partition to manufacture a plurality of semiconductor devices,
The formation of the contact hole in the step (e) and the formation of the wiring in the step (g) are performed by a photolithography technique and an etching technique, and the photolithography technique is formed by a direct drawing apparatus that does not use a photomask. Manufactured by.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the means (1), (a) the conductor layer of the wiring substrate and the electrode of the semiconductor chip are connected by the wiring composed of the conductor layer extending over the interlayer insulating film instead of the wire drawing the loop. The thickness of the sealing body covering the wiring can also be reduced, and the semiconductor device can be made thinner.

  (B) The conductor layer of the wiring board and the electrode of the semiconductor chip are connected by the conductor layer formation and the wiring formed by the subsequent photolithography technique and etching technique, so that a large impact is applied to the semiconductor chip like wire bonding. There is no. Therefore, the electrodes of the semiconductor chip can be arranged on the active region.

  (C) In the case of wire bonding, when the diameter of the wire is about 25 μm, the size of the electrode serving as the bonding pad is a square having a side of about 80 μm. On the other hand, when the connection is made by the wiring of the conductor layer, a square having a side of about 10 μm is sufficient. As a result, it is possible to reduce the size of the semiconductor chip because the area occupied by the electrodes is reduced.

  (D) The wiring formed by patterning the conductor layer by the photolithography technique and the etching technique has a free plane pattern, and can be freely bent and extended. As a result, there is an effect that the electrodes can be arranged between the electrodes freely arranged in the active region.

  (E) As in (b) to (d) above, the electrode as a bonding pad can be made small, the electrode can be arranged on the active region of the semiconductor chip, and the wiring can be bent freely. Therefore, the degree of freedom in electrode layout and wiring design is increased. Therefore, compared with the conventional semiconductor chip structure in which the electrode is formed outside the active region, the electrode forming region outside the active region can be reduced or eliminated, and the semiconductor chip can be made smaller. You can also. Miniaturization of the semiconductor chip promotes miniaturization of the semiconductor device.

  (F) Photolithography in wiring formation can be formed with a low-cost and high-throughput photomaskless exposure apparatus having a resolution of about 10 μm, that is, a direct drawing apparatus, and a reduction in manufacturing cost of the semiconductor device can be achieved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.

  FIGS. 1 to 23 are diagrams related to the semiconductor device according to the first embodiment of the present invention, FIGS. 1 to 3 are diagrams related to the structure of the semiconductor device, and FIGS. 4 to 23 are diagrams related to the method of manufacturing the semiconductor device. It is. 24 to 26 are diagrams showing modifications of the first embodiment.

  The semiconductor device 1 according to the first embodiment has a structure as shown in FIGS. 1 is a cross-sectional view of the semiconductor device, FIG. 2 is a plan view of the semiconductor device excluding a part of the sealing body, and FIG. 3 is a bottom view of the semiconductor device.

  The semiconductor device 1 has a rectangular (for example, square) wiring board 2. As shown in FIGS. 1 and 2, the semiconductor chip 3 is mounted (fixed) on the central portion of the first surface 2a (upper surface in FIG. 1) of the wiring board 2 via an adhesive (not shown). . A plurality of wiring layers 4 are provided in the surrounding wiring board region (second surface) that is separated from the semiconductor chip 3. The wiring layer 4 is an elongated piece from the center of the wiring board 2 to the outside, and has a structure extending in a direction orthogonal to each side of the wiring board 2, for example.

  As shown in FIG. 1, a conductor 5 penetrating the wiring board 2 is provided in the vicinity of the outer end of each wiring layer 4. The conductor 5 is provided on the second surface 2b opposite to the first surface 2a of the wiring board 2, but is not particularly limited, and is electrically connected to the circular base electrode 6. A protruding electrode 7 is formed on the base electrode 6 so as to overlap. In the first embodiment, the protruding electrode 7 is formed of, for example, a ball electrode made of solder. The protruding electrodes 7 are arranged in a rectangular frame shape as shown in FIG. The wiring board 2 is made of, for example, a glass epoxy resin plate having a thickness of about 200 μm. Further, on the surfaces of the wiring layer 4 and the base electrode 6, a plating film (not shown) is formed to improve the connection state with the wiring 13 and the protruding electrode 7.

  On the first surface 2 a side of the wiring substrate 2, an interlayer insulating film 10 made of an insulating resin is formed on the whole to cover the semiconductor chip 3 and the wiring layer 4. The interlayer insulating film 10 is formed of, for example, a polyimide resin having a thickness of 10 to 20 μm. Contact holes 11 and 12 are provided in the interlayer insulating film 10 that covers each electrode (see FIG. 2 and FIG. 10: electrode 9) of the semiconductor chip 3 of the interlayer insulating film 10 and the inner end side of the wiring layer 4. By forming the contact holes 11 and 12, the electrode 9 (electrode pad 9) and the wiring layer 4 are exposed. The electrode exposed at the bottom of the contact hole 11 and the corresponding wiring layer 4 (wiring layer 4 exposed at the bottom of the contact hole 12) are formed of a conductor layer formed so as to lie on the interlayer insulating film 10. The wiring 13 is electrically connected. The conductor layer is formed by applying a conductor paste, printing, or the like.

  A sealing body 14 made of an insulating resin is formed on the entire first surface 2 a of the wiring board 2. In Example 1, the sealing body 14 is formed by cutting an insulating resin layer formed flat by transfer molding. Therefore, the upper surface of the sealing body 14 is a flat surface.

  The thickness of the sealing body 14 is sufficiently thinner than the thickness of the sealing body of the wire bonding structure. The thinning of the sealing body 14 is the thinning of the semiconductor device 1 as it is.

  Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. FIG. 4 is a flowchart showing the method of manufacturing the semiconductor device according to the first embodiment.

  In the semiconductor device 1 of the first embodiment, as shown in the flowchart of FIG. 4, the wiring mother board preparation S01, the semiconductor chip mounting S02, the semiconductor chip fixing position detection S03, the interlayer insulating film formation S04, and the wiring layer formation on the interlayer insulating film For example, through the steps of forming an opening (maskless) S05, forming a conductor layer S06, forming a wiring S07 by selectively removing the conductor layer, forming a resin layer S08, forming a protruding electrode S09, forming the wiring mother board and cutting the resin layer S10 The

  In manufacturing the semiconductor device 1, as shown in FIG. 5, a wiring mother board 20 is prepared (S01). The wiring mother board 20 is composed of a wiring board having a first surface 2a and a second surface 2b (see FIG. 8) which is the opposite surface of the first surface 2a. The wiring mother board 20 is made of, for example, a glass epoxy resin plate having a thickness of about 200 μm.

  As shown in FIG. 5, the wiring mother board 20 has a structure having a plurality of product forming portions 21 partitioned in the plane direction. The product forming portions 21 are arranged in a matrix in the vertical and horizontal directions. The product forming part 21 is a part where one semiconductor device is manufactured. In FIG. 5, the boundaries of the product forming portions 21 are indicated by thick lines, but such lines do not exist in the actual wiring motherboard 20 and are provided for convenience of explanation. In the following description, a method for manufacturing a semiconductor device will be described mainly using this single product forming portion 21.

  The product forming portion 21 has a structure as shown in FIGS. 6 is a plan view showing the first surface 2a of the product forming portion 21, FIG. 7 is a bottom view showing the second surface of the product forming portion 21, and FIG. 8 is a sectional view taken along line XX in FIG. .

  The product forming unit 21 is partitioned into a rectangular (for example, square) region. In the rectangular product forming portion 21, a plurality of wiring layers 4 are formed on the first surface 2a of the wiring mother board 20, as shown in FIG. In the product forming part 21, the central region of the wiring mother board 20 is a region where the semiconductor chip is fixed. Therefore, the wiring layer 4 is provided around the area where the semiconductor chip is fixed. The wiring layer 4 is an elongated piece extending from the center of the wiring mother board 20 to the outside, and has a structure extending in a direction orthogonal to each side of the product forming portion 21, for example. A plurality of wiring layers 4 are arranged in parallel at predetermined intervals along each side.

  Further, as shown in FIG. 7, a circular base electrode 6 is formed on the second surface 2b of the wiring mother board 20 corresponding to the vicinity of the outer end of the wiring layer 4 as shown in FIG. The base electrode 6 and the wiring layer 4 facing the base electrode 6 are electrically connected by a conductor 5 penetrating the wiring motherboard 20. FIG. 9 schematically shows the conductor 5 that connects the wiring layer 4 and the base electrode 6. The wiring layer 4, the conductor 5, and the base electrode 6 are formed by applying or printing a conductor paste or the like and patterning. The wiring layer 4 and the base electrode 6 have a thickness of about 10 μm.

  As shown in FIGS. 10 and 11, the semiconductor chip 3 is positioned and fixed (mounted) on the first surface 2 a of the wiring motherboard 20 via an adhesive (not shown) with respect to such a product forming portion 21. (S02). An electrode (electrode pad) 9 is located on the upper surface of the semiconductor chip 3. As shown in FIG. 10, in the first embodiment, the electrodes 9 are positioned on the extended lines of the wiring layers 4 by mounting with accurate positioning. However, as shown in FIG. 12, in some cases, some of the semiconductor chips 3 may be mounted with displacement. In FIG. 12, the semiconductor chip 3 colored lightly is the misalignment chip 3a. In some misalignment chips 3 a, the electrode 9 may be removed from the extended line of the wiring layer 4. Depending on the adhesive used, a bonding pad made of a conductor layer may be formed on the first surface 2a of the wiring motherboard 20.

  Next, the fixing position of the semiconductor chip 3 in each product forming part 21 of the wiring mother board 20 is detected, and the positional relationship of the electrode 9 with respect to the wiring layer 4 is detected (S03).

  Next, as shown in FIG. 13, the interlayer insulating film 10 is formed over the entire first surface 2a of the wiring motherboard 20 (S04). The interlayer insulating film 10 is formed of, for example, a polyimide resin having a thickness of 10 to 20 μm.

  Next, an opening for forming a wiring layer is formed in the interlayer insulating film 10 by photolithography and etching (S05). Therefore, as shown in FIG. 13, a photoresist film 25 is formed so as to cover the interlayer insulating film 10, and then an electron beam 27 is transferred from the drawing unit 26 of the direct drawing apparatus (maskless exposure apparatus) not using the photomask to the photoresist film. The photoresist film 25 is partially exposed by irradiating a predetermined portion 25. As shown in FIG. 13, the photosensitive portions 28 and 29 correspond to the portions where the contact holes 11 and 12 are formed, and are on the electrodes 9 and the wiring layer 4 of the semiconductor chip 3. Next, the photoresist film 25 is developed to remove the photosensitive portions 28 and 29, and further etched. As a result, the interlayer insulating film 10 corresponding to the photosensitive portions 28 and 29 is etched, and contact holes 11 and 12 are formed in the interlayer insulating film 10 as shown in FIGS. The electrode 9 is exposed at the bottom of the contact hole 11, and the wiring layer 4 is exposed at the bottom of the contact hole 12.

  In the exposure (photosensitive) processing by the direct drawing apparatus in the formation of the contact holes 11 and 12, exposure is performed based on the detection information in step S03. That is, in the semiconductor chip fixed position detection S03, the fixed position of the semiconductor chip 3 in each product forming part 21 of the wiring mother board 20 is detected. Then, a good determination is made for the positional deviation in the predetermined area. However, the misalignment chip 3a having a large misalignment as shown in FIG. 12 is determined to be defective, and the misalignment information is accumulated. When the contact hole 11 is formed on the basis of design criteria, the misalignment tip 3a is detached from the electrode 9, and the electrode 9 is not positioned at the bottom of the contact hole 11, or only a part of the electrode 9 is disposed. It will not be exposed. As a result, when the wiring 13 is formed, the electrode 9 and the wiring layer 4 are not electrically connected, or even if they are connected, they may cause a short circuit failure.

  Therefore, in the first embodiment, in the case of the misalignment chip 3a, the direct drawing apparatus automatically corrects the exposure position based on the detection information in step S03. FIG. 16 is a schematic diagram showing the semiconductor chip 3 (position displacement chip 3a) mounted on the wiring motherboard 20 while being displaced. FIG. 16 also shows contact holes 11 and 12.

  When detecting the displacement of the fixed position of the semiconductor chip, as shown in FIG. 16, the displacement of the semiconductor chip 3 with respect to the origin position O (0, 0) of the X axis and the Y axis is detected. For example, the coordinates of a predetermined corner P (x, y) of the semiconductor chip 3 are detected, and the inclination angle θ of one side of the semiconductor chip 3 with respect to the X axis is obtained. The size of the semiconductor chip 3 varies because, for example, the silicon substrate is cut by cracking (dicing) or dicing. Therefore, for example, the corner where the inner line of the dicing area (line) intersects is P, and the inclination angle θ with respect to the X axis of the inner line of the dicing area (line) is obtained. Thereby, the positional relationship of the electrode 9 with respect to the wiring layer 4 can be confirmed. Based on this detection information, the photosensitive portions 28 and 29 of the photoresist film 25 are formed. When the position variation of the wiring layer 4 is large, the positions of the wiring layer 4 and the electrode 9 in each product forming part 21 are detected, and the contact holes 11 and 12 are formed based on this detection information. Good.

  Next, as shown in FIG. 16, a conductor layer 13a is formed on the entire first surface 2a of the wiring motherboard 20 (S06). The conductor layer 13a is formed by applying a conductor paste, printing, or the like. The conductor layer 13a is formed with a thickness of about 10 μm, for example.

  Next, the conductor layer 13a is patterned by photolithography and etching techniques to electrically connect the electrode 9 exposed at the bottom of the predetermined contact hole 11 and the wiring layer 4 exposed at the bottom of the predetermined contact hole 12. The wiring 13 to be formed is formed. Therefore, as shown in FIG. 17, a photoresist film 35 is formed so as to cover the conductor layer 13a, and then the electron beam 27 emitted directly from the drawing unit 26 of the drawing apparatus is applied to the photoresist film in the same manner as in step S05. The photoresist film 35 in the predetermined contact hole 12 portion to the predetermined contact hole 12 portion is exposed by irradiation over a predetermined length region a of 35. Thereafter, the photoresist film 35 is developed. The photoresist film 35 forms a photoresist in which a photosensitive portion remains by development. Therefore, by etching the conductor layer 13a using the remaining photoresist film 35 as an etching mask, the wiring 13 that electrically connects the electrode 9 and the wiring layer 4 is formed as shown in FIGS. (S07). In the first embodiment, the wiring 13 has a linearly extending pattern. However, a bent pattern can be formed by performing exposure while bending and moving the drawing portion 26.

  Next, as shown in FIG. 20, the entire side of the first surface 2a of the wiring motherboard 20 is covered with an insulating resin layer 14a (S08). The resin layer 14a is not particularly limited, but is formed by a transfer molding apparatus. For this reason, as shown in FIG. 21, the upper surface of the resin layer 14a becomes flat. FIG. 21 is a partial cross-sectional view taken along line XX of FIG. The resin layer 14a is made of, for example, an epoxy resin.

  Next, in a state where the second surface 2b of the wiring mother board 20 is the upper surface, the protruding electrode 7 is formed so as to be superimposed on the base electrode 6 exposed on the second surface 2b (S09). The protruding electrode 7 is formed, for example, by attaching a solder ball and forming it into a hemisphere by reflow (reheating treatment).

  Next, as shown in FIG. 23, the wiring mother board 20 is cut along the boundary lines of the product forming portions 21 to manufacture a plurality of semiconductor devices 1 (S10). FIG. 23 shows a substrate divided with the first surface 2a of the wiring mother board 20 as the upper surface. By this division, the semiconductor device 1 shown in FIGS. 1 to 3 is manufactured. The wiring mother board 20 is divided into the wiring board 2, and the resin layer 14 a is divided into the sealing body 14.

  24 to 26 are cross-sectional views of a semiconductor device which is a modification of the first embodiment. A semiconductor device 1 of FIG. 24 is a semiconductor device that is a first modification of the first embodiment. This semiconductor device 1 is the same as the semiconductor device 1 of Example 1, except that a flat conductor layer (land) 7a is formed on the base electrode 6 to form a protruding electrode. That is, the semiconductor device 1 is a semiconductor device having an LGA structure. The flat conductor layer (land) 7a can be formed by printing or the like, and the manufacturing cost of the semiconductor device 1 can be reduced.

  A semiconductor device 1 of FIG. 25 is a semiconductor device that is a second modification of the first embodiment. The semiconductor device 1 of FIG. 25 is formed by applying an insulating resin such as a polyimide resin without forming the sealing body 14 by transfer molding as in the first embodiment. Since the sealing body 14 can be as thin as about 10 μm, the semiconductor device 1 can be further thinned.

  A semiconductor device 1 of FIG. 26 is a semiconductor device that is a third modification of the first embodiment. The semiconductor device 1 of FIG. 26 has a structure in which a recess 40 is formed in the first surface 2a of the wiring substrate 2 in the semiconductor device 1 of the first embodiment, and the semiconductor chip 3 is mounted in the recess 40. In the semiconductor device 1, the height of the upper surface of the semiconductor chip 3 is reduced by the depth of the recess 40, and thus the thickness of the semiconductor device 1 can be reduced by the depth of the recess 40.

The first embodiment has the following effects.
(1) Since the wiring layer 4 of the wiring board 2 and the electrode 9 of the semiconductor chip 3 are connected by a wiring 13 made of a conductor layer extending over the interlayer insulating film 10 instead of a wire that draws a loop, the wiring 13 The thickness of the sealing body 14 covering the semiconductor device 1 can also be reduced, and the semiconductor device 1 can be reduced in thickness.

  (2) Since the wiring layer 4 of the wiring board 2 and the electrode 9 of the semiconductor chip 3 are connected by the wiring 13 formed by the conductor layer formation and the subsequent photolithography technique and etching technique, the semiconductor chip 3 is connected like wire bonding. There is no big impact on Therefore, the electrode 9 of the semiconductor chip 3 can be disposed also on the active region.

  (3) In the case of wire bonding, when the diameter of the wire is about 25 μm, the size of the electrode serving as the bonding pad is a square having a side of about 80 μm. On the other hand, when connecting with the wiring 13 by a conductor layer, even if the square of one side of the electrode 9 is about 10 micrometers is sufficient. As a result, the semiconductor chip 3 can be reduced in size from the reduction of the area occupied by the electrodes 9.

  (4) As in the above (2) and (3), the electrode 9 as a bonding pad can be made small, and the electrode 9 can be arranged on the active region of the semiconductor chip 3, so that the electrode layout is free. The degree increases. Therefore, compared with a conventional semiconductor chip structure in which electrodes are formed outside the active region, the electrode forming region outside the active region can be reduced or eliminated, and the semiconductor chip 3 can be made smaller. You can also Miniaturization of the semiconductor chip 3 promotes miniaturization of the semiconductor device 1.

  (5) Photolithography for forming the wiring 13 can be formed with a low-cost and high-throughput photomaskless exposure apparatus having a resolution of about 10 μm, that is, a direct drawing apparatus, and the manufacturing cost of the semiconductor device 1 can be reduced. Can be achieved.

  (6) In the case of the semiconductor device 1 having the LGA structure, the manufacturing cost can be reduced.

  (7) In the semiconductor device 1 in which the sealing body 14 is formed by applying an insulating resin, the semiconductor device 1 can be further reduced in thickness.

  (8) In the semiconductor device 1 in which the recess 40 is provided in the wiring substrate 2 and the semiconductor chip 3 is mounted in the recess 40, the thickness of the recess 40 can be reduced.

  27 and 28 are diagrams related to the semiconductor device according to the second embodiment of the present invention, FIG. 27 is a cross-sectional view of the semiconductor device, and FIG. 28 is a plan view in which a part of the sealing body of the semiconductor device is removed.

  In the semiconductor device 1 of the second embodiment, in the semiconductor device 1 of FIG. 1, the wiring 13 connected to the electrode 9 that becomes the ground potential (GND) of the semiconductor chip 3 is formed on the interlayer insulating film 10 on the semiconductor chip 3. It is a structure connected to the shield wiring part 45 which consists of a conductor layer which has a large area. FIG. 28 is a plan view in which a part of the sealing body 14 is removed, and shows a wiring 13 and a shield wiring portion 45 made of a conductor layer formed on the interlayer insulating film 10.

  In FIG. 28, the four wirings 13 connected to the ground electrode of the semiconductor chip 3 are connected to the shield wiring part 45. The shield wiring portion 45 may be formed when the conductor layer 13a is patterned when the wiring 13 is formed.

  In the semiconductor device 1 according to the second embodiment, since the entire semiconductor chip 3 is shielded by the shield wiring portion 45 on the interlayer insulating film 10, the semiconductor device 1 operates stably and has high reliability.

  FIG. 29 is a schematic plan view of a semiconductor device that is Embodiment 3 of the present invention. The semiconductor device 1 according to the third embodiment requires the wiring 13 that connects the electrode 9 of the semiconductor chip 3 and the wiring layer 4 provided on the first surface 2a of the wiring substrate 2 in the semiconductor device 1 according to the first embodiment. It is bent accordingly. Further, the wiring 13 (ground wiring) connected to the ground electrode of the semiconductor chip 3 is thicker than other wirings (for example, signal wiring). The thickening wiring can be applied to power supply potential wiring for supplying power in addition to the ground wiring.

  The electrode 9 can be disposed at any position on the semiconductor chip 3 by bending the wiring 13. This can be achieved by connecting the electrode 13 with the wiring 13 by (1) not damaging the active region of the semiconductor chip 3 due to an impact for bonding unlike the conventional wire bonding method. This is possible by forming the wiring 13 directly using a drawing apparatus.

  Further, the adjustment of the thickness of the wiring can be freely determined by directly adjusting the thickness of the electron beam 27 of the drawing apparatus. In FIG. 29, the wiring indicated by the thick line is the ground wiring 13d.

  In the semiconductor device 1 according to the third embodiment, since the conductor layer 13a is patterned by the photolithography technique and the etching technique to form the wiring 13, the wiring pattern can be freely selected including bending. In addition, since no impact is applied to the electrode 9, the electrode 9 can be freely arranged on the active region of the semiconductor chip 3. Moreover, the electrode 9 as a bonding pad can be made small. Therefore, the electrode 9 can be made small, the electrode 9 can be arranged on the active region of the semiconductor chip 3, and the wiring 13 can be formed into a free pattern including a bend. The degree of freedom in electrode layout and wiring design in manufacturing increases. Therefore, in the semiconductor device 1 of the third embodiment, the electrode formation region outside the active region of the semiconductor chip 3 can be reduced compared to the conventional semiconductor chip structure in which the electrode is formed outside the active region. Alternatively, it can be abolished, and the semiconductor chip 3 can be made smaller. Miniaturization of the semiconductor chip 3 promotes miniaturization of the semiconductor device 1.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor.

It is sectional drawing of the semiconductor device which is Example 1 of this invention. FIG. 3 is a plan view in which a part of the sealing body of the semiconductor device of Example 1 is removed. 2 is a bottom view of the semiconductor device of Example 1. FIG. 3 is a flowchart illustrating a method for manufacturing the semiconductor device according to the first embodiment. 3 is a plan view showing a first surface of a wiring mother board used in the manufacture of the semiconductor device of Example 1. FIG. It is a top view of the product formation part of the said wiring mother board. It is a bottom view which shows the 2nd surface of the said product formation part. It is sectional drawing which follows XX of FIG. It is a top view of the product formation part which described the conductor which connects the wiring of the upper and lower surfaces of the said wiring mother board. It is a top view of the said product formation part carrying a semiconductor chip. It is sectional drawing which follows XX of FIG. FIG. 3 is a schematic plan view showing the wiring mother board on which a semiconductor chip is mounted. It is a schematic diagram which shows the state which selectively exposes the photoresist film formed on the upper surface of the said product formation part with the drawing apparatus. It is a top view which shows the state which formed the through hole selectively in the interlayer insulation film formed in the upper surface of the said product formation part. It is sectional drawing which follows XX of FIG. FIG. 3 is a schematic diagram showing a semiconductor chip mounted on the wiring mother board with a displacement. It is a schematic diagram which shows the state which selectively exposes the photoresist film on the conductor layer formed in the upper surface of the said product formation part with the drawing apparatus. It is a top view of the said wiring mother board which shows the wiring selectively formed on the interlayer insulation film. It is sectional drawing which follows XX of FIG. It is a top view of the said wiring mother board which formed the resin layer in the upper surface. FIG. 20 is a cross-sectional view of a single wiring mother board taken along line XX in FIG. 19. It is sectional drawing of the said product formation part which formed the protruding electrode in the 2nd surface by making a 2nd surface into an upper surface. It is a top view which shows the several semiconductor device manufactured by dividing | segmenting the said wiring mother board. 7 is a cross-sectional view of a semiconductor device that is Modification 1 of Embodiment 1. FIG. It is sectional drawing of the semiconductor device which is the modification 2 of the present Example 1. FIG. It is sectional drawing of the semiconductor device which is the modification 3 of the present Example 1. FIG. It is sectional drawing of the semiconductor device which is Example 2 of this invention. It is the top view which removed a part of sealing body of the semiconductor device of the present Example 2. It is a schematic diagram of the semiconductor device which is Example 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Wiring board, 2a ... 1st surface, 2b ... 2nd surface, 3 ... Semiconductor chip, 3a ... Position shift chip, 4 ... Wiring layer, 5 ... Conductor, 6 ... Base electrode, 7 ... Projection electrode, 7a ... Flat conductor layer (land), 9 ... Electrode (electrode pad), 10 ... Interlayer insulating film, 11, 12 ... Contact hole, 13 ... Wiring, 13a ... Conductor layer, 13d ... Ground wiring, 14 DESCRIPTION OF SYMBOLS ... Sealing body, 14a ... Resin layer, 20 ... Wiring mother board, 21 ... Product formation part, 25 ... Photoresist film, 26 ... Drawing part, 27 ... Electron beam, 28, 29 ... Photosensitive part, 35 ... Photoresist film, 40 ... depression, 45 ... shield wiring part.

Claims (5)

A wiring board having a plurality of wiring layers on an upper surface, and having a plurality of base electrode layers electrically connected to the wiring layer via through conductors on a lower surface opposite to the upper surface;
A semiconductor chip fixed to the upper surface of the wiring board and having a plurality of electrodes on the upper surface;
An interlayer insulating film formed on an upper surface of the wiring substrate and selectively covering the semiconductor chip and the wiring layer;
From the conductor layer formed on the interlayer insulating film, one end side is connected to the electrode of the semiconductor chip through the interlayer insulating film, and the other end side is connected to the wiring layer through the interlayer insulating film And wiring
A sealing body provided on the upper surface side of the wiring board and made of an insulator covering the wiring;
And a protruding electrode provided to overlap the base electrode layer. The semiconductor device according to claim 1, wherein a recess is provided on an upper surface of the wiring substrate, and the semiconductor chip is fixed in the recess. 3. The semiconductor device according to claim 1, wherein the wiring connected to the electrode serving as a ground potential of the semiconductor chip is wider than other wirings. The wiring connected to the electrode serving as the ground potential of the semiconductor chip is connected to a shield wiring portion formed of a conductor layer having a predetermined area on the interlayer insulating film on the semiconductor chip. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. A first surface and a second surface opposite to the first surface, the first surface having a plurality of product forming portions partitioned vertically and horizontally, wherein the product forming portion is the first surface; A wiring mother board having a plurality of wiring layers formed on one surface and a plurality of base electrode layers formed on the second surface and electrically connected to the wiring layers via through conductors The process of preparing
Fixing a semiconductor chip having a plurality of electrodes on the top surface of the first surface of each product forming portion;
Detecting a fixed position of the semiconductor chip in each of the product forming portions, and detecting a positional relationship between the electrode and the wiring layer;
Forming an interlayer insulating film covering the semiconductor chip and the wiring layer on the first surface of the product forming portion;
Forming a contact hole in the interlayer insulating film on the electrode and the wiring layer based on the positional relationship detection information of the electrode and the wiring layer to expose the electrode and the wiring layer;
Forming a conductor layer formed on the first surface of the product forming portion and filling the contact hole;
Forming a wiring having one end connected to the electrode through the contact hole and the other end connected to the conductor layer through the contact hole based on positional relationship detection information between the electrode and the wiring layer; When,
Covering the first surface of the product forming portion with an insulating resin layer;
Forming a bump electrode overlying the base electrode layer on the second surface of the product forming portion;
Cutting the wiring mother board along the partition line of the partition to produce a plurality of semiconductor devices,
The method for manufacturing a semiconductor device is characterized in that the contact hole and the wiring are formed by a photolithography technique and an etching technique, and the photolithography technique is formed by a direct drawing apparatus that does not use a photomask.

Images