JP2006012999A - Method for manufacturing solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a solid-state imaging device with good image characteristics by reducing global steps by simple steps, miniaturizing pixels and suppressing shading.
A surface of a semiconductor substrate on which a MOS transistor is formed is covered with a silicon oxide film. A resist pattern 11 is formed on the silicon oxide film 3. The silicon oxide film 3 is etched so that a part of its thickness remains. By removing the resist pattern 11 and etching the entire surface of the silicon oxide film 3 until the remaining silicon oxide film 3 is completely removed, the thickness of the silicon oxide film 3 covered with the resist pattern 11 is reduced. The sidewall spacer 7 is formed while reducing the thickness. Then, after covering the entire surface of the semiconductor substrate 1 with an interlayer insulating film, the surface thereof is flattened. Thereby, a global level | step difference can be reduced.
[Selection] Figure 1

Description

  The present invention relates to a method for manufacturing a solid-state imaging device, and more particularly to a method for manufacturing a solid-state imaging device that can flatten a substrate surface covered with an interlayer insulating film.

  In a solid-state imaging device, an LDD (Lightly Doped Drain) structure is employed for a MOS transistor (for example, Patent Document 1). The LDD structure is for suppressing thermal diffusion in the channel region to suppress increase in leakage current and fluctuation in characteristics. For example, the LDD structure is realized by forming a high concentration impurity region and a low concentration impurity region in the drain region. Is done. As a mask for forming such an impurity region, a side wall spacer is formed on the side wall of the gate electrode.

  FIG. 5 is a cross-sectional view of the substrate and its upper surface at each stage in the process of manufacturing an LDD structure MOS transistor. Hereinafter, a method of manufacturing a MOS transistor having an LDD structure will be described with reference to FIG.

  FIG. 5A shows a state where the surface of the substrate on which the MOS transistor is formed is covered with an oxide film. First, the gate insulating film 24 a is formed on the main surface of the semiconductor substrate 21. Then, isolation oxide films 22a and 22b are formed by LOCOS (local oxidation of silicon) method. Next, the gate electrode 24 is formed on the main surface of the semiconductor substrate 21 between the isolation oxide films 22a and 22b via the gate insulating film 24a.

  Next, using the isolation oxide films 22a and 22b and the gate electrode 24 as a mask, an impurity having a conductivity type opposite to that of the semiconductor substrate 21 is implanted into the main surface of the semiconductor substrate 21 by an ion implantation method or the like. As a result, a source region 25, a drain region 26, and a photodiode (hereinafter referred to as PD) region (not shown) are formed on the main surface of the semiconductor substrate 21. The source region 25 includes a floating diffusion (hereinafter referred to as FD) region for converting signal charges generated in the PD region into a signal voltage.

  By forming each diffusion layer described above, a MOS transistor is formed on the main surface of the semiconductor substrate 21. The main surface of the semiconductor substrate 21 is covered with a silicon oxide film 23. A part of the silicon oxide film 23 becomes a side wall spacer for forming an LDD structure, as will be described later.

  FIG. 5B shows a state in which a mask pattern for patterning the silicon oxide film 23 is formed on the substrate. First, a resist film is formed by applying a resist on the silicon oxide film 23. The resist film is exposed and developed to form a resist pattern 31 patterned into a desired shape. The resist pattern 31 is patterned into a shape that protects the PD region and the source region 25 from ion irradiation damage by a plasma etching apparatus in an etching process described later.

  FIG. 5C shows a state after the silicon oxide film 23 is etched (etched back). Using the resist pattern 31 as a mask, the silicon oxide film 23 is etched back by a plasma etching apparatus. Thereby, a silicon oxide film 23a patterned in a desired shape is obtained. A sidewall spacer 27 is formed on the side wall of the gate electrode 24 on the drain region 26 side.

  FIG. 5D shows a state where a MOS transistor having an LDD structure is formed on the main surface of the substrate. First, using the sidewall spacer 27 as a mask, an impurity having the same conductivity type as the above-described impurity and having a high impurity concentration is implanted toward the drain region 26. As a result, a high concentration impurity region 26a is formed in the drain region 26, and a MOS transistor having an LDD structure is obtained. Then, the resist pattern 31 is removed by an ashing process using a plasma ashing apparatus.

  The semiconductor substrate 21 configured as described above can be flattened by covering the surface with an interlayer insulating film. FIG. 6A shows a state in which the surface of the semiconductor substrate 21 on which the LDD structure MOS transistor is formed is covered with an interlayer insulating film 32. First, a BPSG (Boro-Phosho Silicate Glass) film is formed on the entire surface of the substrate. Then, the interlayer insulating film 32 is formed by annealing the BPSG film.

  Since the surface of the interlayer insulating film 32 is uneven and has a large surface step, a surface flattening process such as a CMP (Chemical Mechanical Polishing) process is performed. FIG. 6B shows a state after the CMP process is performed on the interlayer insulating film 32. Although the surface of the interlayer insulating film 32 is generally planarized by the surface planarization treatment, the rise of the interlayer insulating film 32 is increased near the upper portion of the gate electrode 24. For this reason, a surface level difference H2 occurs on the surface of the substrate. This is because the thickness d3 of the silicon oxide film 23a on the gate electrode 24 is large, so that the level difference between the substrate surface and the upper surface of the silicon oxide film 23a on the gate electrode 24 is large. The surface level difference H2 is about 150 nm or more, although it varies slightly depending on the size and layout of the pixel cell.

  Solid-state imaging is performed by forming contact holes for forming wiring patterns, forming color filters, condenser lenses, and the like on the interlayer insulating film 32 that has been subjected to surface planarization as described above. A device is obtained.

  By the way, the solid-state imaging device includes a pixel unit in which a plurality of pixels are arranged in a matrix and a peripheral circuit unit arranged around the pixel unit. In the above description, the MOS transistor included in the pixel has been described as an example, but the MOS transistor is also included in the peripheral circuit portion. As described above, in each MOS transistor, since the interlayer insulating film 32 is raised on the gate electrode 24, the surface of the entire substrate is uneven.

Further, since the wiring rate of the polysilicon wiring in the pixel portion is higher than the wiring rate of the polysilicon wiring in the peripheral circuit portion, the rise of the interlayer insulating film 32 is directed from the peripheral portion of the substrate toward the vicinity of the center of the pixel portion. As a result, the surface step of the entire substrate becomes large. Such a surface step on the entire substrate is called a global step.
JP 2002-190586 A

  In the solid-state imaging device, miniaturization of the upper-layer aluminum wiring is progressing in particular because of the necessity of increasing the number of pixels while suppressing the increase in chip size. In order to realize such a wiring pattern, for example, a pattern is formed on the resist with a photolithography stepper having a high resolution but a shallow focal depth.

  However, if the global level difference is large, it is difficult to form a fine wiring pattern, and dimensional accuracy is not sufficiently ensured, which causes a problem in terms of reliability of the solid-state imaging device. Further, since the global level difference causes not only wiring failure but also shading, there is a demand for reduction thereof.

  In order to reduce the global level difference, it is most effective to reduce the thickness d3 of the silicon oxide film 23a on the gate electrode 24 in the pixel portion where the rise of the interlayer insulating film 32 is large. However, the silicon oxide film 23a has not only a role of preventing etching damage but also a role of forming the sidewall spacer 27 for forming the LDD structure. Therefore, in FIG. 6B, the thickness d3 of the silicon oxide film 23 cannot be made thinner than the thickness d1 of the sidewall spacer 27.

  Patent Document 1 proposes a technique in which the entire surface of the substrate is covered with a thin oxide film, and then a sidewall spacer is formed on the side wall of the gate electrode. However, this method involves a complicated manufacturing process. Further, since the number of etching processes performed in the vicinity of the drain region is increased, the drain region is easily damaged by etching, and image characteristics are easily deteriorated due to a leak current.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a solid-state imaging device that can reduce a global level difference with a simple process, reduce the size of pixels, suppress shading, and have good image characteristics.

  The invention for solving the above problems is directed to a method for manufacturing a solid-state imaging device in which a surface of a substrate is covered with an interlayer insulating film and the surface is flattened. In this manufacturing method, first, a gate electrode is formed on the main surface of a semiconductor substrate. Next, first, second, and third diffusion layers are formed by implanting impurities into the main surface of the semiconductor substrate. Next, a first insulating film that covers the surface of the semiconductor substrate is formed. Next, a mask layer pattern that covers at least the first diffusion layer among the first, second, and third diffusion layers is formed. Next, as the first etching process, the first insulating film is etched using the mask layer pattern as a mask so that a part of the thickness remains in the film thickness direction. Next, the mask layer pattern is removed. Next, as the second etching process, the entire surface of the first insulating film is etched until the first insulating film remaining by the first etching process is completely removed. As a result, the thickness of the first insulating film covered with the mask layer pattern is reduced, and a side wall spacer is formed on the side wall of the gate electrode. Next, the entire surface of the semiconductor substrate is covered with a second insulating film. Then, the surface of the second insulating film is planarized.

  The first diffusion layer is a photodiode, and the second diffusion layer is a floating diffusion. In the first etching process, it is preferable to etch back the first insulating film to 10% to 90% with respect to the film thickness direction.

  As described above, in the first etching process, the thickness of the first insulating film not covered with the mask layer pattern is reduced, and in the second etching process, the first insulating film having a reduced thickness is formed. By completely removing and forming the sidewall spacer, the step between the substrate surface and the first insulating film on the gate electrode can be reduced without changing the thickness of the sidewall spacer. As a result, the rise of the second insulating film on the gate electrode can be reduced, and thus the global level difference can be reduced.

  As described above, according to the method for manufacturing a solid-state imaging device of the present invention, the first insulating film covering the MOS transistor is patterned by performing the etching process twice, so that the MOS transistor adopting the LDD structure is adopted. Even in a solid-state imaging device including the above, it is possible to reduce the global level difference without changing the thickness of the sidewall spacer. As a result, a more flattened substrate surface can be obtained, so that wiring and the like can be patterned with high accuracy, and the manufacturing yield of the solid-state imaging device can be improved.

  Below, the manufacturing method of the solid-state imaging device concerning the embodiment of the present invention is explained. The solid-state imaging device according to the present embodiment is a CMOS-type solid-state imaging device, and includes a pixel unit in which a plurality of pixels are arranged in a matrix and a peripheral circuit unit arranged around the pixel unit. Each pixel and the peripheral circuit section are provided with a plurality of MOS transistors constituting amplifiers, switches and the like.

  Each pixel includes a first diffusion layer in which a PD region is formed, a second diffusion layer including an FD region and a source region, a third diffusion layer in which a drain region is formed, and a gate electrode. The PD region converts the received light into signal charges.

  Hereinafter, a method of manufacturing a solid-state imaging device according to an embodiment of the present invention will be described by taking a transfer MOS transistor for transferring a signal charge generated in a PD region as a transistor formed in a pixel. This will be described with reference to the drawings.

  FIG. 1 is a cross-sectional view of a substrate and its upper surface at each stage in the process of manufacturing a solid-state imaging device according to an embodiment of the present invention. FIG. 1A shows a state where the surface of the substrate on which the MOS transistor is formed is covered with an oxide film as a first insulating film. First, the gate insulating film 4 a is formed on the main surface of the silicon semiconductor substrate 1. Then, isolation oxide films 2a and 2b are formed by the LOCOS method. Next, the gate electrode 4 is formed on the main surface of the semiconductor substrate 1 between the isolation oxide films 2a and 2b via the gate insulating film 4a.

  Next, using the isolation oxide films 2a and 2b and the gate electrode 4 as a mask, an impurity having a conductivity type opposite to that of the semiconductor substrate 1 is implanted into the main surface of the semiconductor substrate 1 by an ion implantation method or the like. As a result, the first, second, and third diffusion layers are formed on the main surface of the semiconductor substrate 1. The first diffusion layer includes a PD region (not shown). The PD region converts the received light into signal charges. The second diffusion layer includes an FD region (not shown) and the source region 5. The FD region converts the signal charge generated in the PD region into a signal voltage. The source region 5 is an extension from the FD region. The FD region and the PD region are adjacent to each other with the gate electrode interposed therebetween. The third diffusion layer includes the drain region 6. An LDD is formed in the drain region 6 as will be described later.

  Thus, the main surface of the semiconductor substrate 1 on which the MOS transistor is formed is covered with a silicon oxide film 3 such as TEOS (tetraethoxy silane). The silicon oxide film 3 is formed with a film thickness of, for example, 150 nm to 200 nm by a thermal CVD (Chemical Vapor Deposition) method. A part of the silicon oxide film 3 serves as a side wall spacer for forming the LDD, as will be described later.

  FIG. 1B shows a state in which a mask pattern for patterning the silicon oxide film 3 is formed on the substrate. First, a resist film is formed by applying a resist on the silicon oxide film 3. The resist film is exposed and developed to form a resist pattern 11 patterned into a desired shape. The resist pattern 11 is patterned into a shape that protects the PD region and the source region 5 from ion irradiation damage by the plasma etching apparatus at the time of etch back described later.

  Here, the reason why the PD region and the source region 5 are protected from ion irradiation damage will be described. As described above, the PD area converts received light into signal charges and accumulates them, and the FD area transfers the signal charges generated in the PD area. Therefore, when the source region 5 including the PD region or the FD region is damaged, the obtained signal charge is lost as a leakage current through the defect of the etching damage layer generated on the surface of the semiconductor substrate 1. This is because the sensitivity of the solid-state imaging device is lowered and the image characteristics are deteriorated.

  FIG. 1C shows a state in which the silicon oxide film 3 has been subjected to the first etching process. In the first etching process, the silicon oxide film 3 is dry-etched using a plasma etching apparatus using the resist pattern 11 as a mask. Here, in this embodiment, unlike the manufacturing method of the conventional solid-state imaging device shown in FIG. 5, the silicon oxide film 3 is etched back so that a part of the thickness remains in the film thickness direction. As a result, a silicon oxide film 3a in which the thickness of the portion other than the portion covered with the resist pattern 11 is thin is obtained.

  In the first etching process, it is preferable to etch the silicon oxide film 3 in a range of 10 to 90% with respect to the film thickness direction. For example, when dry etching is performed under the same conditions using a plasma etching apparatus similar to the conventional one, the silicon oxide film 3 can be etched back to 50% in the film thickness direction by setting the etch back time to half that of the conventional one. .

  In addition, since the plasma etching process is an anisotropic etching condition, the etching proceeds from the surface of the silicon oxide film 3 toward the substrate. Therefore, the thickness of the silicon oxide film 3 not covered with the resist pattern 11 can be reduced without substantially changing the thickness of the silicon oxide film 3 formed along the side wall of the gate electrode 4.

  FIG. 1D shows a state where the resist pattern 11 is removed. The resist pattern 11 is removed by an ashing process using a plasma ashing apparatus. The ashing process according to the present embodiment means that the resist pattern 11 is completely removed. If possible in processing, for example, to clean the surface after ashing the resist pattern 11. Wet cleaning may be added.

  FIG. 1E shows a state in which the second etching process is performed on the silicon oxide film 3. In the second etching process, the entire surface of the silicon oxide film 3 is etched until the portion where the film thickness is reduced by the first etching process is completely removed. As a result, a silicon oxide film 3b in which the film thickness of the portion covered with the resist pattern 11 is thin is obtained. Further, side wall spacers 7 are formed on the side walls of the gate electrode 4, and the drain regions 6 are exposed on the surface of the substrate.

  The second etching process may be terminated by a conventionally known end point detection. For example, when dry etching is performed under the same conditions using a plasma etching apparatus similar to the conventional one, the etching back time that is half of the conventional one is reduced. This can be achieved by using it as a measure of termination.

  FIG. 1F shows a state in which an LDD structure MOS transistor is formed on the main surface of the substrate. First, using the sidewall spacer 7 as a mask, an impurity having the same conductivity type and high concentration as the above-described impurity is implanted toward the drain region 6. As a result, a high concentration impurity region 6a is formed in the drain region 6, and a MOS transistor having an LDD structure is formed.

  The semiconductor substrate 1 configured as described above can be flattened by covering the surface with an interlayer insulating film. FIG. 2A shows a state in which the surface of the semiconductor substrate 1 on which the LDD structure MOS transistor is formed is covered with an interlayer insulating film 12. First, a BPSG film is formed on the entire surface of the substrate. Then, the BPSG film is annealed to form the interlayer insulating film 12. The unevenness of the surface of the interlayer insulating film 12 is gentler than that of the conventional example shown in FIG.

  FIG. 2B shows a state in which the interlayer insulating film 12 has been subjected to a surface flattening process such as a CMP process. The surface of the interlayer insulating film 12 is planarized by polishing using a CMP apparatus. The surface level difference H1 of the substrate is smaller than the surface level difference H2 of the conventional substrate shown in FIG. This is because the thickness d2 of the silicon oxide film 3a on the gate electrode 4 is made larger than that of the conventional example described above by etching the silicon oxide film 3 into the first etching process and the second etching process. This is because the thickness is reduced and the step between the silicon oxide film 3a and the substrate surface can be reduced.

  The thickness d2 of the silicon oxide film 3b above the gate electrode 4 is thinner than the thickness d3 of the conventional silicon oxide film 23a, but the thickness d1 of the sidewall spacer 7 is the thickness of the conventional sidewall spacer 27. Since it is not different from d1, a desired LDD can be realized.

  In the solid-state imaging device according to the present embodiment obtained as described above, the rise of the interlayer insulating film 12 on the gate electrode 4 is reduced, so that the surface step of the entire substrate, that is, the global step is also the conventional global step. Has been reduced.

  Although the silicon oxide film 3 has been subjected to the first and second etching processes, the upper portion of the drain region 6 that is susceptible to etching damage is covered with the sidewall spacer 7, so that the drain region 6 Does not cause etching damage.

  Here, the relationship between the etching process for the silicon oxide film and the global level difference will be described. In the following description, the time required for the first etching process is referred to as “first dry etch time”, and the time required for the second etching process is referred to as “second dry etch time”. FIG. 3 shows the relationship between the ratio of the first dry etch time to the total dry etch time including the first and second dry etch times (hereinafter referred to as the first dry etch time ratio) and the global level difference. It is a graph.

  In FIG. 3, the global level difference is greatest when the first dry etch time ratio is 100%, that is, when the second dry etch time is zero. When the first dry etch time ratio is 100%, it corresponds to the conventional manufacturing method shown in FIG. The global level difference decreases as the first dry etch time ratio decreases from 100%, and is the minimum when the first dry etch time ratio is 0%. When the first dry etching time ratio is 0%, the silicon oxide film 3 including the PD region and the FD region is entirely etched back after the resist pattern 11 is removed. Therefore, the silicon oxide film 3 on the gate electrode 4 is completely removed, and the global step is minimized.

  Next, the relationship between the etching process for the silicon oxide film and the manufacturing yield of the solid-state imaging device will be described. FIG. 4 is a graph showing the relationship between the first dry etch time ratio and the yield. Here, the yield evaluation of the solid-state imaging device was performed based on pattern formation defects due to unevenness on the surface of the interlayer insulating film, assuming that a resist is applied to the surface of the interlayer insulating film and a wiring structure is formed by lithography. .

  Specifically, the surface of the substrate covered with the interlayer insulating film 12 was subjected to CMP treatment, and a wiring pattern (not shown) for forming contact holes was formed on the surface of the interlayer insulating film 12. And the yield was calculated | required based on the quality of the obtained pattern formation. The wiring pattern was patterned as follows because pattern formation defects due to unevenness appeared sensitively, and it was easy to confirm defective products. That is, the contact hole diameter to be formed was patterned by aiming at a lower limit of specification of 10% (0.18 μm) with respect to the design value of 0.20 μm (exposure amount: 38 mJ).

  In FIG. 4, when the first dry etch time ratio is 100%, the conventional yield is shown. The yield is the best when the first dry etch time ratio is 50%, and the yield is improved over the conventional range in the range of about 40% to less than 100%. This is because the flatness of the substrate surface is improved by reducing the global level difference as shown in FIG. 3, and even if the contact hole diameter is at the lower limit of the standard of the management pattern, It is considered that the lithography patterning accuracy in the process is improved.

  On the other hand, when the first dry etch time ratio is 0%, the yield deteriorates even though the flatness of the substrate surface is good. This is because, as described above, since the silicon oxide film 3 including the PD region and the FD region is entirely etched, the PD region and the FD region are damaged by the ion irradiation at the time of etch back, and the yield is lowered. It is considered a thing. That is, if the first dry etch time ratio is too small, the global level difference can be reduced, but the manufacturing yield decreases. If the first dry etch time ratio is too high, a sufficient global level level reduction effect cannot be obtained. Therefore, it is desirable that the first dry etching time ratio is in a range of 50% ± 10% of the time for completely etching back the silicon oxide film 23.

  From the results shown in FIG. 3 and FIG. 4, considering the relationship between the first dry etch time ratio and the global step and yield, if the first dry etch time ratio is in the range of 10% to 90%, the global step It can be seen that the yield can be improved.

  In the above-described embodiment, the LOCOS method is used for the isolation oxide film having the structure of the solid-state imaging device. However, the present invention is not limited to this, and an isolation oxide film using the STI (Shallow Trench Isolation) method may be used.

  Further, the first etching, ashing, and second etching may be performed by different apparatuses, and if an etching apparatus with a reaction chamber for resist ashing is used, continuous processing in-line may be performed. . Further, the first etching, ashing, and second etching processes may be performed continuously in one etching chamber.

  Moreover, in the said embodiment, although the example which formed the sidewall spacer 7 in the drain region 6 side of the gate electrode 4 was demonstrated, the sidewall spacer 7 may be formed in the source region 5 side, The formation location is not particularly limited. That is, the LDD structure of the MOS transistor may be formed on the source region side of the gate electrode, or may be formed on both sides of the gate electrode.

  In the above embodiment, an example in which the thickness of the oxide film on the gate electrode is reduced in the transfer MOS transistor in the pixel has been described. However, the manufacturing method of the present invention is also applied to the MOS transistor included in the peripheral circuit. By doing so, the global level difference can be further reduced. Thereby, a fine wiring pattern in the peripheral circuit portion can be formed.

  Furthermore, although the solid-state imaging device according to the above embodiment has been described by taking a MOS solid-state imaging device as an example, it may be applied to a CCD or the like.

  The solid-state imaging device according to the present invention can reduce the global level difference and can improve the yield of the solid-state imaging device, and thus can be suitably used for a MOS type solid-state imaging device.

The figure explaining the manufacturing process of the solid-state imaging device concerning the embodiment of the present invention. The figure explaining the manufacturing process of the solid-state imaging device concerning the embodiment of the present invention. Graph showing the relationship between the etching time of silicon oxide film and the global level difference Graph showing the relationship between etching time of silicon oxide film and yield of solid-state imaging device The figure explaining the manufacturing process of the conventional solid-state imaging device The figure explaining the manufacturing process of the conventional solid-state imaging device

Explanation of symbols

1, 21 Semiconductor substrate 2a, 2b, 22a, 22b Isolation oxide film 3, 23 Silicon oxide film 3a, 3b, 23a Silicon oxide film 7, 27 Side wall spacer 4, 24 Gate electrode 5, 25 Source region 6, 26 Drain region 6a, 26a High-concentration impurity regions 11, 31 Resist patterns 12, 32 Interlayer insulating film

Claims (3)

A method of manufacturing a solid-state imaging device in which the surface of a substrate is covered with an interlayer insulating film and the surface is flattened,
Forming a gate electrode on the main surface of the semiconductor substrate;
Forming first, second, and third diffusion layers by implanting impurities into the main surface of the semiconductor substrate;
Forming a first insulating film covering the surface of the semiconductor substrate;
Forming a mask layer pattern covering at least the first diffusion layer among the first, second and third diffusion layers;
Using the mask layer pattern as a mask, a first etching step of etching the first insulating film so that a part of the thickness remains in the film thickness direction;
Removing the mask layer pattern;
The first insulating film covered with the mask layer pattern is etched by etching the entire surface of the first insulating film until the first insulating film remaining by the etching process is completely removed. And a second etching step of forming a sidewall spacer on the side wall of the gate electrode,
Covering the entire surface of the semiconductor substrate with a second insulating film;
And a step of planarizing the surface of the second insulating film. The first diffusion layer is a photodiode;
The method of manufacturing a solid-state imaging device according to claim 1, wherein the second diffusion layer is a floating diffusion. 2. The method of manufacturing a solid-state imaging device according to claim 1, wherein in the first etching step, the first insulating film is etched to 10% to 90% in a film thickness direction.

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