JP2006005954A - Gray code counter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gray code counter capable of skip count and always having two bit transitions at the time of skip count.
SOLUTION: A 5-bit gray code counter 2 that counts one by one, and gray code data (Q0p to Q4p) output from the gray code counter 2 is incremented by a value obtained by subtracting 1 from a power of 2 to correspond to the count. By providing the output value converter 3 for converting to the gray code (Q0 to Q4) corresponding to the decimal count, the gray code counter can always make the number of bit transitions when jumping and counting to be two. .
[Selection] Figure 1

Description

  The present invention relates to a gray code counter. In particular, the present invention relates to a gray code counter capable of a jump count operation.

  In some cases, a decoder type scanning circuit is used in a solid-state imaging device. The decoder type scanning circuit includes a counter, and scans an address that matches a value output from the counter. Imaging can be obtained by causing the counter to perform a desired counting operation.

  Conventionally, a binary counter is used as this counter. However, in the binary counter, there are cases where a plurality of bit transitions occur when one decimal count transitions. For example, in a 5-bit binary counter, when the decimal count transitions from 0 to 1, the binary code changes from (00000) to (00001) as shown in FIG. However, when the decimal count changes from 15 to 16, the binary code changes from (01111) to (10000) as shown in FIG. 2, so the number of bit transitions is 5. As the number of bit transitions increases, a power supply current flows in a system provided with a counter, and electrical noise is generated. At that time, interference occurs between signals in the system, which may cause the system to malfunction.

  Gray code counters have been used to suppress the occurrence of this electrical noise. A typical circuit configuration of the 5-bit gray code counter is shown in FIG.

  The Q output terminal of the flip-flop FF6 is connected to the C input terminal of the flip-flop FF1 via the buffer BUF1. The XQ output terminal of the flip-flop FF6 is connected to the first input terminals of the NAND circuits NA1 to NA4.

  The second input terminal of the NAND circuit NA1 is connected to the Q output terminal of the flip-flop FF1. The output terminal of the NAND circuit NA1 is connected to the C input terminal of the flip-flop FF2 via the inverter circuit INV1.

  The second input terminal of the NAND circuit NA2 is connected to the XQ output terminal of the flip-flop FF1, and the third input terminal of the NAND circuit NA2 is connected to the Q output terminal of the flip-flop FF2. The output terminal of the NAND circuit NA2 is connected to the C input terminal of the flip-flop FF3 via the inverter circuit INV2.

  The second input terminal of the NAND circuit NA3 is connected to the XQ output terminal of the flip-flop FF1, the third input terminal of the NAND circuit NA3 is connected to the XQ output terminal of the flip-flop FF2, and the fourth input terminal of the NAND circuit NA3. Is connected to the Q output terminal of the flip-flop FF3. The output terminal of the NAND circuit NA3 is connected to the C input terminal of the flip-flop FF4 via the inverter circuit INV3.

  The second input terminal of the NAND circuit NA4 is connected to the XQ output terminal of the flip-flop FF1, the third input terminal of the NAND circuit NA4 is connected to the XQ output terminal of the flip-flop FF2, and the fourth input terminal of the NAND circuit NA4. Is connected to the XQ output terminal of the flip-flop FF3, and the fifth input terminal of the NAND circuit NA4 is connected to the Q output terminal of the flip-flop FF4. The output terminal of the NAND circuit NA4 is connected to the C input terminal of the flip-flop FF5 via the inverter circuit INV4.

  Furthermore, in each of the flip-flops FF1 to FF6, the XQ output terminal and the D input terminal are connected. Thereby, in each of the flip-flops FF1 to FF6, the output signal output from the Q output terminal is inverted every time the clock signal input to the C input terminal rises.

  The clock generation circuit 21 including the buffer BUF1, NAND circuits NA1 to NA4, and inverter circuits INV1 to INV4 functions as a circuit that generates a clock that determines the inversion timing of each output of the gray code counter 2.

  Next, the operation of the gray code counter 2 will be described with reference to FIGS. Note that the set signals SETQ0 to SETQ4 and SETNCK inputted to the XS terminals of the flip-flops FF1 to FF6 are all always set to 1. The reset signals RESETQ0 to RESETQ4 and RESETNCK input to the XR terminals of the flip-flops FF1 to FF6 are initialized to 0 and then set to 1.

  The flip-flop FF6 receives the reference clock signal CK, generates a divide-by-2 clock signal NCK that is a divide-by-2 of the reference clock signal CK, and supplies the divided clock signal NCK and the divide-by-two clock signal NCK to the clock generation circuit 21 in the next stage. The inverted signal NCKX is output.

  The clock generation circuit 21 generates a clock signal Q0CKN that is the same as the divided-by-2 clock signal NCK. Since the flip-flop FF1 receives the clock signal Q0CKN from the clock generation circuit 21, the flip-flop FF1 outputs an output signal Q0p that is inverted every time the divided clock signal NCK rises and its inverted signal Q0X.

  The clock generation circuit 21 also generates a clock signal Q1CKN that rises when the output signal Q0p is 1 and the divided-by-2 clock signal NCK falls. Since the flip-flop FF2 receives the clock signal Q1CKN from the clock generation circuit 21, the flip-flop FF2 outputs an output signal Q1p that is inverted every time the clock signal Q1CKN rises and an inverted signal Q1X.

  The clock generation circuit 21 also generates a clock signal Q2CKN that rises when the output signal Q0p is 0, the output signal Q1p is 1, and the divided-by-2 clock signal NCK falls. Since the flip-flop FF3 receives the clock signal Q2CKN from the clock generation circuit 21, the flip-flop FF3 outputs an output signal Q2p that is inverted every time the clock signal Q2CKN rises and an inverted signal Q2X.

  The clock generation circuit 21 also generates a clock signal Q3CKN that rises when the output signal Q0p is 0, the output signal Q1p is 0, the output signal Q2p is 1, and the divided-by-2 clock signal NCK falls. Since the flip-flop FF4 receives the clock signal Q3CKN from the clock generation circuit 21, the flip-flop FF4 outputs an output signal Q3p that is inverted every time the clock signal Q3CKN rises and an inverted signal Q3X.

  The clock generation circuit 21 also generates a clock signal Q4CKN that rises when the output signal Q0p is 0, the output signal Q1p is 0, the output signal Q2p is 0, the output signal Q3p is 1, and the divided-by-2 clock signal NCK falls. Since the flip-flop FF5 receives the clock signal Q4CKN from the clock generation circuit 21, the flip-flop FF5 outputs an output signal Q4p that is inverted every time the clock signal Q4CKN rises and an inverted signal Q4X.

  Output signal Q0p is output at the 0th bit, that is, the least significant bit, output signal Q1p is output at the first bit, output signal Q2p is output at the second bit, output signal Q3p is output at the third bit, and output signal Q4p is 4 bits Assuming that the output of the first bit is the most significant bit, the gray code counter 2 outputs the gray code shown in FIG. 2 in accordance with the decimal count of the clock signal CK.

  In the gray code, a continuous decimal count has a different code by 1 bit, and the other bits have the same code. That is, the number of bit transitions is always 1 in consecutive decimal counts. As a result, the gray code counter can reduce the current due to bit transitions compared to the binary code, and can suppress the generation of electrical noise.

  On the other hand, in a solid-state imaging device, it may be necessary for the counter to perform interlaced counting, that is, for the decoder-type scanning circuit to perform interlaced scanning.

  For example, the solid-state imaging device can be provided with an electronic zoom function by switching between interlaced scanning and normal scanning. That is, interlaced scanning is performed during normal shooting (without electronic zoom), and normal scanning is performed during electronic zoom. Here, a solid-state imaging device having an imaging area of 200 addresses (pixels) in the horizontal direction and 200 addresses (pixels) in the vertical direction, and 100 display areas in the horizontal direction and 100 pixels in the vertical direction. A case of using a display device having the above will be described.

  During normal shooting (without electronic zoom), the solid-state imaging device scans addresses by jumping one by one with 0, 2, 4,..., 196, 198 in both the horizontal and vertical directions, and 10,000 (100 × 100) data. Is acquired and displayed on the display device. At the time of electronic zoom, the solid-state imaging device scans addresses in increments of 0, 1, 2,..., 98, 99 in both the horizontal and vertical directions, acquires 10000 (100 × 100) data, and displays the display device. To display. The image displayed in the case of this electronic zoom is an image obtained by zooming the upper left portion of the image at the time of normal shooting by four times.

In some cases, a solid-state imaging device captures both still images and moving images. In the case of moving images, it may be difficult to scan all addresses due to frequency limitations. However, in the case of a still image, the resolution is better when all addresses are scanned. For this reason, it is preferable to scan all addresses in the case of a still image and to skip over in the case of a moving image.
JP-A-1-296712

  However, the gray code is not easy to calculate (for example, addition) as compared with the binary code, and the code itself is complicated, so that it is difficult to logically design the gray code counter capable of performing the jump count. For this reason, when the above-described jump count is necessary, a binary counter is conventionally used. In addition, even if the jumping count can be performed in the gray code counter, there is a problem that the number of bit transitions greatly increases depending on the skipped value. For example, when counting is performed by skipping 9 by 9, when the transition is made from 0 to 10, the gray code changes from (00000) to (01111) and the number of bit transitions becomes 4, and the number of bit transitions can be reduced. The characteristics of the gray code will be lost.

  Furthermore, in the solid-state imaging device, in order to enable the screen cutting operation, it is necessary for the decoder type scanning circuit to scan from an arbitrary address to an arbitrary address, that is, random access. For example, in a solid-state imaging device having 200 horizontal addresses, if 100 to 149 are scanned, images corresponding to addresses 1 to 99 and 150 to 200 are not scanned, and addresses 100 to 149 are scanned. Only the corresponding image can be cut out. In this case, a counter is required that starts counting from an arbitrary start value and can end counting at an arbitrary end value.

  In view of the above problems, an object of the present invention is to provide a gray code counter that can perform an interlace count and always has two bit transitions during the interlace count. It is another object of the present invention to provide a solid-state imaging device capable of interlaced address scanning and less electrical noise, and a camera system using the same.

  In order to achieve the above object, in the gray code counter according to the present invention, the gray code counter that counts one by one and the gray code data that is output from the gray code counter that counts one by one subtract 1 from the power of 2. Output value conversion means for converting into a gray code corresponding to a decimal count that jumps over each value.

  In addition, the output value conversion means outputs the gray code data output from the gray code counter that counts one by one as it is, or counts one by one so that the count can be switched between one count and the skip count. Selection means is provided for selecting, based on an external signal, whether to convert gray code data output from the gray code counter into a gray code corresponding to a decimal count that jumps and counts by a value obtained by subtracting 1 from a power of 2. You may do it.

  In order to achieve the above object, the solid-state imaging device according to the present invention includes the gray code counter having the above-described configuration. In order to achieve the above object, the camera system according to the present invention includes the solid-state imaging device having the above-described configuration.

  According to the present invention, the gray code counter counts the gray code counter that counts one by one and the gray code data output from the gray code counter that counts one by one by incrementing a value obtained by subtracting 1 from the power of 2. Output value conversion means for converting to a gray code corresponding to a decimal count, so that the value obtained by subtracting 1 from the power of 2 can be counted and the number of bit transitions at that time is always 2 It becomes. Thereby, it is possible to perform the jump count while suppressing the generation of electrical noise.

  According to the present invention, the gray code data output from the gray code counter that counts one by one by the output value conversion means is output as it is, or the gray code data that is output from the gray code counter that counts one by two Since there is a selection means for selecting based on an external signal whether to convert to a gray code corresponding to a decimal count that jumps and counts by a value obtained by subtracting 1 from the power, it counts one by one instead of just the jump count Operations can also be performed. Thereby, the use range of the gray code counter can be expanded.

  In addition, according to the present invention, the solid-state imaging device includes the gray code counter that can perform the interlace count and the number of bit transitions at that time is 2, so that the electronic noise can be suppressed while suppressing the generation of electrical noise. Zoom can be performed. In addition, when the gray code counter has a selection means that can select either an interlace count operation or one count operation, when capturing a moving image, the interlace count operation is selected to scan below the limit frequency. When a still image is captured, the resolution can be improved by selecting one count operation, and the occurrence of electrical noise can be suppressed.

  In addition, according to the present invention, the camera system includes the solid-state imaging device having the gray code counter that can perform the interlace count and the number of bit transitions at that time is 2, so that the electronic zoom can be performed and the optical lens Even if the zoom range of the system is narrowed, the zoom range of the entire camera system can be secured. Thereby, size reduction of a camera system can be achieved.

  An embodiment of the present invention will be described with reference to the drawings. The configuration of the gray code counter according to the first embodiment of the present invention is shown in FIG. The gray code counter of the first embodiment has a 5-bit configuration, and the gray code counter 2 that counts one by one has the same circuit configuration as the gray code counter shown in FIG. The gray code counter 1 of the first embodiment includes a gray code counter 2 and an output value converter 3 that count one by one.

The gray code counter 2 outputs gray code data Q0p to Q4p. The output value converter 3 outputs the gray code data Q0p to Q4p output from the gray code counter 2 as output data Q0 to Q4 as they are when the control signals mode0 and mode1 are counted one by one, and the control signal mode0 When the mode 1 is to skip over 2 ^M −1, the gray code data Q0p to Q4p output from the gray code counter 2 is converted into a gray code corresponding to a decimal count that skips over 2 ^M −1. And output as output data Q0 to Q4.

Here, the relationship between the gray code output data when counting one by one and the gray code output data when counting by skipping 2 ^M −1 is considered. As is apparent from FIG. 2, the gray code output data when counting one by one is the bit change pattern in which the K bit repeats the first 2 ^K 0s, and then 2 ^{K + 1} repeats the same value and then inverts. It is.

When M = 1 in the case of counting by skipping 2 ^M −1, that is, when counting by skipping one by one, the Gray code counter 1 of the first embodiment counts as 0, 2, 4, 6,. Go. FIG. 3 shows a correspondence diagram of decimal numbers and gray codes in the case of jumping one by one and counting. As can be seen from FIG. 3, the 0th bit (least significant bit) of the gray code when counting by skipping one by one is inverted whenever the count value changes, and the upper 4 bits (4 The change pattern of the (α + 1) -th bit belonging to the (bit-1st bit) is the α-th bit belonging to the lower 4 bits (3rd to 0th bit) when the gray code counter 2 counts from 0 to 15 The change pattern is the same (see FIG. 2). However, when M = 1, α is an integer of 0 to 3.

Further, when M = 2 in the case of counting by skipping 2 ^M −1, that is, when counting by skipping by 3, the Gray code counter 1 of the first embodiment counts 0, 4, 8,. Go. FIG. 4 shows a correspondence diagram of decimal numbers and gray codes in the case of counting by skipping three by three. As is apparent from FIG. 4, the 0th bit (least significant bit) of the gray code in the case of counting by skipping by 3 always takes a value of 0. The first bit is inverted every time it is counted with an initial value of 0. The change pattern of the (α + 2) bit of the upper 3 bits (4th to 2nd bits) due to the change of the count value is the lower 3 bits (2nd bit) when the gray code counter 2 counts from 0 to 7 This is the same as the change pattern of the α-th bit belonging to (˜0-th bit) (see FIG. 2). However, when M = 2, α is an integer of 0-2.

Further, when M = 3 in the case of counting by skipping 2 ^M −1, that is, when counting by skipping by 7, the gray code counter 1 of the first embodiment counts as 0, 8, 16, 24,. I will do it. FIG. 5 shows a correspondence diagram of decimal numbers and gray codes in the case of counting by skipping 7 by 7. As is apparent from FIG. 5, the 0th bit (least significant bit) and the 1st bit of the gray code in the case of counting by skipping by 7 always take a value of 0. The second bit is inverted every time it is counted, with an initial value of 0. The change pattern of the (α + 3) bit belonging to the upper 2 bits (4th to 3rd bits) due to the change of the count value is the lower 2 bits (1 bit) when the gray code counter 2 counts from 0 to 3 This is the same as the change pattern of the α-th bit belonging to the (first to 0th bits) (see FIG. 2). However, when M = 3, α is an integer of 0 to 1.

Of course, this relationship also holds when the number of gray code bits increases. That is, in the N-bit gray code counter, when the gray code output data is counted by skipping 2 ^M -1 values, the (α + M) bit belonging to the upper (NM) bits is counted one by one. It has the same sign as the α-th bit belonging to the lower (NM) bits of the gray code output data, and the (M−1) -th bit is inverted every time it is counted, with the initial value being 0, and (N−2) bits It always keeps 0 after the eye.

Accordingly, when counting by skipping by 2 ^M −1, the output value converter 3 uses the α-bit bit data belonging to the lower (NM) bits of the gray code counter output as the (α + M) -bit bit data. The upper (N−M) bits are output and inverted every time the (M−1) th bit data of the remaining lower M bits is counted, and if there are more than the (M−2) th bit, M-2) It is only necessary to operate so that bit data below the bit number is always 0, and a specific configuration when N = 5 is the circuit configuration shown in FIG.

  The output value converter 3 shown in FIG. 6 will be described. The first input terminal of the selector S1, the second input terminal of the selector S2, the third input terminal of the selector S3, and the fourth input terminal of the selector S4 are connected in common, and the 0th bit data Q4p of the gray code counter 2 is input. The The first input terminal of the selector S2, the second input terminal of the selector S3, the third input terminal of the selector S4, and the fourth input terminal of the selector S5 are connected in common, and the first bit data Q1p of the gray code counter 2 is Entered. The first input terminal of the selector S3, the second input terminal of the selector S4, and the third input terminal of the selector S5 are connected in common, and the second bit data Q2p of the gray code counter 2 is input. The first input terminal of the selector S4 and the second input terminal of the selector S5 are connected in common, and the third bit data Q3p of the gray code counter 2 is input. The fourth bit data Q4p of the gray code counter 2 is input to the first input terminal of the selector S4.

  The second input terminal of the selector S1, the third input terminal of the selector S2, and the fourth input terminal of the selector S3 are connected in common and connected to the Q output terminal of the flip-flop FF7. The third and fourth input terminals of the selector S1 and the fourth input terminal of the selector S2 are grounded.

  Further, the first control signal mode0 is input to each of the first control terminals of the selectors S1 to S4, and the second control signal mode1 is input to each of the second control terminals of the selectors S1 to S4. The selectors S1 to S4 output a signal input to the first input terminal when a low level signal is input to the first control terminal and the second control terminal, and input a high level signal to the first control terminal. When a low level signal is input to the second control terminal, a signal input to the second input terminal is output, a low level signal is input to the first control terminal, and a high level signal is input to the second control terminal. When a signal is input, the signal input to the third input terminal is output, and when a high level signal is input to the first control terminal and the second control terminal, the signal input to the fourth input terminal Is output.

  Therefore, the bit data output from the output value converter 3 is as shown in FIG. When the first control signal mode0 and the second control signal mode1 are both 0, the gray code counter 1 of the first embodiment counts one by one. When the first control signal mode0 is 1 and the second control signal mode1 is 0, The gray code counter 1 of the first embodiment skips one by one, and when the first control signal mode0 is 0 and the second control signal mode1 is 1, the gray code counter 1 of the first embodiment skips by three and counts. However, when both the first control signal mode0 and the second control signal mode1 are 1, the gray code counter 1 of the first embodiment counts by skipping 7 by 7.

As a result, it is possible to count over 2 ^M −1 (M = 1 to 3), and the number of bit transitions can always be 2. It is also possible to switch between the operation of counting by 1 and the operation of jumping and counting by 2 ^M −1.

  Next, a gray code counter according to a second embodiment of the present invention will be described. The gray code counter of the first embodiment described above can only start counting from zero. However, in the solid-state imaging device, in order to enable the operation of cutting the screen, it is necessary for the decoder type scanning circuit to scan from an arbitrary address to an arbitrary address, that is, random access. For this reason, the counter which can start a count from arbitrary count numbers and can complete a count by arbitrary count numbers is needed.

  Therefore, the gray code counter of the second embodiment is configured as shown in FIG. 8 so that counting can be started from an arbitrary count number and can be ended at an arbitrary count number. Note that the gray code counter of the second embodiment also has a 5-bit configuration like the gray code counter of the first embodiment. Further, in FIG. 8, the same parts as those in FIG.

  Gray code data START0 to START4 of the value to start counting are input to the input value converter 4 and the initial setting means 7. The input value converter 4 converts the gray code data START0 to START4 of the value to start counting according to the control signals mode0 and mode1 and outputs the converted data to the count start data setting means 5. The count start data setting means 5 controls the initial state of the gray code counter 2 based on the bit data sent from the input value converter 4.

  On the other hand, the initial setting means 7 controls the initial state of the output value converter 3 'in accordance with the gray code data START0 to START4 of the value to start counting and the control signals mode0 and mode1. The output value conversion value 3 'converts the gray code counter output data Q0p to Q4p and outputs gray code data Q0 to Q4.

  Further, the count end data setting means 6 controls the clock signal to be sent to the gray code counter 2 in accordance with the gray code data STOP0 to STOP4 of the value to end counting and the output data Q0 to Q4 of the output value converter 3 ′. .

  Next, specific aspects of each component of the gray code counter of the second embodiment shown in FIG. 8 will be described. First, the output value converter 3 'and the initial setting means 7 will be described.

Here, the relationship between the gray code output data when counting one by one and the gray code output data when counting by skipping 2 ^M −1 when counting is started from an arbitrary number will be considered.

When M = 1 when counting by skipping 2 ^M −1, that is, when counting by skipping one by one, the count starts from 0 and jumps one by one, and the count starts from 1. Think of it in two ways: skipping one by one and counting. FIG. 17 (a) shows the correspondence between decimal numbers and gray codes when counting starts from 0, and FIG. 17 (b) shows the correspondence between decimal numbers and gray codes when counting starts from 1. Show.

  As can be seen from FIG. 17A, when the decimal count of the value to start counting is an even number, the count operation is the same as the case of starting counting from 0 except that the initial value to start counting is different. . Further, as is clear from FIG. 17B, when the decimal count of the value to start counting is an odd number, the count operation is the same as when starting counting from 1, except that the initial value for starting counting is different. It is.

  Further, from FIGS. 17 (a) and 17 (b), regardless of whether the value to start counting is an even number or an odd number, the gray code output data when counting one by one and when counting by jumping one by one It can be seen that there is a certain relationship with the gray code output data. That is, when counting by skipping one by one, the 0th bit (least significant bit) of the gray code starts counting with the value of the 0th bit of the value to start counting as an initial value, and thereafter the count value changes. It is inverted. Also, the change pattern due to the change of the count value at the (α + 1) -th bit belonging to the upper 4 bits (4th to 1st bits) of the gray code when jumping one by one is counted when counting one by one. This is the same as the change pattern due to the change of the count value at the α-th bit belonging to the lower 4 bits (3rd to 0th bits) of the gray code (see FIG. 2). However, when M = 1, α is an integer of 0 to 3.

In addition, when M = 2 in the case of counting by skipping by 2 ^M −1, that is, in the case of counting by skipping by three, starting from 0 and counting by skipping by 3 and counting from 1 It is divided into four cases: starting from 3 and counting by skipping, counting from 2 and counting by skipping by 3 and starting from 3 and counting by skipping by 3 . FIG. 18 (a) shows the correspondence between decimal numbers and gray codes when counting starts from 0, and FIG. 18 (b) shows the correspondence between decimal numbers and gray codes when counting starts from 1. FIG. 18C shows the correspondence between the decimal number and the gray code when counting is started from 2, and FIG. 18D shows the correspondence between the decimal number and the gray code when counting is started from 3. Show.

  As is clear from FIG. 18A, when the decimal count of the value to start counting is a multiple of 4, the count operation is different from the case of starting counting from 0 except that the initial value to start counting is different. The same. Further, as apparent from FIG. 18B, when the decimal count of the value to start counting is a value obtained by adding 1 to a multiple of 4, the case of starting counting from 1 is the initial time to start counting. The counting operation is the same except that the values are different. Further, as is clear from FIG. 18C, when the decimal count of the value to start counting is a value obtained by adding 2 to a multiple of 4, the case of starting counting from 2 is the initial time to start counting. The counting operation is the same except that the values are different. As is clear from FIG. 18 (d), when the decimal count of the value to start counting is a value obtained by adding 3 to a multiple of 4, the case of starting counting from 3 is the initial time to start counting. The counting operation is the same except that the values are different.

  Further, from FIGS. 18A to 18D, regardless of the value at which the count is started, between the gray code output data when counting one by one and the gray code output data when counting while skipping three by three. It can be seen that there is a certain relationship. In other words, the 0th bit (least significant bit) of the gray code when counting is skipped by 3 always remains the value of the 0th bit of the value at which counting is started. In addition, the first bit of the gray code when counting by skipping by 3 starts counting with the value of the first bit of the value to start counting as an initial value, and then is inverted every time the count value changes. . In addition, the change pattern due to the change in the count value at the (α + 2) bit belonging to the upper 3 bits (4th bit to 2nd bit) of the gray code when skipping by 3 is used when counting one by one. This is the same as the change pattern by changing the count value at the α-th bit belonging to the lower 3 bits (2nd to 0th bits) of the gray code (see FIG. 2). However, when M = 2, α is an integer of 0-2.

Further, when M = 3 when jumping and counting by 2 ^M −1, that is, when counting by jumping by 7 and counting, it can be considered in the same way as when M = 1 and 2 described above by dividing into 8 ways. Since it can, explanation is omitted.

Such a relationship can also be said when the number of bits increases. That is, in the N-bit gray code, the change pattern due to the change in the count value at the (α + M) -th bit belonging to the upper (NM) bits of the gray code when the count is skipped by 2 ^M −1 is 1 This is the same as the change pattern by changing the count value at the α-th bit belonging to the lower (NM) bits of the gray code when counting one by one. In addition, the (M−1) -th bit of the gray code when counting by skipping by 2 ^M −1 starts counting with the value of the (M−1) -th bit of the value to start counting as an initial value, and thereafter Each time the count value changes, it is inverted. Further, if there is a (M-2) th bit or less, the β bit of the gray code when counting by skipping 2 ^M −1 is always the value of the β bit of the value at which counting is started.

  Accordingly, the output value converter 3 ′ uses the α-th bit data belonging to the lower (N−M) bits of the gray code data output from the gray code counter 2 as the upper (N + M) bit data (N + M). -M) output bits, and start counting with the (M-1) -th bit value of the value to start counting the bit data of the (M-1) -th bit among the remaining lower M bits as the initial value, Thereafter, it is inverted every time the count value changes, and if there is a (M-2) th bit or less, β bits belonging to the (M-2) th bit or less of the gray code data output from the gray code counter 2 at the start of counting. It suffices to operate so that the bit data of the βth bit is output as the bit data of the βth bit and the (M-2) th bit or less. As a specific mode when N = 5, FIG. Circuitry shown and the like.

  15, the same parts as those in FIG. 6 are denoted by the same reference numerals, and only the parts different from the circuit connection in FIG. 6 will be described. The third input terminal and the fourth input terminal of the selector S1 are commonly connected, and the 0th bit data START0 having a value for starting the count is input. Further, the first bit data START1 of the value to start counting is input to the fourth input terminal of the selector S2.

  The inversion signal tog output from the flip-flop FF7 has different initial values depending on the type of count operation and the value at which counting starts. FIG. 19 shows a correspondence diagram of output values of the gray code counter 1 ′ to be output by the output value converter 3 ′. When counting one by one, the output bit data Q4p to Q4p of the gray code 1 'may be output as it is. Therefore, the initial value of the inversion signal tog may be any value.

  Then, when counting is performed by skipping one by one, the value of the 0th bit START0 of the value to start counting may be set as the initial value of the inverted signal tog. In addition, when counting is performed by skipping three by three, the value of the first bit START1 of the value to start counting may be set as the initial value of the inverted signal tog. In addition, when counting is performed by skipping by seven, the value of the second bit START2 of the value to start counting may be set as the initial value of the inverted signal tog.

  FIG. 16 shows a specific mode of the initial setting means 7 for outputting the set signal SETtog and the reset signal RESETtog to the flip-flop FF7 in order to set the initial value of the inverted signal tog as described above.

  The output terminal of the selector S11 is input to the first input terminal of the NAND circuit NA17 and the inverter circuit INV11, and the output signal of the inverter circuit INV11 is input to the first input terminal of the NAND circuit NA18. The start signal START is input to the second input terminals of the NAND circuits NA17 and NA18. A set signal SETtog is output from the NAND circuit NA17, and a reset signal RESETtog is output from the NAND circuit NA18.

  When the initial setting means 7 has the configuration shown in FIG. 16, when the flip-flop FF7 is to be operated normally, the start signal START is set to 0, and the set signal SETtog and the reset signal RESETtog are set to 1.

  At the start of counting, the start signal START is set to 1. In this case, when the output signal of the selector S11 is 1, the set signal SETtog becomes 0 and the reset signal RESETtog becomes 1. When the output signal of the selector S11 is 0, the set signal SETtog is 1 and the reset signal RESETtog is 0. Thereby, the sign of the signal tog output from the Q terminal of the flip-flop FF7 and the output signal of the selector signal S11 can be matched.

  Further, the first control signal mode0 is input to the first control terminal of the selector S11, and the second control signal mode1 is input to the second control terminal of the selector S11. The selector S11 outputs a signal input to the first input terminal when a low level signal is input to the first control terminal and the second control terminal, and a high level signal is input to the first control terminal. When a low level signal is input to the second control terminal, a signal input to the second input terminal is output, a low level signal is input to the first control terminal, and a high level signal is input to the second control terminal. When input, the signal input to the third input terminal is output, and when a high level signal is input to the first control terminal and the second control terminal, the signal input to the fourth input terminal is output. To do. The first input terminal of the selector S11 is grounded, bit data of the 0th bit START0 of the value to start counting is input to the second input terminal, and 1 bit of the value to start counting is input to the third input terminal. The bit data of the first START1 is input, and the bit data of the second bit START2 of the value to start counting is input to the fourth input terminal.

  By setting the initial setting means 7 in such a configuration, when counting is performed by skipping one by one, the initial value of the inverted signal tog can be made the same sign as the bit data of the 0th bit START0 of the value to start counting. The initial value of the inverted signal tog can be set to the same sign as the bit data of the first bit START1 of the value to start counting when skipping by 3 and counting is inverted when counting is skipped by 7 The initial value of the signal tog can have the same sign as the bit data of the second bit START2 of the value to start counting.

Next, the input value converter 4 will be described. As described above, when the count is skipped by 2 ^M −1, the gray value when the output value converter 3 ′ jumps and counts the gray code output data counted by 1 by the gray code counter 2 by 2 ^M −1. Convert to code output data. For this reason, when skipping and counting by 2 ^M −1, the input value converter 4 converts the bit data (START4 to START0) of the value to start counting into gray code output data when counting one by one and gray It is necessary to output to the code counter 2 side.

  Therefore, the input value converter 4 uses the (α + M) bit data belonging to the upper (NM) bits of the value to start counting as the α bit data belonging to the lower (NM) bits of the output data. The upper M bits may be always set to 0, and a specific configuration when N = 5 includes the circuit configuration shown in FIG.

  The input value converter 4 shown in FIG. 9 will be described. The 0th bit data START0 of the value to start counting is input to the first input terminal of the selector S6. The second input terminal of the selector S6 and the first input terminal of the selector S7 are connected in common, and the first bit data START1 of the value for starting the count is input. The third input terminal of the selector S6, the second input terminal of the selector S7, and the first input terminal of the selector S8 are connected in common, and the second bit data START2 having a value for starting counting is input. The fourth input terminal of the selector S6, the third input terminal of the selector S7, the second input terminal of the selector S8, and the first input terminal of the selector S9 are connected in common, and the third bit data START3 of the value to start counting is input. The The fourth input terminal of the selector S7, the third input terminal of the selector S8, the second input terminal of the selector S9, and the first input terminal of the selector S10 are connected in common, and the fourth bit data START4 of the value to start counting is input. Is done. The fourth input terminal of the selector S8, the third and fourth input terminals of the selector S9, and the second to fourth input terminals of the selector S10 are commonly connected and grounded.

  Further, the first control signal mode0 is input to each of the first control terminals of the selectors S6 to S10, and the second control signal mode1 is input to each of the second control terminals of the selectors S6 to S10. The selectors S6 to S10 output a signal input to the first input terminal when a low level signal is input to the first control terminal and the second control terminal, and a high level signal is input to the first control terminal. When a low level signal is input to the second control terminal, the signal input to the second input terminal is output, a low level signal is input to the first control terminal, and a high level signal is input to the second control terminal. When a signal is input, the signal input to the third input terminal is output, and when a high level signal is input to the first control terminal and the second control terminal, the signal input to the fourth input terminal Is output. Therefore, the data output from the input value converter 4 is as shown in FIG.

  Next, the count start data setting unit 5 will be described. A circuit block diagram of one embodiment of the count start data setting means 5 is shown in FIG. The even / odd number judgment circuit 51 outputs 0 when the decimal count is an even number, and outputs 1 when the decimal count is an odd number. When the decimal count is an even number, the number of 1s included in the gray code is an even number, whereas when the decimal count is an odd number, the number of 1s included in the gray code is an odd number. The circuit 51 is preferably a logic circuit as shown in FIG.

  The exclusive OR circuit E1 inputs the bit data AFT_START0 to AFT_START2. Further, the exclusive OR circuit E2 inputs the bit data AFT_START3 to AFT_START4. Then, the exclusive OR circuit E3 inputs the output signals of the exclusive OR circuits E1 and E2, and outputs an even / odd signal odd_even.

  The set / reset control circuit 52 generates a control signal to be output to the XS terminal and the XR terminal of the flip-flop FF6 based on the even / odd signal odd_even output from the even / odd determination circuit 51.

  The set / reset terminal control circuit 52 sets the set signal SETNCK input to the XS terminal to 1 and sets the reset signal RESETNCK input to the XR terminal to 0 when the output signal of the Q terminal of the flip-flop FF6 is set to 0. . When the output signal at the Q terminal of the flip-flop FF6 is to be set to 1, the set signal SETNCK input to the XS terminal is set to 0, and the reset signal RESETNCK input to the XR terminal is set to 1. When the flip-flop FF6 is to be operated normally, the set signal SETNCK input to the XS terminal is set to 1, and the reset signal RESETNCK input to the XR terminal is set to 1.

  FIG. 12 shows an embodiment of the set / reset terminal control circuit 52 that performs such an operation. The even / odd signal odd_even is input to the first input terminal of the NAND circuit NA5 and the inverter circuit INV5, and the output signal of the inverter circuit INV5 is input to the first input terminal of the NAND circuit NA6. A start signal START is input to the second input terminals of the NAND circuits NA5 and NA6. A set signal SETNCK is output from the NAND circuit NA5, and a reset signal RESETNCK is output from the NAND circuit NA6.

  When the set / reset terminal control circuit 52 is configured as shown in FIG. 12R> 2, when the flip-flop FF6 is to be operated normally, the start signal START is set to 0, and the set signal SETNCK and the reset signal RSETNCK are set to 1. .

  At the start of counting, the start signal START is set to 1. In this case, when the even / odd signal odd_even is 1 (when the decimal count corresponding to the bit data AFT_START0 to AFT_START4 is an odd number), the set signal SETNCK becomes 0 and the reset signal RESETNCK becomes 1. When the even / odd signal odd_even is 0 (when the decimal count corresponding to the bit data AFT_START0 to AFT_START4 is an even number), the set signal SETNCK becomes 1 and the reset signal RESETNCK becomes 0. Accordingly, as shown in FIG. 23, when the decimal count corresponding to the bit data AFT_START0 to AFT_START4 is an odd number, the divide-by-2 signal NCK output from the Q terminal by the flip-flop FF6 can be set to 1, and the bit data When the decimal count corresponding to AFT_START0 to AFT_START4 is an even number, the divide-by-2 signal NCK output from the Q terminal by the flip-flop FF6 can be set to zero.

  The set / reset control circuit 53 creates control signals to be output to the XS terminals and XR terminals of the flip-flops FF1 to FF5 based on the bit data AFT_START0 to AFT_START4.

  One embodiment of the set / reset terminal control circuit 53 is shown in FIG. The set / reset terminal control circuit 53 is provided with five circuits having the same configuration as the set / reset terminal control circuit 52. In place of the even / odd signal odd_even, bit data AFT_START0, AFT_START1, AFT_START2, AFT_START3, and AFT_START4 are input to the respective circuits.

  As a result, when the start signal START is set to 1, the gray code counter 2 outputs the bit data AFT_START0, AFT_START1, AFT_START2, AFT_START3, and AFT_START4. When the start signal START is set to 0, the flip-flops FF1 to FF5 operate normally. Therefore, the gray code counter 2 performs a counting operation.

Next, a circuit block diagram of one embodiment of the count end data setting means 6 is shown in FIG. The comparator 61 compares the gray code data STOP0 to STOP4 of the value to end the count with the output signals Q0, Q1, Q2, Q3, and Q4 of the gray code counter 1 ′, and compares the least significant bit and the one bit. When all of the first, second, third, and most significant bits match, a control signal is sent to the clock control circuit 62 to stop the output of the clock signal CK. As a result, the clock signal CK is not supplied to the gray code counter 2, and the gray code counter 1 ′ ends the counting. When the gray code counter 1 'is incremented by 2 ^M −1, it is necessary to set the gray code data STOP0 to STOP4 of the value to end the count according to the value to start counting and the number to be skipped. is there. For example, when the decimal count of the value for starting the count is 0 and the count is skipped by 1, it is necessary to set the count end value to an even number.

  Next, an embodiment of a camera system according to the present invention will be described with reference to FIG. The optical lens system 11 takes in an optical real image (not shown) that is an object to be imaged and forms an image on a solid-state image sensor 15 provided in the solid-state image sensor 12.

  In the solid-state image sensor 15, 1024 photoelectric conversion elements 15a are arranged in a matrix (32 × 32). One vertical direction selection line 15b and one horizontal direction selection line 15c are connected to each photoelectric conversion element 15a. One vertical selection line 15b is selected by the vertical decoder 15d, and one horizontal selection line 15c is selected by the horizontal decoder 15e.

  The vertical decoder 15d selects an address specified by the vertical gray code counter 15f, and the horizontal decoder 15e selects an address specified by the horizontal gray code counter 15g. A signal of the photoelectric conversion element 15a corresponding to the address selected for both the vertical direction selection line 15b and the horizontal direction selection line 15c is output to the output circuit 15h.

  By fixing the count value output by the vertical gray code counter 15f, the vertical address is fixed, and the horizontal gray code counter 15g is counted and scanned in the horizontal direction. When the horizontal scanning is completed, the vertical gray code counter 15g is counted to scan the next horizontal line. By repeating this operation, an imaging operation is realized. The vertical gray code counter 15f and the horizontal gray code counter 15g have the same configuration as the above-described 5-bit gray code counter 1 'according to the second embodiment.

  The vertical direction control circuit 16a outputs gray code data START0 to START4 having a value for starting counting, gray code data STOP0 to STOP4 having a value for ending counting, and control signals mode0 and mode1 to the vertical gray code counter 15f. Thus, the vertical gray code counter 15f is controlled. The horizontal direction control circuit 16b outputs gray code data START0 'to START4' having a value for starting counting, gray code data STOP0 'to STOP4' having a value for ending counting, and control signals mode0 'and mode1' to the horizontal direction gray code. By outputting to the counter 15g, the horizontal gray code counter 15g is controlled.

  The output circuit 15h outputs the signal voltage to the signal processing circuit 13 at the next stage. The signal processing circuit 13 creates a drive signal based on the signal voltage output from the output circuit 15 h and outputs it to the display means 14. The display means has 256 pixels arranged in a matrix (16 × 16).

  With such a configuration, an electronic zoom function can be added to the camera system 10. That is, when normal shooting (without electronic zoom) is performed, the vertical gray code counter 15f starts counting from 0, skips one by one, ends at 30, and the horizontal gray code counter 15g is 0. The counting starts from 1 and skips one by one and finishes counting at 30. Therefore, the solid-state imaging device 12 outputs 256 (16 × 16) data signal processing circuits 13 from the entire area within the imaging area, and the display means 14 displays the entire area within the imaging area of the solid-state imaging apparatus 12. The corresponding image is displayed. On the other hand, when the electronic zoom is performed, the vertical gray code counter 15f starts counting from 0, counts one by one, ends counting at 15, and the horizontal gray code counter 15g starts counting from zero. Count one by one and end counting at fifteen. Therefore, the solid-state imaging device 12 outputs 256 (16 × 16) data signals from the upper left quarter region in the imaging region to the processing circuit 13, and the display unit 14 has the inside of the imaging region of the solid-state imaging device 12. An image corresponding to the upper left quarter region is displayed. That is, when the camera system 10 performs electronic zoom, it is possible to obtain an image in which the upper left portion of the image during normal shooting is zoomed four times.

  Further, with the configuration as shown in FIG. 21, it is possible to add an image cropping function to the camera system 10. That is, when it is desired to cut out the lower left quarter region in the above-described normal shooting (without electronic zoom), the vertical gray code counter 15f starts counting from 16, starts counting one by one, and finishes counting at thirty. The horizontal gray code counter 15g starts counting from 0, skips one by one, and finishes counting at 14. As a result, the solid-state imaging device 12 outputs 64 (8 × 8) data from the lower left area in the imaging area to the signal processing circuit 13, and the display means 14 displays the lower left area in the imaging area of the solid-state imaging apparatus 12. An image corresponding to the ¼ area is displayed.

  Furthermore, the number of pixels of the display unit 14 may be 1024 (32 × 32) instead of 256 (16 × 16), and both still images and moving images may be captured. In such a configuration, when capturing a still image, all addresses may be scanned, and when capturing a moving image, scanning may be skipped. Thereby, when capturing a moving image, scanning can be performed below the limit frequency, and when capturing a still image, the resolution of an image displayed on the display unit 14 can be improved.

These are the block diagrams of the gray code counter of 1st embodiment which concerns on this invention. FIG. 5 is a diagram illustrating a 5-bit binary code and a gray code corresponding to a decimal count. These are figures which show the decimal count and gray code in the case of counting by skipping one by one. These are figures which show a decimal count and a gray code in the case of counting by skipping three by three. These are figures which show a decimal count and a gray code in the case of skipping 7 by 7 and counting. These are figures which show one embodiment of the output value changer with which the gray code counter of FIG. 1 is provided. These are figures which show the relationship between a control signal and the output bit of the output value changer of FIG. These are the block diagrams of the gray code counter of 2nd embodiment which concerns on this invention. These are figures which show one embodiment of the input value changer with which the gray code counter of FIG. 8 is provided. These are the block diagrams of the count start data setting means with which the gray code counter of FIG. 8 is provided. FIG. 11 is a diagram illustrating an embodiment of an even / odd number determination circuit illustrated in FIG. 10. These are figures which show one embodiment of the set / reset terminal control circuit which inputs a signal from the even-odd determination circuit shown in FIG. FIG. 11 is a diagram showing an embodiment of another set / reset terminal control circuit shown in FIG. 10. These are the block diagrams of the count end data setting means with which the gray code counter of FIG. 8 is provided. These are figures which show one embodiment of the output value changer with which the gray code counter of FIG. 8 is provided. These are figures which show one embodiment of the initial setting means with which the gray code counter of FIG. 8 is provided. These are figures which show the decimal count and gray code in the case of counting by skipping one by one. These are figures which show a decimal count and a gray code in the case of counting by skipping three by three. These are figures which show the relationship between a control signal and the output bit of the output value changer of FIG. These are figures which show the relationship between a control signal and the output bit of the input value changer of FIG. These are figures which show the structure of the camera system which concerns on this invention. FIG. 3 is a logic circuit diagram of a gray code counter that counts one by one. FIG. 23 is a time chart showing the operation of the gray code counter of FIG. 22.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Gray code counter of 1st embodiment 1 'Gray code counter of 2nd embodiment 2 Gray code counter which counts 1 at a time 3, 3' Output value converter 4 Input value converter 5 Count start data setting means 6 Count end data Setting means 7 Initial setting means 10 Camera system 12 Solid-state imaging device

Claims (4)

Gray code counter that counts one by one,
Output value conversion means for converting gray code data output from the gray code counter that counts one by one into a gray code corresponding to a decimal count that jumps and counts by a value obtained by subtracting 1 from a power of 2.
A gray code counter comprising: The output value converting means is
The gray code data output from the gray code counter that counts one by one is output as it is,
The gray code data output from the gray code counter that counts one by one is converted into a gray code corresponding to a decimal count that jumps and counts by a value obtained by subtracting 1 from the power of 2.
The gray code counter according to claim 1, further comprising a selection unit that selects a signal based on an external signal.   A solid-state imaging device comprising the gray code counter according to claim 1.   A camera system comprising the solid-state imaging device according to claim 3.

Images