JP2006004464A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller capable of improving the efficiency of data transfer execution for a memory (e.g., SDRAM). <P>SOLUTION: This memory controller 100 is provided with a BANK/ROW address comparison section 7, and a refresh request generation section 8. The BANK/ROW address comparison section 7 is a circuit for comparing a first address in active ROW information with a second address in a memory access request for an SDRAM 300. The refresh request generation section 8 is a circuit for generating a refresh request for the SDRAM 300 according to the comparison results of the BANK/ROW address comparison section 7. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory control device, and can be applied as, for example, a memory control device that controls SDRAM refresh processing.

  When an SDRAM (Synchronous Dynamic Random Access Memory) is used, it is necessary to recharge the memory contents of the memory cell. Here, the recharging is performed by issuing an auto refresh command at regular intervals.

  In the refresh control method of the SDRAM according to the prior art, the auto-refresh command is executed at regular intervals regardless of the state of the SDRAM command issuing unit (for example, see Non-Patent Document 1).

  Here, the SDRAM command issuing unit is a device that accepts a memory access command and a refresh command and issues a command sequence for the SDRAM in the order of acceptance.

  Note that before data is read (or written) from a predetermined storage element of the SDRAM, the SDRAM performs bank precharge / bank activation processing on the corresponding bank and ROW (row). Here, the bank activation process is a process of selecting and activating an access target bank and row address prior to execution of a read / write command. The bank precharge operation is a process for returning the bank and row address activated by the bank activation process to an inactive (idle) state. A plurality of row addresses cannot be activated for the same bank. In order to activate another row address, it is necessary to deactivate the already activated row address.

  Here, it is assumed that data reading (or writing) processing is continuously performed on storage elements belonging to the same bank and the same ROW. In this case, a read (or write) command is continuously issued to the SDRAM without performing bank activation processing.

“Hitachi SuperH RISC engine SH7615 Hardware Manual”, pp315 (7-61) -pp316 (7-62), “7.5.8 Refresh, (1) Auto-refresh”, [online], August 2000, Hitachi, Ltd., Semiconductor Group Electronic Business Sales Division, [Search April 23, 2004], Internet <http: // www. renesas. com / avs / resource / japan / jpn / pdf / mpumcu / j602209_sh7615. pdf>

  By the way, after the refresh process is performed on the SDRAM, it is necessary to perform the bank activation process on a predetermined bank and ROW before issuing a read (or write) command to the SDRAM.

  However, in the technique according to Non-Patent Document 1, it is assumed that a refresh command that is periodically issued is forcibly inserted during continuous access to a memory area that differs in column address by the same bank and the same ROW address. When the refresh process is performed, all banks are in an idle state. Therefore, in the above case, it is necessary to execute the command sequence from the bank activation process.

  This makes it necessary to perform bank activation processing that is essentially unnecessary after the SDRAM refresh processing. That is, not only an execution cycle necessary for the refresh process but also an extra bank activation process cycle is required. Therefore, the effective transfer efficiency of the SDRAM is impaired.

  Therefore, an object of the present invention is to provide a memory control device that can minimize the loss of effective data transfer efficiency even if a refresh process is performed on the memory.

  In order to achieve the above object, the memory control device according to claim 1 of the present invention includes a first address in active information indicating an active state of a memory, a second address in a memory access request, And a refresh request generator for generating a refresh request for the memory according to the comparison result of the address comparator.

  According to a second aspect of the present invention, there is provided a memory control device that detects an idle cycle in which there is no access to the memory, and generates a refresh request for the memory in response to detection of an idle cycle by the idle cycle detection unit. And a refresh request generation unit.

  The memory control device according to claim 15, wherein an address comparison unit that compares a first address in active information indicating an active state of a memory with a second address in a memory access request, and the memory An idle cycle detection unit that detects an idle cycle without access; a refresh request generation unit that generates a refresh request for a memory in response to a comparison result of the address comparison unit and an idle cycle detection of the idle cycle detection unit; Is provided.

  According to a first aspect of the present invention, there is provided a memory control device comprising: an address comparing unit that compares a first address in active information indicating a memory active state with a second address in a memory access request; and the address A refresh request generation unit that generates a refresh request for the memory according to the comparison result of the comparison unit is provided, so the timing of the activation process for the memory is determined, and the memory refresh process is performed aiming at the time Can do. Therefore, it is not necessary to perform a useless activation process associated with the refresh process. Therefore, effective data transfer efficiency with respect to the memory can be improved.

  According to a second aspect of the present invention, there is provided a memory control device that detects an idle cycle in which there is no access to the memory, and generates a refresh request for the memory in response to detection of an idle cycle by the idle cycle detection unit. Since the refresh request generator is provided, the memory refresh process can be performed using the idle cycle. Therefore, effective data transfer efficiency with respect to the memory can be improved.

  The memory control device according to claim 15, wherein an address comparison unit that compares a first address in active information indicating an active state of a memory with a second address in a memory access request, and the memory An idle cycle detection unit that detects an idle cycle without access; a refresh request generation unit that generates a refresh request for a memory in response to a comparison result of the address comparison unit and an idle cycle detection of the idle cycle detection unit; Therefore, it is possible to provide a memory control device in which the memory control devices according to claims 1 and 2 are combined.

  As can be seen from the example shown below, the effective transfer efficiency of SDRAM (Synchronous Dynamic Random Access Memory) varies depending on the timing at which the refresh process is performed. For example, the memory access sequence shown in FIG. 1 will be described as an example.

  Here, “RD” in FIG. 1 means read access. “Bi” indicates the i-th bank address. “Ri” indicates the row address of the i-th row. “Ci” indicates a column address of the i-th column. For example, the first memory access request ID1 is a read access command for the storage elements belonging to the first bank address, the first row address, and the first column address.

  As can be seen from FIG. 1, the memory access request ID1 and the memory access request ID2 are continuous accesses to the same bank and the same ROW address. Memory access request ID2 and memory access request ID3 are continuous accesses to different ROW addresses (the bank addresses are the same).

  In the memory access sequence shown in FIG. 1, when refresh processing is performed between memory access request ID1 and memory access request ID2 (Case A), and refresh processing is performed between memory access request ID2 and memory access request ID3. Each case is considered (Case B).

  FIG. 2 shows a command sequence for the SDRAM of case A. FIG. 3 shows a command sequence for the SDRAM of case B.

  Here, in FIGS. 2 and 3, “ACT” means a bank activate command. “READ” means a read command. “WRITE” means a write command. “PRE” means a precharge command. “REF” means a refresh command.

  As can be seen from FIG. 2, in case A, nine cycles are required to complete a series of processing. On the other hand, as can be seen from FIG. 3, in case B, only 7 cycles are required to complete a series of processing.

  Thus, it can be seen that the effective transfer efficiency of the SDRAM changes depending on the place where the refresh process is inserted. The present invention suppresses a decrease in the effective transfer efficiency of the SDRAM by optimizing the refresh execution timing in this way.

  Hereinafter, based on the drawings showing the embodiments of the present invention, the timing at which the refresh process is performed will be specifically described.

<Embodiment 1>
The memory control device according to the present embodiment is characterized in that refresh processing is performed on the SDRAM at the timing when bank activation processing is required. FIG. 4 is a block diagram showing a configuration of the memory control device according to the present embodiment.

  As shown in FIG. 4, the memory control device 100 includes first and second threshold setting units 1 and 2, a refresh counter 3, an average refresh interval setting unit 4, first and second comparison units 5 and 6, and BANK / ROW. The address comparison unit 7, the refresh request generation unit 8, the request arbitration unit 9, and the SDRAM command issue unit 10 are configured.

  FIG. 4 also shows the bus master 200 and the SDRAM 300 in addition to the memory control device 100.

  Here, the SDRAM 300 is a DRAM that operates in synchronization with a clock input from the outside. Further, in the SDRAM 300, read / write processing is continuously performed on the storage areas belonging to the same BANK / same ROW address without bank activation processing.

  The bus master 200 is a device that issues a memory access request to the SDRAM 300. There may be cases where a plurality of bus masters 200 exist. However, only one is shown here for simplicity. Examples of the bus master 200 include a CPU (Central Processing Unit) and a DMAC (Direct Memory Access Controller).

  As shown in FIG. 4, the output unit o <b> 1 of the first threshold setting unit 1 is connected to the input unit i <b> 3 of the first comparison unit 5. The output unit o2 of the second threshold setting unit 2 is connected to the input unit i5 of the second comparison unit 6.

  The output unit o3 of the refresh counter 3 is connected to the input unit i4 of the first comparison unit 5 and the input unit i6 of the second comparison unit 6. The input unit i1 of the refresh counter 3 is connected to the output unit o4 of the average refresh interval setting unit 4, and the input unit i2 is connected to the output unit o9 of the request arbitration unit 9.

  The input unit i9 of the refresh request generation unit 8 is connected to the output unit o7 of the BANK / ROW address comparison unit 7, and the input unit i10 is connected to the output unit o5 of the first comparison unit 5. The input unit i11 is connected to the output unit o6 of the second comparison unit 6. The output unit o8 of the refresh request generation unit 8 is connected to the input unit i12 of the request arbitration unit 9.

  The output unit o10 of the request arbitration unit 9 is connected to the input unit i14 of the SDRAM command issue unit 10. The output unit o11 of the SDRAM command issuing unit 10 is connected to the input unit i15 of the SDRAM 300, and the output unit o12 is connected to the input unit i8 of the BANK / ROW address comparing unit 7.

  The output unit o13 of the bus master 200 is connected to the input unit i7 of the BANK / ROW address comparison unit 7 and the input unit i13 of the request arbitration unit 9, respectively.

  Next, each part which comprises the memory control apparatus 100 is demonstrated.

  The first and second threshold setting units 1 and 2 are registers that hold (store) threshold values that serve as reference values for switching the refresh control method.

  The average refresh interval setting unit 4 is a register that holds (stores) an average value of required refresh intervals (hereinafter referred to as an average refresh interval value).

  The refresh counter 3 is a device that normally counts down as the number of cycles increases. When the refresh process for the SDRAM 300 is executed, the refresh counter 3 adds the average refresh interval value held in the average refresh interval setting unit 4 to the current count value.

  The first comparison unit 5 is a device for comparing the magnitude relationship between the count value of the refresh counter 3 and the threshold value (hereinafter referred to as the first threshold value) held in the first threshold value setting unit 1. If the count value is larger, the first comparison unit 5 outputs a signal “1”.

  The second comparison unit 6 is a device for comparing the magnitude relationship between the count value of the refresh counter 3 and a threshold value (hereinafter referred to as a second threshold value) held in the second threshold value setting unit 2. If the count value is larger, the second comparison unit 6 outputs a signal “1”.

  The BANK / ROW address comparison unit 7 compares the current active ROW information (including BANK information) AR output from the SDRAM command issuing unit 10 with the BANK / ROW address in the memory access request output from the bus master 200. To do. If the two match as a result of the comparison, the BANK / ROW address comparison unit 7 outputs a signal of “1”.

  Here, the active ROW information AR is information held by the SDRAM command issuing unit 10 as internal information, and the BANK address and ROW address in the active state of the SDRAM 300 can be known from the active ROW information AR. .

  As will be described later, the SDRAM command issuing unit 10 issues a command sequence including a plurality of commands. The SDRAM command issuing unit 10 creates the active ROW information AR by referring to the contents of the command sequence. Then, the SDRAM command issuing unit 10 holds the created active ROW information AR as an internal state.

  The refresh request generator 8 implements the following logic.

  If a signal of “0” is output from the first comparison unit 5 (that is, as a result of comparison processing in the first comparison unit 5, the count value of the refresh counter 3 is less than or equal to the first threshold value. Case) (hereinafter referred to as case α), the refresh request generator 8 outputs a refresh request signal (outputs a signal of “1”).

  If the first comparison unit 5 outputs a signal of “1” (that is, when the count value of the refresh counter 3 is greater than the first threshold as a result of the comparison process in the first comparison unit 5), In addition, a signal of “0” is output from the second comparison unit 6 (that is, when the count value of the refresh counter 3 is equal to or smaller than the second threshold value as a result of the comparison process in the second comparison unit 6). In the case where the signal “0” is output from the BANK / ROW address comparison unit 7 (that is, the current active ROW information output from the SDRAM command issuing unit 10 in the BANK / ROW address comparison unit 7 ( BANK information) and the BANK / ROW address in the memory access request output from the bus master 200, as a result of comparison processing, the BANK address or ROW address is To become case) (hereinafter, referred to as casing beta), a refresh request generation unit 8 outputs a signal to output a refresh request signal ( "1").

  If the signal “1” is output from the first comparator 5 and the signal “0” is output from the second comparator 6, the BANK / ROW address comparator 7 outputs “1”. (That is, the current active ROW information (including BANK information) AR output from the SDRAM command issuing unit 10 in the BANK / ROW address comparison unit 7 and the memory output from the bus master 200) When the BANK address and the ROW address match each other as a result of the comparison process with the BANK / ROW address in the access request (hereinafter referred to as case γ), the refresh request generation unit 8 outputs a refresh request signal. No (outputs a signal of “0”).

  If a signal “1” is output from the first comparator 5 and a signal “1” is output from the second comparator 6 (that is, a comparison process in the second comparator 6). As a result, when the count value of the refresh counter 3 is larger than the second threshold value (hereinafter referred to as case δ), the refresh request generator 8 does not output a refresh request signal (“0” signal is output). Output).

  In case α and case δ, the above processing is performed regardless of the signal output from the BANK / ROW address comparison unit 7.

  The request arbitration unit 9 arbitrates between a memory access request output from the bus master 200 and a refresh request output from the refresh request generation unit 8. Then, one of the requests is output to the SDRAM command issuing unit 10. Here, the arbitration method of the request arbitration unit 9 is a method in which a refresh request is always output to the SDRAM command issuing unit 10 with priority.

  The SDRAM command issuing unit 10 receives a memory access request and a refresh request input via the request arbitration unit 9. Then, in order to output to the SDRAM 300, the SDRAM command issuing unit 10 issues a command sequence configured in the order of acceptance.

  Next, the operation of the memory control device 100 according to the present embodiment shown in FIG. 4 will be described. In the first threshold setting unit 1, “5” is set as the first threshold. In the second threshold setting unit 2, “9” is set as the second threshold. The average refresh interval setting unit 4 is set to “10” as the average refresh interval value.

  Further, it is assumed that the bus master 200 outputs a memory access sequence including a series (9 in FIG. 5) of memory access requests shown in FIG.

  In FIG. 5, a memory access request IDi (i = 1, 2,..., 9) indicates the i-th memory access request. RD indicates read access to the SDRAM 300. WT indicates a write access to the SDRAM 300.

  BANK address Bk indicates the kth bank address. ROW addressRl indicates the row address of the lth row. Further, COLUMN addressCm indicates the column address of the m-th column. Note that k, l, and m are natural numbers.

  FIG. 6 shows changes in the states and signals of the circuits shown in FIG. 4 with respect to the memory access sequence shown in FIG.

  In FIG. 6, the first line is the number of cycles. The second line is the memory access request ID number output from the bus master 200. The third line is the counter value of the refresh counter 3. The fourth line is an output signal of the second comparison unit 6. The fifth line is an output signal of the first comparison unit 5.

  The sixth line shows the BANK address among the currently active ROW information (active ROW information) managed (held) by the SDRAM command issuing unit 10. The seventh line indicates a ROW address in the ROW information. The eighth line is the BANK address of the memory access request output from the bus master 200, and the ninth line is the ROW address.

  The 10th line is an output signal of the BANK / ROW address comparison unit 7. The eleventh line is an output signal of the refresh request generation unit 8. The twelfth line is a command for the SDRAM 300 output from the SDRAM command issuing unit 10. The thirteenth line is a BANK address for the SDRAM 300 output from the SDRAM command issuing unit 10. Furthermore, the 14th line is a ROW address or a COLUMN address for the SDRAM 300, which is output from the SDRAM command issuing unit 10.

  In the command display on the eleventh line in FIG. 6, “READ” indicates a read processing command. “WRITE” indicates a write processing command. “ACT” represents a bank activation processing command. “PRE” indicates a bank precharge processing command. “REF” represents a refresh processing command.

  First, as shown in FIG. 6, in the first cycle, the memory access request ID <b> 1 is output from the bus master 200. The memory access request ID1 is a data read processing command from the storage element of the SDRAM 300 corresponding to the addresses B1, R1, and C1, as shown in FIG.

  In the SDRAM 300, the bank activation process is executed for the storage areas of the BANK address B1 and the ROW address R1 before the memory access request ID1 read process (second cycle) (first cycle in FIG. 6). . That is, the bank activation processing command is issued before the data read command.

  At this time, the counter value of the refresh counter 3 is “10”. Therefore, since the counter value “10” is larger than the second threshold value “9” stored in the second threshold value setting unit 2, a signal “1” is output from the second comparison unit 6. Is done. Further, since the counter value “10” is larger than the first threshold value “5” stored in the first threshold value setting unit 1, a signal “1” is output from the first comparison unit 5. Is done.

  As described above, the counter value of the refresh counter 3 decreases as the number of cycles increases. Therefore, after the second cycle, the counter value of the refresh counter 3 is equal to or less than the second threshold value. Therefore, a signal “0” is output from the second comparison unit 6 (the fourth line in FIG. 6).

  In the third cycle, the memory access request ID2 (data read processing from the storage element of the SDRAM 300 corresponding to the addresses B1, R1, and C2) shown in FIG. Is input. At this time, the counter value of the refresh counter 3 is “8”. That is, it is larger than the first threshold “5” and smaller than the second threshold “9”. Therefore, a signal “1” is output from the first comparison unit 5, and a signal “0” is output from the second comparison unit 6.

  In the third cycle, the active ROW information AR output from the SDRAM command issuing unit 10 is (B1, R1).

  Then, the BANK / ROW address comparison unit 7 receives the BANK / ROW address (B1, R1) in the memory access request ID2 from the bus master 200, and the BANK / ROW address (B1, R1) in the active state in the third cycle. ) Match each other (that is, a signal of “1” is output from the BANK / ROW comparing unit 7 (see FIG. 6)). This corresponds to the above case γ.

  Therefore, the refresh request generator 8 does not output a refresh request (that is, a signal “0” is output from the refresh request generator 8 (see FIG. 6)). Therefore, the SDRAM command issuing unit 10 issues a data read processing command to the corresponding storage element of the SDRAM 300 according to the memory access request ID 2 (see FIG. 6).

  Next, in the fourth cycle, the memory access request ID3 (data read processing from the storage element of the SDRAM 300 corresponding to the addresses B1, R2, and C3) output from the bus master 200 shown in FIG. 7 and 9. At this time, the counter value of the refresh counter 3 is “7”. That is, it is larger than the first threshold “5” and smaller than the second threshold “9”. Therefore, a signal “1” is output from the first comparison unit 5, and a signal “0” is output from the second comparison unit 6.

  In the fourth cycle, the active ROW information AR output from the SDRAM command issuing unit 10 is (B1, R1).

  Then, the BANK / ROW address comparison unit 7 receives the BANK / ROW address (B1, R2) in the memory access request ID2 from the bus master 200, and the BANK / ROW address (B1, R1) in the active state in the fourth cycle. ) Does not completely match (that is, a signal of “0” is output from the BANK / ROW comparison unit 7, see FIG. 6). This corresponds to the case β.

  Therefore, the refresh request generator 8 outputs a refresh request (that is, a signal “1” is output from the refresh request generator 8 (see FIG. 6)). Then, the SDRAM command issuing unit 10 issues a bank precharge processing command in order to set the storage area (addresses B1, R1) currently active in an inactive state. In addition, the active ROW information AR output from the SDRAM command issuing unit 10 at this time becomes invalid (indicated as “X” in FIG. 6).

  Then, in the fifth cycle (the refresh counter value becomes “6”) after issuing the bank precharge processing command, the SDRAM command issuing unit 10 issues a refresh processing command to the SDRAM 300 in response to the refresh request. Issue (see FIG. 6).

  Further, in response to the refresh request output via the request arbitration unit 9, the refresh counter 3 sets the average refresh interval value “10” stored in the average refresh interval setting unit 4 to the current count value “6”. Is added (sixth cycle in FIG. 6).

  Accordingly, in the sixth cycle, the count value “16” of the refresh counter is larger than the first and second threshold values, so that the first and second comparison units 5 and 6 output a signal “1”. The

  In the sixth cycle, in the SDRAM 300, the bank activation process is executed for the storage areas of the BANK address B1 and the ROW address R2 before the memory access request ID3 is read (seventh cycle). Therefore, in the sixth cycle, the SDRAM command issuing unit 10 issues a bank activate processing command prior to the read processing command.

  Now, from the sixth cycle to the twelfth cycle, the count value of the refresh counter 3 is larger than the second threshold “9”. This is the case of the above case δ.

  Therefore, during the period from the sixth cycle to the twelfth cycle, the refresh request generation unit 8 does not output the refresh request signal (continues to output the signal “0”). Then, the SDRAM command issuing unit 10 issues a command such as normal data read processing for the SDRAM 300 in accordance with the memory access request IDs 4, 5, and 6 output from the bus memory 200 (see FIG. 6).

  That is, the storage area in the active state is the BANK address Bi and the ROW address Ri, and the memory access request output from the bus master 200 is for the storage area of the BANK address Bi and the ROW address Ri (that is, Both BANK / ROW addresses match exactly). At this time, without issuing the bank precharge processing command and the bank activation processing command, a processing command such as data reading according to the memory access request is issued.

  Further, assume that the storage areas in the active state are the BANK address Bi and the ROW address Ri, and the memory access request output from the bus master 200 is for the storage areas of the BANK address Bj and the ROW address Rj (that is, (If the BANK address or the ROW address do not match) At this time, a bank precharge processing command and a subsequent bank activation processing command are issued. Thereafter, a processing command such as data reading according to the memory access request is issued.

  Now, after the thirteenth cycle, the counter value of the refresh counter 3 becomes “9” or less. That is, the counter value is equal to or smaller than the second threshold “9”. Accordingly, the refresh request generator 8 performs the operation shown in either case β or case γ.

  If the refresh request generator 8 does not generate a refresh request after the thirteenth cycle, the memory control device 100 instructs the SDRAM 300 according to the memory access request IDs 7 and 8 output from the bus memory 200. Ordinary data read processing or the like is executed (see FIG. 6).

  Here, in the fifteenth and sixteenth cycles, the memory access request IDs 7 and 8 output from the bus master 200 are input to the BANK / ROW address comparison unit 7. The BANK address and the ROW address in the memory access request IDs 7 and 8 are the BANK in the active ROW information (the active information is output from the SDRAM command issuing unit 10 in the fifteenth and sixteenth cycles). It matches the address and ROW address (case γ).

  Therefore, the SDRAM command issuing unit 10 does not issue the refresh processing command of the SDRAM 300, but issues processing commands such as data reading and writing to the corresponding storage element according to the memory access request IDs 7 and 8.

  In the seventeenth cycle, the counter value of the refresh counter 3 is “5”. The counter value corresponds to the first threshold “5” or less. That is, both the first and second comparison units 5 and 6 output “0” signals. This case corresponds to case α.

  Accordingly, the refresh request generator 8 outputs a refresh request signal (outputs a signal “1”) regardless of the signal output from the BANK / ROW address comparator 7.

  Thus, in the seventeenth cycle, the SDRMA command issuing unit 10 issues a bank precharge processing command in order to deactivate the storage area that is currently active.

  In the eighteenth cycle, the SDRAM command issuing unit 10 issues a refresh processing command for the SDRAM 300.

  Thereafter, in the nineteenth cycle, before issuing a data read processing command (20th cycle) in accordance with the memory access request ID 9 from the SDRAM command issuing unit 10, the SDRAM command issuing unit 10 stores the corresponding BANK address and ROW address in the storage area. On the other hand, a bank activation processing command is issued.

  In the eighteenth cycle, since the refresh process has been performed, the average refresh interval value “10” is added to the count value “4” of the refresh counter 3. That is, in the nineteenth cycle, the counter value of the refresh counter 3 is “14”.

  Therefore, the case δ is applied after the nineteenth cycle. Therefore, the refresh request generation unit 8 does not output a refresh request signal regardless of the output of the BANK / ROW comparison unit 7 until the counter value becomes equal to or smaller than the second threshold “9”.

  FIG. 7 schematically shows changes in the counter value of the refresh counter 3 with respect to the number of cycles when the memory control device 100 according to the present embodiment is used. In FIG. 7, the vertical axis represents the counter value, and the horizontal axis represents the number of cycles. In the above embodiment, the first threshold value “5”, the second threshold value “9”, and the refresh interval value “10” have been described. However, the schematic diagram of FIG. 7 has a setting different from the setting of each threshold value and the like.

  “Circle” is a case where the BANK / ROW address of the memory access request and the BANK / ROW address of the active ROW information AR match each other. “Star” is a case where the BANK address or ROW address of the memory access request does not match the BANK address or ROW address of the active ROW information AR. An “arrow” indicates addition of an average refresh interval value after the refresh process.

  As shown in FIG. 7, in the case where the counter value is equal to or smaller than the second threshold value, if the address mismatch event occurs continuously, the refresh process is continuously performed each time. Each time the refresh process is performed, the average refresh interval value is added to the counter value.

  However, if the counter value is larger than the second threshold value, the refresh process is not performed.

  Further, when the address coincidence event occurs continuously, the counter value can be equal to or less than the first threshold value. However, when the count value continues to decrease and falls below the first threshold value, the refresh process is forcibly executed. Then, the average refresh interval value is added to the count value.

  As described above, the memory control device 100 according to the present embodiment performs the refresh process on the SDRAM 300 aiming at the timing when the bank activation process is necessary, as in the cases β and γ.

  Therefore, as described with reference to FIGS. 2 and 3, it is possible to prevent the refresh process from being performed while continuously accessing the same BANK / same ROW address. That is, it is not necessary to perform useless bank precharge processing and useless bank activation processing.

  Therefore, even if the refresh process is performed on the SDRAM 300, since it is performed at the timing when the bank activation is performed, the loss of effective data transfer efficiency can be minimized.

  In addition, the memory control device 100 according to the present embodiment has an average refresh interval setting unit 4 that holds an average refresh interval value. When the refresh process is performed, the average refresh interval value is added to the counter value of the refresh counter 3.

  Therefore, although the refresh process interval does not become constant, the average refresh process interval can be made substantially equal to the average refresh interval value in the long term.

  In addition, the memory control device 100 according to the present embodiment includes a first comparison unit 5 that compares the first threshold value with the count value of the refresh counter 3. When the counter value is equal to or smaller than the first threshold value as a result of the comparison by the first comparison unit 5, the refresh request generation unit 8 generates a refresh request.

  Therefore, when the BANK address and the ROW address of the memory access request from the bus master 200 continuously match the BANK address and the ROW address of the active ROW information AR, the SDRAM 300 is forcibly refreshed. Processing can be performed.

  The refresh process is performed after the process in accordance with the memory access request in the previous stage is completed. Therefore, the first threshold value should be set to be equal to or greater than the maximum number of processing cycles required for one memory access request.

  In addition, the memory control device 100 according to the present embodiment includes a second comparison unit 6 that compares the second threshold value with the count value of the refresh counter 3. When the counter value is larger than the second threshold as a result of the comparison by the second comparison unit 6, the refresh request generation unit 8 does not generate a refresh request.

  Therefore, by setting the second threshold value to an appropriate value based on an empirical rule or the like, useless SDRAM 300 when the amount of charge stored in SDRAM 300 is sufficient and there is no need to perform refresh processing. The refresh process can be prevented.

  When the counter value of the refresh counter 3 becomes larger than the second threshold value, the refresh process is not performed. Therefore, the maximum counter value that the refresh counter 3 can take is when the refresh process is performed at the second threshold value.

  As described above, the first threshold value is desirably set to be equal to or greater than the maximum number of processing cycles required for one memory access request. Therefore, if the restriction is strictly observed, the minimum counter value that the refresh counter 3 can take is “0”. That is, when the counter value of the refresh counter 3 is “0”, the refresh process may be forcibly performed.

  As described above, the number of cycles between refresh processes is at most (second threshold value) + (average refresh interval value).

  By the way, the SDRAM 300 defines an upper limit period tREF until the next refresh process is necessary after the refresh process is performed once. Therefore, if the second threshold value is set too large, the number of cycles between refresh processes may exceed the upper limit period tREF.

  Therefore, it is necessary to set the second threshold within a range in which the number of cycles between refresh processes does not exceed the upper limit period tREF.

  Further, the memory control device according to the present embodiment has a request arbitration unit 9. The request arbitration unit 9 is a device that arbitrates between a memory access request and a refresh request, and outputs the refresh request to the subsequent SDRAM command issuing unit 10 with priority. Therefore, it has the following effects.

  That is, it is assumed that the memory access request is prioritized over the refresh request and is input to the SDRAM command issuing unit 10. At this time, even if a refresh request is generated at the timing when bank activation is performed, in the command sequence issued by the SDRAM command issuing unit 10, the order of the refresh requests is delayed from the timing.

  However, by providing the request arbitration unit 9, it is possible to prevent the occurrence of the above problems.

  In addition, the memory control device according to the present embodiment includes an SDRAM command issuing unit 10 that holds active ROW information AR of the SDRAM 300 as an internal state.

  Therefore, the internal state of the SDRAM command issuing unit 10 can be referred to during the comparison process in the BANK / ROW address comparing unit 7. Therefore, it is possible to reduce the work of referring to the active state of the SDRAM 300 during the comparison process, and to perform the comparison process more simply.

  In the above description, the SDRAM command issuing unit 10 manages (holds) the active ROW information AR without distinguishing between banks. That is, when the BANK address and ROW address in the active ROW information AR are the same as the BANK address and ROW address in the memory access request, the bank precharge / bank activation process is not performed. This is control for improving the efficiency of memory access.

  On the other hand, apart from the above, the SDRAM command issuing unit 10 may be configured to manage (hold) the active ROW information AR by distinguishing banks. In other words, when the ROW address in the active ROW information is the same as the ROW address in the memory access request, the bank precharge / bank activation process may not be performed. As a result, the memory access can be made more efficient than in the former case.

<Embodiment 2>
The memory control device according to the present embodiment is characterized in that the SDRAM is subjected to refresh processing aiming at an idle cycle timing in which there is no memory access request from the bus master (no access to the memory). FIG. 8 is a block diagram showing a configuration of the memory control device according to the present embodiment.

  Memory control device 100 (FIG. 8) according to the present embodiment differs from memory control device 100 (FIG. 4) according to the first embodiment in the following points.

  In the memory control device 100 according to the first embodiment, two threshold setting units 1 and 2 and comparison units 5 and 6 are provided. However, the memory control device 100 according to the present embodiment includes only one threshold setting unit 21 and one comparison unit 22.

  Further, in the memory control device 100 according to the present embodiment, an idle cycle detection unit 23 is arranged instead of the BANK / ROW address comparison unit 7.

  Since other configurations and connection relationships are the same as those of the memory control device 100 according to the first embodiment, a detailed description thereof is omitted here.

  FIG. 8 also shows the bus master 200 and the SDRAM 300 in addition to the memory control device 100 as in the first embodiment. The description of bus master 200 and SDRAM 300 is as described in the first embodiment.

  In FIG. 8, a threshold value setting unit 21 is a register that holds (stores) a third threshold value that is a reference for switching the refresh control method. The comparison unit 22 is a device for comparing the magnitude relationship between the count value of the refresh counter 3 and the third threshold value set in the threshold value setting unit 21. If the count value is larger, the comparison unit 22 outputs a signal of “1”.

  The idle cycle detection unit 23 is a circuit that monitors the state of the memory access request output from the bus master 200 and the active ROW information AR output from the SDRAM command issue unit 10.

  The idle cycle detection unit 23 detects an idle cycle when there is no memory access request output from the bus master 200 and no command sequence is issued from the SDRAM command issuing unit 10 to the SDRAM 300.

  When the idle cycle detection unit 23 detects the idle cycle, the idle cycle detection unit 23 outputs a signal “1” to the refresh request generation unit 8. As a result, the refresh request generator 8 can be notified that the idle cycle detector 23 has detected an idle cycle.

  The refresh request generator 8 implements the following logic.

  If a signal “1” is output from the comparison unit 22 (that is, if the count value of the refresh counter 3 is larger than the third threshold as a result of the comparison process in the comparison unit 22) (hereinafter, The refresh request generator 8 does not output a refresh request signal (outputs a signal “0”).

  If the comparison unit 22 outputs a signal “0” (that is, if the count value of the refresh counter 3 is equal to or smaller than the third threshold as a result of the comparison process in the comparison unit 22), and the idle cycle is detected. When the signal “0” is output from the unit 23 (that is, the idle cycle detection unit 23 has not detected an idle cycle) (hereinafter referred to as case ζ), the refresh request generation unit 8 No signal is output (“0” signal is output).

  If the comparison unit 22 outputs a “0” signal and the idle cycle detection unit 23 outputs a “1” signal (the idle cycle detection unit 23 has detected an idle cycle) The refresh request generator 8 outputs a refresh request signal (outputs a signal “1”).

  In case ε, the above processing is performed regardless of the output result from the idle cycle detection unit 23.

  Next, the operation of the memory control device 100 according to the present embodiment shown in FIG. 8 will be described. In the threshold setting unit 21, “50” is set as the third threshold. The average refresh interval setting unit 4 is set to “10” as the average refresh interval value.

  Also, the bus master 200 includes a memory access sequence including a series of memory access requests shown in FIG. 9 (five in FIG. 9) (in FIG. 9, a part “IDLE” in which no memory access request is output is included in the middle). Is output).

  The meaning content of each symbol shown in FIG. 9 is the same as that of each symbol shown in FIG. 5 described in the first embodiment.

  FIG. 10 shows changes in the states and signals of the circuits shown in FIG. 8 with respect to the memory access sequence shown in FIG.

  In FIG. 10, the first line is the number of cycles. The second line is the memory access request ID number output from the bus master 200. The third line is the counter value of the refresh counter 3. The fourth line is an output signal of the comparison unit 22. The fifth line is an output signal of the idle cycle detection unit 23. The sixth line is an output signal of the refresh request generator 8.

  The seventh line is a command for the SDRAM 300 output from the SDRAM command issuing unit 10. The eighth line is a BANK address for the SDRAM 300 output from the SDRAM command issuing unit 10. Further, the ninth line is a ROW address or a COLUMN address for the SDRAM 300 output from the SDRAM command issuing unit 10.

  In FIG. 10, “NOP” indicates a state in which there is no command issued from the SDRAM command issuing unit 10. The meanings and contents of the other symbols shown in FIG. 10 are the same as those of the symbols shown in FIG. 6 described in the first embodiment.

  First, as shown in FIG. 10, in the first cycle, the memory access request ID <b> 1 is output from the bus master 200. The memory access request ID1 is a data read processing command from the storage element of the SDRAM 300 corresponding to the addresses B1, R1, and C1, as shown in FIG.

  In the SDRAM 300, the bank activation process is executed for the storage area of the BANK address B1 and the ROW address R1 before the memory access request ID1 is read (second cycle) (first cycle in FIG. 10). . That is, the SDRAM command issuing unit 10 issues a bank activate processing command before issuing a read processing command.

  At this time, the counter value of the refresh counter 3 is “51”. Therefore, since the counter value “51” is larger than the third threshold value “50” stored in the threshold setting unit 21, a signal “1” is output from the comparison unit 22.

  As in the first embodiment, the counter value of the refresh counter 3 decreases every time the number of cycles increases. Accordingly, after the second cycle, the counter value of the refresh counter 3 is equal to or less than the third threshold value. Therefore, a signal “0” is output from the comparison unit 22 (fourth line in FIG. 6).

  In the second and third cycles, the SDRAM command issuing unit 10 issues a read processing command for the storage element at the corresponding address. Here, the read command is in accordance with the memory access requests ID1 and ID2 shown in FIG.

  In the second and third cycles (the counter values of the refresh counter 3 are “50” and “49”, respectively), the idle cycle is not detected. Therefore, the second and third cycles correspond to case ζ. Therefore, the refresh request generator 8 does not generate a refresh request (that is, the refresh request generator 8 outputs a signal “0”).

  Next, in the fourth cycle, the idle cycle detection unit 23 does not output a memory access request from the bus master 200, and does not issue a memory access request to the SDRAM 300 from the SDRAM command issue unit 10. , Is detected. That is, the idle cycle detection unit 23 detects an idle cycle.

  Therefore, the idle cycle detection unit 23 outputs a signal “1”, and the refresh request generation unit 8 receives the signal.

  By the way, in the fourth cycle, the counter value of the refresh counter 3 is “48”. That is, the counter value satisfies a condition equal to or smaller than the third threshold value.

  From the above, the fourth cycle corresponds to case η, and the refresh request generator 8 generates a refresh request. That is, the refresh request generator 8 outputs a signal “1” (see FIG. 10).

  Therefore, in the fourth cycle, prior to the refresh process for the SDRAM 300, the SDRAM command issuing unit 10 issues a bank precharge process command to deactivate the storage areas (addresses B1 and R1) that are currently active. Is issued.

  Then, after issuing the bank precharge processing command, in the fifth cycle (the refresh counter value becomes “47”), the SDRAM command issuing unit 10 issues a refresh processing command to the SDRAM 300 in response to the refresh request. (See FIG. 10).

  Further, in response to the refresh request output via the request arbitration unit 9, the refresh counter 3 sets the average refresh interval value “10” stored in the average refresh interval setting unit 4 to the current count value “47”. Are added (sixth cycle in FIG. 6).

  Therefore, in the sixth cycle, the count value “57” of the refresh counter becomes larger than the third threshold value, and therefore the signal “1” is output from the comparison unit 22.

  Also, in the sixth cycle, before issuing the memory access request ID3 read processing command (seventh cycle), the SDRAM command issuing unit 10 issues a bank activation processing command to the storage areas of the BANK address B1 and the ROW address R1. To do.

  Now, from the sixth cycle to the twelfth cycle, the count value of the refresh counter 3 is larger than the third threshold “50”. This is the case of the case ε.

  Therefore, in the eleventh cycle, the idle cycle detection unit 23 detects the idle cycle, but the refresh request generation unit 8 does not output the refresh request signal (continues to output the signal “0”).

  Therefore, during the period from the sixth cycle to the twelfth cycle, the SDRAM command issuing unit 10 according to the memory access request IDs 3, 4, and 5 output from the bus memory 200 regardless of whether or not the idle cycle is detected. A normal data read processing command or the like is issued (see FIG. 6).

  That is, the storage area in the active state is the BANK address Bi and the ROW address Ri, and the memory access request output from the bus master 200 is for the storage area of the BANK address Bi and the ROW address Ri (that is, Both BANK / ROW addresses match exactly).

  At this time, the bank precharge processing command and the bank activation processing command are not issued, and the SDRAM command issuing unit 10 issues a processing command such as data read according to the memory access request.

  Further, assume that the storage areas in the active state are the BANK address Bi and the ROW address Ri, and the memory access request output from the bus master 200 is for the storage areas of the BANK address Bj and the ROW address Rj (that is, (If the BANK address or the ROW address do not match)

  At this time, the SDRAM command issuing unit 10 issues a bank precharge processing command and a subsequent bank activation processing command. After that, the SDRAM command issuing unit 10 issues a processing command such as data reading according to the memory access request.

  In the eleventh cycle, since no memory access request is output from the bus master 200, the SDRAM command issuing unit 10 does not issue a command (idle cycle). In FIG. 10, “NOP” is indicated.

  As described above, the memory control device 100 according to the present embodiment performs the refresh process on the SDRAM 300 aiming at the idle cycle timing as in the cases ζ and η. Therefore, it has the following effects.

  For example, it is assumed that the refresh process for the SDRAM 300 is performed in a cycle different from the idle cycle. In this case, the number of idle cycles N1 and the number of cycles N2 required for refresh processing (number of cycles required for bank precharge processing + number of cycles required for refresh processing + number of cycles required for bank activation processing) are required. That is, a total of N1 + N2 cycles are required.

  However, the idle cycle number N1 can be reduced by using the idle cycle as in the present embodiment and performing the refresh process during the idle cycle. That is, only the total number of N2 cycles is sufficient.

  Therefore, by adopting memory control device 100 according to the present embodiment, even if refresh processing is performed on SDRAM 300, loss of effective data transfer efficiency can be minimized.

  The memory control device 100 according to the present embodiment also has an average refresh interval setting unit 4 that holds an average refresh interval value. When the refresh process is performed, the average refresh interval value is added to the counter value of the refresh counter 3.

  Therefore, as in the first embodiment, the refresh processing interval does not become constant, but when viewed in the long term, the average refresh processing interval should be approximately equal to the average refresh interval value. Can do.

  Further, the memory control device 100 according to the present embodiment includes a comparison unit 22 that compares the third threshold value with the count value of the refresh counter 3. Then, as a result of the comparison by the comparison unit 22, when the counter value is larger than the third threshold value, the refresh request generation unit 8 does not generate a refresh request.

  If the third threshold value is set too low, there is a high possibility that the third threshold value will not be executed although the refresh process is required. On the other hand, if the third threshold is set too high, unnecessary refresh processing may be frequently performed.

  Accordingly, by setting the third threshold value to an appropriate value based on an empirical rule or the like, useless SDRAM 300 when the amount of charge stored in SDRAM 300 is sufficient and there is no need to perform refresh processing. The refresh process can be prevented.

  The memory control device 100 according to the present embodiment also includes a request arbitration unit 9 and an SDRAM command issue unit 10. Therefore, the effect similar to the effect demonstrated in Embodiment 1 can be acquired also in this Embodiment.

  In the above description, the SDRAM command issuing unit 10 manages (holds) the active ROW information AR without distinguishing between banks. That is, when the BANK address and ROW address in the active ROW information AR are the same as the BANK address and ROW address in the memory access request, the bank precharge / bank activation process is not performed. This is control for improving the efficiency of memory access.

  On the other hand, as described in the first embodiment, the SDRAM command issuing unit 10 may be configured to manage (hold) the active ROW information AR by distinguishing banks. In other words, when the ROW address in the active ROW information is the same as the ROW address in the memory access request, the bank precharge / bank activation process may not be performed. As a result, the memory access can be made more efficient than in the former case.

<Embodiment 3>
The memory control device according to the present embodiment is a combination of the first embodiment and the second embodiment. In other words, the memory control device according to the present embodiment performs a refresh process on the SDRAM with the aim of the timing when the bank activation process is necessary and the timing of the idle cycle where there is no memory access request from the bus master. And FIG. 11 is a block diagram showing a configuration of the memory control device according to the present embodiment.

  The memory control device 100 (FIG. 11) according to the present embodiment has the memory control device 100 (FIG. 8) according to the second embodiment in addition to the memory control device 100 (FIG. 4) according to the first embodiment. Further, an idle cycle detection unit 23, a threshold setting unit (referred to as a third threshold setting unit in the present embodiment) 21 and a comparison unit (referred to as a third comparison unit in the present embodiment) 22 are added. It is a thing.

  Other circuits, configurations, and the like are the same as those in the first and second embodiments, and a description thereof is omitted here.

  FIG. 11 also shows the bus master 200 and the SDRAM 300 in addition to the memory control device 100 as in the first and second embodiments. The description of bus master 200 and SDRAM 300 is as in the first and second embodiments.

  As shown in FIG. 11, the SDRAM command issuing unit 10 according to the present embodiment manages (holds) the active ROW information BAR for each of the four banks. That is, when the ROW address in the active ROW information corresponding to the bank address in the memory access request is the same as the ROW address in the memory access request, the bank precharge / bank activation process is not performed.

  The logic of the refresh request generation unit 8 according to this embodiment will be described with reference to FIG.

  In FIG. 12, the vertical axis represents the counter value of the refresh counter 3. The horizontal axis represents the number of cycles. The first, second, and third threshold values are threshold values set in the first threshold value setting unit 1, the second threshold value setting unit 2, and the third threshold value setting unit 21, respectively.

  “Circle” indicates a case where the BANK / ROW address of the memory access request and the BANK / ROW address of the active ROW information match. “Star” is a case where the BANK address or ROW address of the Mori access request does not match the BANK address or ROW address of the active ROW information. The “square mark” is a case where an idle cycle is detected. An “arrow” indicates addition of an average refresh interval value after the refresh process.

  When the counter value of the refresh counter 3 is larger than the third threshold value, the refresh request generator 8 outputs the refresh request signal regardless of the result of the idle cycle detector 23 and the result of the BANK / ROW address comparator 7. Does not output (outputs a signal of “0”).

  When the counter value of the refresh counter 3 is equal to or smaller than the third threshold and greater than the second threshold, if the idle cycle detection unit 23 detects an idle cycle, the refresh request generator 8 A request signal is output (a signal of “1” is output).

  However, when the idle cycle cycle detection unit 23 does not detect an idle cycle, the refresh request generation unit 8 does not output a refresh request signal (“0” signal) regardless of the result of the BANK / ROW address comparison unit 7. Is output).

  When the refresh counter value is equal to or smaller than the second threshold and greater than the first threshold, if the idle cycle cycle detection unit 23 detects an idle cycle, or the BANK / ROW address comparison unit 7 When a mismatch between the BANK address / ROW address of the active ROW information and the BANK address / ROW address of the memory access request is confirmed, in each case, the refresh request generator 8 outputs a refresh request signal (“1 ”Signal).

  However, when the idle cycle detection unit 23 does not detect an idle cycle, the BANK / ROW address comparison unit 7 determines that the BANK address / ROW address of the active ROW information matches the BANK address / ROW address of the memory access request. If confirmed, the refresh request generator 8 does not output a refresh request signal (outputs a signal of “0”).

  When the refresh counter value is equal to or smaller than the first threshold, the refresh request generator 8 forcibly refreshes regardless of the detection result of the idle cycle cycle detector 23 and the comparison result of the BANK / ROW address comparator 7. A request signal is output (a signal of “1” is output).

  As described above, since the memory control device 100 according to the present embodiment is combined with the memory control device 100 according to the first and second embodiments, the same effects as the first and second embodiments can be obtained. .

It is a figure which shows a memory access sequence example. It is a figure which shows the command sequence of an example with bad data transfer efficiency. It is a figure which shows the command sequence of an example with the sufficient data transfer efficiency. 1 is a diagram illustrating a configuration of a memory control device according to a first embodiment. 6 is a diagram illustrating an example of a memory access sequence for explaining an operation of the memory control device according to the first embodiment; FIG. 6 is a diagram for explaining an operation of the memory control device according to the first embodiment; FIG. It is a figure which shows the mode of the change of the counter value of a refresh counter. FIG. 4 is a diagram illustrating a configuration of a memory control device according to a second embodiment. FIG. 10 is a diagram showing a memory access sequence example for explaining the operation of the memory control device according to the second embodiment. FIG. 10 is a diagram for explaining the operation of the memory control device according to the second embodiment. FIG. 10 is a diagram illustrating a configuration of a memory control device according to a third embodiment. It is a figure which shows the mode of the change of the counter value of a refresh counter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 1st threshold value setting part, 2nd 2nd threshold value setting part, 3 refresh counter, 4 average refresh space | interval setting part, 5 1st comparison part, 6 2nd comparison part, 7 BANK / ROW address comparison part, 8 Refresh request generation unit, 9 request arbitration unit, 10 SDRAM command issuance unit, 21 (third) threshold setting unit, 22 (third) comparison unit, 23 idle cycle detection unit, 100 memory controller, 200 bus master, 300 SDRAM.

Claims (15)

An address comparison unit that compares the first address in the active information indicating the active state of the memory with the second address in the memory access request;
A refresh request generation unit that generates a refresh request for the memory according to the comparison result of the address comparison unit,
A memory control device comprising: An idle cycle detector for detecting an idle cycle in which no memory is accessed;
A refresh request generator for generating a refresh request for the memory in response to detection of an idle cycle of the idle cycle detector;
A memory control device comprising: An average refresh interval setting unit for holding an average refresh interval value;
A counter that decreases the count value as the number of cycles increases, and adds the average refresh interval value to the counter value when the refresh process of the memory is performed based on the refresh request; In addition,
3. The memory control device according to claim 1, wherein the memory control device is a memory control device. A threshold setting unit for holding a predetermined threshold;
A comparison unit that compares the predetermined threshold value with the count value of the counter, and
The refresh request generation unit
Generating a refresh request according to the comparison result of the address comparison unit and the comparison result of the comparison unit;
The memory control device according to claim 1. The threshold setting unit includes:
A first threshold value setting unit for holding a first threshold value;
A second threshold value setting unit that holds a second threshold value that is larger than the first threshold value,
The comparison unit includes:
A first comparison unit for comparing a first threshold value and the count value;
A second comparison unit that compares a second threshold value and the count value,
The memory control device according to claim 4. The refresh request generation unit
As a result of the comparison in the second comparison unit, when the counter value is larger than the second threshold value, a refresh request is not generated.
The memory control device according to claim 5. The refresh request generation unit
When the counter value is less than or equal to a second threshold value as a result of comparison in the second comparison unit, and the counter value is greater than the first threshold value as a result of comparison in the first comparison unit If the BANK address and ROW address of the first address match the BANK address and ROW address of the second address, respectively, as a result of the comparison by the address comparison unit, no refresh request is generated. ,
When the counter value is less than or equal to a second threshold value as a result of comparison in the second comparison unit, and the counter value is greater than the first threshold value as a result of comparison in the first comparison unit If the BANK address or ROW address of the first address does not match the BANK address or ROW address of the second address as a result of the comparison by the address comparison unit, a refresh request is generated.
The memory control device according to claim 5, wherein the memory control device is a memory control device. The refresh request generation unit
As a result of the comparison in the first comparison unit, when the counter value is less than or equal to the first threshold, a refresh request is generated.
8. The memory control device according to claim 5, wherein the memory control device is a memory control device. A threshold setting unit for holding a predetermined threshold;
A comparison unit that compares the predetermined threshold value with the count value of the counter, and
The refresh request generation unit
In response to detection of an idle cycle of the idle cycle detection unit and a comparison result of the comparison unit, a refresh request is generated.
The memory control device according to claim 2. The refresh request generation unit
As a result of the comparison in the comparison unit, when the counter value is larger than the predetermined threshold, a refresh request is not generated.
The memory control device according to claim 9. The refresh request generation unit
As a result of the comparison in the comparison unit, when the counter value is equal to or less than the predetermined threshold value and the idle cycle detection unit detects the idle cycle, the refresh request is generated,
As a result of the comparison in the comparison unit, when the counter value is equal to or less than the predetermined threshold and the idle cycle detection unit does not detect the idle cycle, the refresh request is not generated.
The memory control device according to claim 9 or 10, wherein A command issuing unit for issuing a command sequence for the memory in the order of acceptance;
A request arbitration unit that arbitrates the memory access request and the refresh request, and prioritizes the refresh request and outputs the request to the command issuing unit;
12. The memory control device according to claim 1, wherein the memory control device is a memory control device. The command issuing unit
Holding the active ROW information as an internal state;
The memory control device according to claim 12. The memory is composed of at least two banks,
The command issuing unit
The active ROW information is held as internal information for each bank.
The memory control device according to claim 13. An address comparison unit that compares the first address in the active information indicating the active state of the memory with the second address in the memory access request;
An idle cycle detector for detecting an idle cycle without access to the memory;
A refresh request generator for generating a refresh request for the memory in response to a comparison result of the address comparator and detection of an idle cycle of the idle cycle detector;
A memory control device comprising:

Images