JP2006003398A - Driving method of plasma display panel - Google Patents

Abstract

Provided is a plasma display panel driving method capable of displaying a good image without causing a false discharge phenomenon even with a panel having an increased xenon partial pressure.
A sustain pulse for generating a sustain discharge for causing a discharge cell to emit light with a predetermined luminance weight is applied to a scan electrode and a sustain electrode during the sustain period, and the last of the sustain pulses applied to the scan electrode is The pulse width of sustain pulse Pw is wider than that of other sustain pulses Pm, and pulse voltage Vn (V) of last sustain pulse Pw is lower than pulse voltage Vm (V) of other sustain pulses Pm.
[Selection] Figure 4

Description

  The present invention relates to a method for driving a plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of pairs of display electrodes made up of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrodes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs formed on the back side in parallel with the data electrodes. A phosphor layer is formed on the side surface of the partition wall. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed at a portion where the display electrode and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of RGB colors are excited and emitted by this ultraviolet light to perform color display.

  As a method for driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. Each subfield has an initializing period, an address period, and a sustain period. In the initializing period, an initializing discharge is generated in the discharge cell, and in the addressing period, an address discharge is selectively applied to the discharge cell to be lit. In the sustain period, a sustain discharge is generated to emit light with a predetermined luminance weight for the discharge cells that have generated the address discharge.

  Among the subfield methods, Patent Document 1 discloses a novel driving method in which light emission not related to gradation display is reduced as much as possible to suppress an increase in black luminance and an contrast ratio is improved. According to this driving method, during the initializing period, all the cell initializing operations for performing initializing discharge for all the discharge cells that perform image display, or the discharge cells that have been subjected to the sustain discharge in the immediately preceding subfield are performed. On the other hand, one of the selective initializing operations for selectively performing initializing discharge is performed. Further, by reducing the number of subfields having an initialization period for performing all-cell initialization operation among a plurality of subfields constituting one field, light emission not related to image display can be suppressed, and contrast can be reduced. High image display is possible.

Further, Patent Document 2 discloses a novel driving method that includes a subfield having a single wide pulse in the sustain period and improves gradation in a dark screen. According to this driving method, the erase operation can be performed simultaneously with the sustain discharge with a single thick pulse, and the light emission at that time becomes darker than the light emission when the sustain pulse is used. It is possible to express gradations that are darker than the minimum gradation.
JP 2000-242224 A JP 2002-014652 A

  In recent years, studies have been made to increase the luminous efficiency of the panel by increasing the xenon partial pressure of the discharge gas sealed in the panel. However, if the xenon partial pressure is increased, the discharge becomes unstable, and the discharge cells that should be discharged do not discharge, or the discharge cells that should not discharge discharge, and the image display quality deteriorates. There was a problem to do. Further, there has been a problem that the drive margin of the panel is lowered even if the erroneous discharge phenomenon does not occur.

  The present invention has been made in view of these problems, and provides a panel driving method capable of displaying a good image without causing an erroneous discharge phenomenon even if the panel has an increased xenon partial pressure. With the goal.

  The panel driving method of the present invention is a plasma display panel driving method in which discharge cells are formed at intersections of scan electrodes, sustain electrodes, and data electrodes. One field period is an initialization period, an address period, and Consists of a plurality of subfields having a sustain period. In the sustain period, a sustain pulse for generating a sustain discharge for causing a discharge cell to emit light with a predetermined luminance weight is applied to the scan electrode and the sustain electrode, and applied to the scan electrode. Of the sustain pulses, the pulse width of the last sustain pulse is wider than the pulse width of the other sustain pulses, and the pulse voltage of the last sustain pulse is lower than the pulse voltage of the other sustain pulses. . According to this method, it is possible to provide a method for driving a plasma display panel capable of displaying a good image without causing a false discharge phenomenon even in a panel having an increased xenon partial pressure.

  Moreover, the discharge cell of the panel to which the driving method of the present invention is applied has a discharge gas containing 10% or more of xenon. Accordingly, it is possible to provide a method for driving a plasma display panel capable of displaying a good image without causing a false discharge phenomenon even in a panel with an increased xenon partial pressure.

  In the panel driving method of the present invention, it is desirable that at least a part of the rising period of the last sustain pulse applied to the scan electrode and the falling period of the sustain pulse applied to the sustain electrode overlap in time. This method can further suppress the erroneous discharge phenomenon.

  According to the present invention, it is possible to provide a method for driving a plasma display panel capable of displaying a good image without causing a false discharge phenomenon even if the panel has an increased xenon partial pressure.

  Hereinafter, a panel driving method according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is a perspective view showing a main part of a panel used in the embodiment of the present invention. The panel 1 is configured such that a glass front substrate 2 and a back substrate 3 are disposed to face each other and a discharge space is formed therebetween. On the front substrate 2, a plurality of scanning electrodes 4 and sustaining electrodes 5 constituting display electrodes are formed in parallel with each other. A dielectric layer 6 is formed so as to cover the scan electrode 4 and the sustain electrode 5, and a protective layer 7 is formed on the dielectric layer 6. The protective layer 7 is preferably made of a material having a large secondary electron emission coefficient and high sputtering resistance in order to generate a stable discharge, and an MgO thin film is used in the embodiment of the present invention. A plurality of data electrodes 9 covered with an insulating layer 8 are provided on the back substrate 3, and a partition wall 10 is provided in parallel with the data electrodes 9 on the insulating layer 8 between the data electrodes 9. A phosphor layer 11 is provided on the surface of the insulator layer 8 and the side surfaces of the partition walls 10. Further, the front substrate 2 and the rear substrate 3 are arranged to face each other in the direction in which the scan electrode 4 and the sustain electrode 5 and the data electrode 9 intersect, and in the discharge space formed therebetween, for example, neon And a mixed gas of xenon. In the embodiment of the present invention, the xenon partial pressure of the discharge gas sealed in the panel is increased to 10% in order to improve the light emission efficiency of the panel.

  FIG. 2 is an electrode array diagram of the panel used in the embodiment of the present invention. N scan electrodes SCN1 to SCNn (scan electrode 4 in FIG. 1) and n sustain electrodes SUS1 to SUSn (sustain electrode 5 in FIG. 1) are alternately arranged in the row direction, and m data electrodes in the column direction. D1 to Dm (data electrodes 9 in FIG. 1) are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCNi and sustain electrode SUSi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  FIG. 3 is a circuit block diagram of a plasma display device using the panel driving method according to the embodiment of the present invention. The plasma display device includes a panel 1, a data electrode drive circuit 12, a scan electrode drive circuit 13, a sustain electrode drive circuit 14, a timing generation circuit 15, an AD (analog / digital) converter 18, a scan number conversion unit 19, and a subfield. A conversion unit 20 and a power supply circuit (not shown) are provided.

  In FIG. 3, the image signal sig is input to the AD converter 18. The horizontal synchronization signal H and the vertical synchronization signal V are input to the timing generation circuit 15, the AD converter 18, the scanning number conversion unit 19, and the subfield conversion unit 20. The AD converter 18 converts the image signal sig into digital signal image data, and outputs the image data to the scanning number conversion unit 19. The scanning number conversion unit 19 converts the image data into image data corresponding to the number of pixels of the panel 1 and outputs the image data to the subfield conversion unit 20. The subfield conversion unit 20 divides the image data of each pixel into a plurality of bits corresponding to a plurality of subfields, and outputs the image data for each subfield to the data electrode driving circuit 12. The data electrode driving circuit 12 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  The timing generation circuit 15 generates a timing signal based on the horizontal synchronization signal H and the vertical synchronization signal V, and outputs the timing signal to the scan electrode drive circuit 13 and the sustain electrode drive circuit 14, respectively. Scan electrode drive circuit 13 supplies a drive voltage waveform to scan electrodes SCN1 to SCNn based on the timing signal, and sustain electrode drive circuit 14 supplies a drive voltage waveform to sustain electrodes SUS1 to SUSn based on the timing signal.

  Next, a driving voltage waveform for driving the panel and its operation will be described. In the embodiment of the present invention, one field is divided into ten subfields (first SF, second SF,..., Tenth SF), and each subfield has a luminance weight that is greater in the subsequent subfield. Explanation will be made assuming that this is configured.

  FIG. 4 is a drive voltage waveform diagram applied to each electrode when using the panel drive method according to the embodiment of the present invention, and shows the first SF and the second SF in detail. Here, the first SF is a subfield having an initialization period for performing the all-cell initialization operation (hereinafter abbreviated as “all-cell initialization subfield”), and the second SF is an initialization for performing the selective initialization operation. This is a subfield having a period (hereinafter abbreviated as “selective initialization subfield”).

  In the initializing period of the first SF, the data electrodes D1 to Dm and the sustain electrodes SUS1 to SUSn are held at 0 (V), and the discharge is started from the voltage Vp (V) that is lower than the discharge start voltage with respect to the scan electrodes SCN1 to SCNn. A ramp voltage that gradually increases toward the voltage Vr (V) exceeding the start voltage is applied. Then, the first weak initializing discharge is caused in all the discharge cells, negative wall voltages are stored on scan electrodes SCN1 to SCNn, and positive on sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm. Wall voltage is stored. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode.

  Thereafter, sustain electrodes SUS1 to SUSn are maintained at positive voltage Vh (V), and a ramp voltage that gradually decreases from voltage Vg (V) to voltage Va (V) is applied to scan electrodes SCN1 to SCNn. Then, the second weak initializing discharge is caused in all the discharge cells, the wall voltage on scan electrodes SCN1 to SCNn and the wall voltage on sustain electrodes SUS1 to SUSn are weakened, and the wall voltage on data electrodes D1 to Dm is reduced. Is also adjusted to a value suitable for the write operation.

  As described above, in the initializing period of the first SF, the all-cell initializing operation for performing initializing discharge in all the discharge cells is performed.

  In the subsequent address period, scan electrodes SCN1 to SCNn are temporarily held at Vs (V). Next, a positive address pulse voltage Vw (V) is applied to the data electrode Dk (k = 1 to m) of the discharge cell to be displayed in the first row among the data electrodes D1 to Dm, and the first row. Negative scan pulse voltage Vb (V) is applied to scan electrode SCN1. Then, a voltage obtained by adding the address pulse voltage and the scan pulse voltage is applied between scan electrode SCN1 and data electrode Dk and exceeds the discharge start voltage, so that discharge occurs at the intersection of scan electrode SCN1 and data electrode Dk. Is generated and progresses to discharge between scan electrode SCN1 and sustain electrode SUS1 of the corresponding discharge cell. A positive wall voltage is accumulated on scan electrode SCN1 of the discharge cell in which the address discharge has occurred, a negative wall voltage is accumulated on sustain electrode SUS1, and a negative wall voltage is also accumulated on data electrode Dk. Thus, address discharge is generated in the discharge cells to which the address pulse voltage Vw (V) in the first row is applied. On the other hand, in the discharge cells to which the address pulse voltage Vw (V) is not applied, the address discharge does not occur and the wall charges are not accumulated. At this time, the positive address pulse voltage Vw (V) is applied to the data electrodes Dk of the discharge cells in the second and subsequent rows, but the negative scan pulse voltage Vb (V) is applied to the scan electrodes SCNi in the second and subsequent rows. Is not applied, the voltage applied between the corresponding scan electrode SCNi and the data electrode Dk is only the address pulse voltage Vw (V) and does not exceed the discharge start voltage, so that no address discharge occurs.

  Subsequently, a positive address pulse voltage Vw (V) is applied to the data electrode Dk of the discharge cell to be displayed in the second row, and a negative scan pulse voltage Vb (V) is applied to the scan electrode SCN2 in the second row. To do. Then, a voltage obtained by adding the address pulse voltage and the scan pulse voltage is applied between the scan electrode SCN2 and the data electrode Dk to exceed the discharge start voltage, and the discharge is applied with the address pulse voltage Vw (V) in the second row. A cell address discharge occurs. On the other hand, in the discharge cells to which the address pulse voltage Vw (V) is not applied, the address discharge does not occur and the wall charges are not accumulated. Also in this case, since the voltage applied between the scan electrode SCNi and the data electrode Dk of the discharge cells in the third and subsequent rows is only the address pulse voltage Vw (V) and does not exceed the discharge start voltage, address discharge occurs. Never do.

  The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, sustain electrodes SUS1 to SUSn are returned to 0 (V), and at the same time, a wide sustain pulse Pw having a positive voltage Vn (V) is applied to scan electrodes SCN1 to SCNn. In the embodiment of the present invention, the width of the sustain pulse Pw is set to 5 μs, and the voltage Vn (V) is set to 140 (V). At this time, in the discharge cell in which the address discharge has occurred, the voltage between scan electrode SCNi and sustain electrode SUSi is equal to the voltage Vn (V) of sustain pulse Pw, and the wall voltage on scan electrode SCNi and sustain electrode SUSi. , The discharge start voltage is slightly exceeded, and a sustain discharge occurs between scan electrode SCNi and sustain electrode SUSi. A positive wall voltage is accumulated on the data electrode Dk. Here, sustain pulse Pw applied to scan electrodes SCN1 to SCNn has a wide pulse width, and voltage Vn (V) is lower than sustain pulse voltage Vm (V), which will be described later, on scan electrode SCNi and sustain electrode SUSi. When added to the wall voltage, the voltage is set slightly higher than the discharge start voltage. Therefore, the wall charges accumulated on scan electrode SCNi and sustain electrode SUSi after discharge are small, and the sustain discharge by the wide sustain pulse Pw also serves as an erasing operation, and should not be discharged in the subsequent subfield. It is possible to prevent a false discharge phenomenon such as discharge. Then, in the sustain period of the first SF, there is one light emission by applying a wide sustain pulse Pw, and there is a total of two light emissions when combined with the address discharge in the address period. In the first SF, these two times of light emission display the minimum gradation “gradation 1”.

  At this time, the sustain electrodes SUS1 to SUSn are returned from the voltage Vh (V) to 0 (V), and at the same time, the sustain pulse voltage Vn (V) is applied to the scan electrodes SCN1 to SCNn, which is applied to the scan electrodes SCN1 to SCNn. This is because the rise period of the drive voltage waveform and the fall period of the drive voltage waveform applied to the sustain electrodes SUS1 to SUSn are overlapped in time. As will be described later, this is important in preventing an erroneous discharge phenomenon such that a discharge cell to be discharged does not discharge even when a panel having a high xenon partial pressure is used.

  In the initialization period of the second SF, sustain electrodes SUS1 to SUSn are held at Vh (V), data electrodes D1 to Dm are held at 0 (V), and scan electrodes SCN1 to SCNn are directed to voltage Va (V). Apply a ramp voltage that falls slowly. Then, in the discharge cell that has undergone the sustain discharge in the sustain period of the first SF, a weak initializing discharge occurs, the wall voltages on scan electrodes SCN1 to SCNn and on sustain electrodes SUS1 to SUSn are weakened, and on data electrode Dk. The wall voltage is also adjusted to a value suitable for the write operation. On the other hand, the discharge cells that have not been subjected to the sustain discharge in the first SF are not discharged, and the wall charge state at the end of the initialization period of the first SF is maintained as it is. As described above, the initializing operation of the second SF is a selective initializing operation in which the initializing discharge is performed in the discharge cells in which the sustain discharge has been performed in the previous subfield.

  Since the writing period is the same as the writing period of the first SF, description thereof is omitted.

  In the subsequent sustain period, first, sustain electrodes SUS1 to SUSn are returned to 0 (V), and voltage Vm (V) of positive sustain pulse Pm is applied to scan electrodes SCN1 to SCNn. In the embodiment of the present invention, the width of the sustain pulse Pm is set to 3 μs, and the voltage Vm (V) is set to 180 (V). At this time, in the discharge cell in which the address discharge has occurred, the voltage due to the wall charges is added to the sustain pulse voltage Vm (V), so that the sustain discharge occurs greatly exceeding the discharge start voltage. A positive wall voltage is accumulated on data electrode Dk, and the polarity of the wall voltage on scan electrode SCNi and sustain electrode SUSi is inverted. Subsequently, when scan electrodes SCN1 to SCNn are returned to 0 (V) and voltage Vm (V) of positive sustain pulse Pm is applied to sustain electrodes SUS1 to SUSn, sustain discharge occurs again in the discharge cell, and scan electrode SCNi And the polarity of the wall voltage on the sustain electrode SUSi is reversed. Thereafter, sustain electrodes SUS1 to SUSn are returned to 0 (V), and at the same time, wide sustain pulse Pw having positive voltage Vn (V) is applied to scan electrodes SCN1 to SCNn. Then, a third sustain discharge is generated between scan electrode SCNi and sustain electrode SUSi. Here, sustain pulse voltage Vn (V) applied to scan electrodes SCN1 to SCNn is lower than sustain pulse voltage Vm (V), and when the wall voltage on scan electrode SCNi and sustain electrode SUSi is added, the discharge start voltage is slightly increased. The voltage is set to exceed. Therefore, the wall charges accumulated on scan electrode SCNi and sustain electrode SUSi after discharge are small, and the sustain discharge by the wide sustain pulse Pw also serves as an erasing operation, and should not be discharged in the subsequent subfield. It is possible to prevent a false discharge phenomenon such as discharge. However, the wall voltage on the data electrode Dk is not erased. Then, in the sustain period of the second SF, two discharges by the normal sustain pulse Pm and one erase discharge by the wide sustain pulse Pw are generated, and the total of the address discharge in the address period is four times in the second SF. There is luminescence. These four times of light emission display “gradation 2”.

  At this time, the sustain electrodes SUS1 to SUSn are returned from the voltage Vm (V) to 0 (V), and at the same time, the sustain pulse voltage Vn (V) is applied to the scan electrodes SCN1 to SCNn, which is applied to the scan electrodes SCN1 to SCNn. This is because the rising period of sustain pulse Pw and the falling period of sustain pulse Pm applied to sustain electrodes SUS1 to SUSn are overlapped in time.

  Since the initialization period and the writing period of the subfield after the third SF are the same as those of the second SF, description thereof will be omitted.

  In the sustain period of the subfield after the third SF, first, sustain electrodes SUS1 to SUSn are returned to 0 (V), and voltage Vm (V) of sustain pulse Pm is applied to scan electrodes SCN1 to SCNn. At this time, in the discharge cell in which the address discharge has occurred, the voltage due to the wall charges is added to the sustain pulse voltage Vm (V), so that the sustain discharge occurs greatly exceeding the discharge start voltage. A positive wall voltage accumulates on data electrode Dk, and the polarity of the wall voltage on scan electrode SCNi and sustain electrode SUSi is inverted. Subsequently, when the scan electrodes SCN1 to SCNn are returned to 0 (V) and the voltage Vm (V) of the sustain pulse Pm is applied to the sustain electrodes SUS1 to SUSn, the sustain discharge occurs again in the discharge cell, and the scan electrodes SCNi and The polarity of the wall voltage on the sustain electrode SUSi is inverted. The above operation is repeated as many times as necessary to display the gradation. At the end of the sustain period, the sustain electrodes SUS1 to SUSn are returned to 0 (V), and at the same time, a wide sustain pulse Pw having a positive voltage Vn (V) is applied to the scan electrodes SCN1 to SCNn to generate a sustain discharge. Let Here, since voltage Vn (V) of sustain pulse Pw applied to scan electrodes SCN1 to SCNn is lower than sustain pulse voltage Vm (V), the wall charges accumulated on scan electrode SCNi and sustain electrode SUSi after discharge are The sustain discharge caused by the small and wide sustain pulse Pw also serves as an erasing operation, and can prevent an erroneous discharge phenomenon such as discharge of a discharge cell that should not be discharged in the subsequent subfield. However, the wall voltage on the data electrode Dk is not erased. In the sustain period after the third SF, a discharge due to the normal sustain pulse Pm and a single erasure discharge due to the wide sustain pulse Pw occur, and a predetermined gradation is displayed in total with the address discharge in the address period. .

  Here, in the sustain period of each subfield, at least a part of the rising period of sustain pulse Pw last applied to scan electrodes SCN1 to SCNn and the fall period of sustain pulse Pm applied to sustain electrodes SUS1 to SUSn is timed. The reason for the overlap is explained. The reason why the erroneous discharge phenomenon such as the discharge cell to be discharged is not discharged by the drive voltage waveform described above is not completely clarified, but one factor can be considered as follows.

  FIG. 5 is a diagram showing a drive voltage waveform applied to the scan electrode and the sustain electrode in the sustain period and a light emission waveform associated therewith, and FIG. 5A shows a rise period of the drive voltage waveform of the scan electrode and the drive voltage waveform of the sustain electrode. FIG. 5 (b) shows the case where the falling periods are not overlapped.

  As shown in FIG. 5A, when the rising period of the driving voltage waveform of the scan electrode and the falling period of the driving voltage waveform of the sustain electrode are not overlapped, the sustain electrode SUSi is fixed to 0 (V). Later, a self-erasing discharge d1 is generated between sustain electrode SUSi and data electrode Dk, and the wall voltage on data electrode Dk is erased. When voltage Vn (V) is applied to scan electrode SCNi, sustain discharge d2 is generated between scan electrode SCNi and sustain electrode SUSi. On the other hand, when the rising period and the falling period are overlapped as shown in FIG. 5B, the self-erase discharge is not substantially generated, and the sustain discharge d3 is generated between the scan electrode SCNi and the sustain electrode SUSi. It has occurred. The sustain discharge d3 at this time is larger than the sustain discharge d2 in the first sustain period. This is because the sustain discharge d3 is a discharge including the data electrode Dk, and it is considered that a positive wall voltage is formed on the data electrode Dk.

  Then, since the positive wall voltages are sufficiently stored on the data electrodes Dk, the subsequent subfield selective initialization operation can be stabilized and a stable write operation can be performed. That is, when a ramp voltage that gradually decreases toward voltage Va (V) is applied to scan electrode SCNi in the subsequent initialization period, between sustain electrode SUSi and scan electrode SCNi and between data electrode Dk and scan electrode SCNi. A stable weak initializing discharge is generated. Then, the wall voltage on scan electrode SCNi and the wall voltage on sustain electrode SUSi are weakened, and the wall voltage on data electrode Dk can be adjusted to a value suitable for the write operation. However, when the positive wall voltage on the data electrode Dk is insufficient, the initialization discharge does not occur in the subsequent subfield initialization period, or even if it occurs, sufficient wall voltage adjustment is not performed. A wall voltage suitable for operation is not formed. Therefore, it is considered that the problem that the address discharge becomes unstable occurs.

  In the panel driving method according to the embodiment of the present invention, the sustain pulse rising period applied to scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUS1 when applying sustain pulse Pw having a wide width in the sustain period as described above. The falling period of the sustain pulse applied to SUSn is temporally overlapped. By this driving method, the subsequent initialization operation, particularly the selective initialization operation is stabilized, and wall charge formation suitable for the write operation is performed.

  In the embodiment of the present invention, the width of sustain pulse Pw is set to 5 μs, voltage Vn (V) is set to 140 (V), the width of sustain pulse Pm is set to 3 μs, and voltage Vm (V) is set to 180 (V). Was set. However, these are not limited to the above-mentioned values, and the erroneous discharge phenomenon is least likely to occur in the range of the width of the sustain pulse Pw> the width of the sustain pulse Pm and the voltage Vn (V) <the voltage Vm (V). It is desirable to set the driving margin to a wide value.

  Further, in the embodiment of the present invention, the first SF is the all-cell initializing subfield, but the all-cell initializing subfield can be set to any subfield regardless of the sustain period maintaining operation.

  The panel driving method of the present invention is useful as a plasma display panel driving method and the like because it can display a good image without causing a false discharge phenomenon even if the panel has an increased xenon partial pressure.

The perspective view which shows the principal part of the panel used for embodiment of this invention Electrode arrangement of the panel Circuit block diagram of plasma display device using panel driving method according to embodiment of present invention Drive voltage waveform diagram applied to each electrode when using this drive method The figure which shows the drive voltage waveform applied to a scan electrode and a sustain electrode in a sustain period, and the light emission waveform accompanying it

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Panel 2 Front substrate 3 Back substrate 4 Scan electrode 5 Sustain electrode 9 Data electrode 12 Data electrode drive circuit 13 Scan electrode drive circuit 14 Sustain electrode drive circuit 15 Timing generation circuit

Claims (3)

A method for driving a plasma display panel in which discharge cells are formed at intersections of scan electrodes, sustain electrodes, and data electrodes,
One field period is composed of a plurality of subfields having an initialization period, an address period, and a sustain period.
In the sustain period, a sustain pulse for generating a sustain discharge for causing the discharge cell to emit light with a predetermined luminance weight is applied to the scan electrode and the sustain electrode,
Of the sustain pulses applied to the scan electrodes, the pulse width of the last sustain pulse is wider than the pulse width of the other sustain pulses, and the pulse voltage of the last sustain pulse is larger than the pulse voltage of the other sustain pulses. A driving method of a plasma display panel characterized by being low. 2. The method of driving a plasma display panel according to claim 1, wherein the discharge cell has a discharge gas containing 10% or more of xenon. The at least part of the rising period of the last sustain pulse applied to the scan electrode and the falling period of the sustain pulse applied to the sustain electrode overlap in time. A driving method of the plasma display panel as described.

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