JP2006093717A - Field effect transistor having a deformed channel layer and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor having a deformed channel layer and a manufacturing method thereof.
A field effect transistor including a channel layer formed on a side wall of a structure on a semiconductor substrate, wherein at least a part of the channel layer is deformed in a direction in which the side wall of the structure extends from the semiconductor substrate, and its manufacture Is the method. The transistor is a FinFET, and the structure on the semiconductor substrate including the fin structure and the side wall is the side wall of the fin structure. The channel layer is a silicon epitaxial layer 160 and can be formed on an internal fin structure comprising alternating layers of silicon germanium 120 and silicon 140. The channel layer includes a deformed portion and an undeformed portion. The deformed portion and the undeformed portion become the side wall of the channel layer.
[Selection] Figure 4B

Description

  The present invention relates to a semiconductor device, and more particularly to a field effect transistor (FET) and related devices.

  This application claims priority from Korean Patent Application No. 2004-77593 filed on September 25, 2004, the contents of which are hereby incorporated by reference.

  Over the last 30 years, the development of silicon-based integrated circuit technologies such as MOS (Metal Oxide Semiconductor) devices including field effect transistors (FETs and / or MOSFETs) has led to increased device speed, improved integration and low cost. Improved device performance has been provided. As shown in FIG. 1A, a MOS device is typically in a substrate 10 having a heavily doped source / drain (S / D) region 12 separated by a more lightly doped channel region 18. It is formed. The channel region 18 can be controlled by a gate electrode 14 that is separated from the channel region by a gate dielectric 16.

  However, not only high performance, low power consumption, and high economic efficiency, but also with increasing demand for high integration, many problems related to deterioration of transistor characteristics have occurred. For example, as the transistor channel length decreases, punch through, DIBL (Drain Induced Barrier Lowering), subthreshold swing, increased parasitic capacitance between junction region and substrate (ie, junction capacitance), increased leakage current Such a short channel effect occurs.

  Various designs for transistors have evolved to solve some of the problems faced by conventional bulk MOS semiconductor devices. Such transistor designs include, for example, ultra-thin body transistors, double gate transistors, RCAT (Recessed Channel Array Transistors), FinFETs and GAATs (Gate All Around Transistors).

  For example, FIG. 1B shows a conventional ultra-thin body transistor. In the ultra-thin body transistor, the channel region 18 can be formed in a thin film layer on the insulating region. FIG. 1C illustrates a conventional double gate transistor. In a double gate transistor, a single channel region 18 can be controlled by two gates 14a, 14b separated from the channel region by gate dielectrics 16a, 16b. Thereby, both sides of the channel region can be controlled.

  However, the device of FIGS. 1B and 1C requires more complex manufacturing techniques, which causes an increase in cost and a decrease in yield. Therefore, such a device is not practical in general semiconductor manufacturing.

  For example, an ultra-thin body transistor is considerably expensive to manufacture compared to a conventional bulk MOS device. Even though providing improved performance in several areas, ultra-thin body transistors are sensitive to floating body effects and heat transfer effects and have limitations imposed by body thickness.

  Also, by controlling the channel from both sides, the double gate device can exhibit improved leakage performance. However, the double gate device requires a more complicated manufacturing process, thus increasing the cost and reducing the yield. In particular, in the manufacture of a double gate transistor, as shown in FIG. 1C, it is difficult to align the upper gate 14a and the lower gate 14b.

  GAAT is described in Patent Document 1, for example.

  FinFET transistors with channel regions made of vertically protruding “fins” made of semiconductor material provide similar or better leakage performance than double gate transistors, but are not complicated to manufacture , Low cost. FinFET transistors (or simply FinFETs) are scaled to channel lengths of 50 nm or less (possibly as small as 10 nm), which can provide additional improvements in integration and operating speed. The structure of the FinFET is described in Patent Document 2.

  In the FinFET, the channel region is formed in the vertical fin-shaped active region protruding from the semiconductor substrate as described above. A gate dielectric is formed on the fin and a gate electrode is formed along the periphery of the fin. The channel region can be formed first, and then the S / D region can be formed. The S / D region may be formed higher than the fin. Dielectric and conductive materials can then be used to form double and / or triple gate devices.

  2A to 2D are cross-sectional views of a semiconductor substrate for explaining a conventional method for forming a FinFET.

  As shown in FIG. 2A, an etching mask pattern 13 is formed on the silicon substrate 10. A portion of the silicon substrate 10 exposed by the etching mask pattern 13 is anisotropically etched to form silicon fins 15. The upper edge of the silicon fin 15 is formed at a sharp angle (for example, a substantially right angle) by anisotropic etching. The etching mask pattern 13 is formed of nitride, and a thermal oxide layer is formed between the nitride and the substrate. In order to ensure electrical insulation between adjacent silicon fins, an element isolation layer 17 is formed as shown in FIG. 2B.

  As shown in FIG. 2C, a part of the element isolation layer 17 is removed, and the side surface or the side wall of the silicon fin 15 is exposed. The side surface of the silicon fin 15 can serve as a channel region of the transistor.

  As shown in FIG. 2D, the gate insulating layer 19 is formed on the exposed side wall of the silicon fin 15, and the gate electrode 21 is formed so that a double gate FinFET can be formed. Both side walls of the silicon fin 15 can be controlled by the gate electrode 21.

  According to the conventional method for forming the double gate FinFET, when the element isolation layer 17 is removed, the adhesion between the etching mask pattern 13 and the substrate 10 can be weakened. Further, since the element isolation layer 17 can be formed of an oxide, the thermal oxide layer of the etching mask pattern 13 formed on a part of the silicon fin 15 is removed together with a part of the element isolation layer 17. There is also. In order to further improve the degree of device integration, the width of the silicon fin 15 is narrowed, and the possibility that the etching mask pattern 13 is separated from the upper surface of the silicon fin 15 is increased. If the etching mask pattern is removed, the upper surface of the silicon fin 15 is controlled by the gate electrode 21 to form a triple gate FinFET. Thus, double gate and triple gate FinFETs can be formed on the same wafer.

  As shown in FIG. 2D, the width of the silicon fin 15 is narrowed by performing a thermal oxidation process before forming the gate insulating layer 19 in order to form a high performance element. That is, the width of the silicon fin 15 is reduced by forming a sacrificial oxide layer on the sidewall of the silicon fin 15 using a thermal oxidation process and then removing the sacrificial oxide layer. Thereby, the silicon fin 15 is narrower than the etching mask pattern 13. Therefore, an undercut region is formed below the etching mask pattern 13 and the step coverage becomes poor during a subsequent process such as deposition of a gate insulating material. Furthermore, if the sacrificial oxide layer is removed, the thermal oxide layer of the etching mask pattern 13 can also be partially removed. As a result, the etching mask pattern 13 is separated from the silicon fin 15 and the above-described problem occurs.

  Triple gate FinFETs have been developed to solve some of these problems. In the triple gate FinFET, the upper surface and both side walls of the silicon fin are controlled by the gate electrode, which improves the current driving capability.

  A conventional method for forming a triple gate FinFET will be described with reference to FIGS. 3A and 3B. The triple gate FinFET may be formed by removing the etching mask pattern in a conventional manner for forming the double gate FinFET described above with reference to FIGS. 2A-2D.

  As shown in FIG. 2B, silicon fins 15 and element isolation layers 17 are formed. Next, as shown in FIG. 3A, a part of the element isolation layer 17 and the etching mask pattern 13 are removed. As a result, the upper surface and both side walls of the silicon fin 15 are exposed.

  As shown in FIG. 3B, the gate insulating layer 19 is formed on the exposed surface (ie, both side walls and the upper surface) of the silicon fin 15, and then the gate electrode 21 is formed.

Transistors with improved mobility using deformed channels have been investigated to improve transistor performance. Such transistors typically use a thick epitaxial SiGe layer as a stress generator, or an epitaxial SGOI (Silicon on Germanium In Insulator) wafer. However, using a thick SiGe layer or SGOI wafer is expensive to manufacture. Further, transistors with modified channels have typically been implemented with a flat structure. Transistors having a modified channel are described in, for example, Non-Patent Documents 1 to 6, and the disclosed contents are incorporated herein by reference.
US Pat. No. 6,391,782 (assigned to Yu under the name “PROCESS FOR FORMING MULTIPLE ACTIVLINES AND GATE-ALL-AROUND MOSFET”) US Pat. No. 6,413,802 (named “FINFET TRANSISTOR STRUCTURES HAVING A DOUBLE GATE CHANNEL EXTENDING VERTICALLY FROM FROM A SUBSTRATE AND METHODS OF MANUFACTURE”) Hoyt's paper "Strained Silicon MOSFET Technology" (Electron Devices Meeting, 2002. IEDM '02 Digest. International, pp. 23-26). Ota's paper "Novel Locally Strained Channel Technology for High Performance 55nm CMOS" (Electron Devices Meeting, 2002. IEDM '02 Digest. International 30, 27). Rim's paper “Fabrication and Mobility Characteristic of Ultra-thin Strained Si Dirty on Insulator (SSDOI) MOSFETs” (Electron Devices 3E. Ed. Takagi paper "Channel Structure Design, Fabrication and Carrier Transport Properties of Strained-Si / SiCe-On-Insulator (Strained SOI) MOSFETs" (Electron Devices Meeting, 2003.IEDM '03 Technical Digest.IEEE International, pp.3.3 .1-3.3.4) Ge, “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering”, Electron Devices Meeting, 2003. IEDM '03 Technical Digest. 3E. Ernst's paper “Fabrication of a novel strained SiGe: C-channel planer 55 nm nMOSFET for High-Performance CMOS” (2002 Symposium on VLSI Technology Digests)

  A problem to be solved by the present invention is to provide an FET that improves the current mobility characteristics of a semiconductor device by forming a deformable layer that improves electron mobility in at least a part of the channel layer, and a method for manufacturing the same. It is in.

  An embodiment of the present invention for solving the above problem includes a channel layer formed on a side wall of a structure formed on a semiconductor substrate, and at least a part of the channel layer is formed on the structure. Provided is an FET whose side wall is deformed in a direction extending from the semiconductor substrate, and a method for manufacturing the same.

  In a particular embodiment of the invention, the transistor comprises a FinFET, the structure comprises a fin structure, and the sidewall comprises a sidewall of the fin structure. The channel layer includes a silicon epitaxial layer. The channel layer is thinner than about 100 mm. In a particular embodiment of the invention, the substrate comprises a silicon substrate. The channel layer may include a deformed portion and an undeformed portion. The deformed portion and the undeformed portion include a side wall of the channel layer.

  In another embodiment of the present invention, the fin structure includes a plurality of different material layers. Each of the plurality of different material layers includes an upper surface that is basically parallel to the substrate on the opposite side of the substrate and a side wall surface that is basically perpendicular to the substrate, and the channel layer includes the plurality of layers. Can be formed directly on the side wall surfaces of different material layers.

  In another embodiment of the present invention, the fin structure comprises alternating layers of silicon and silicon germanium. The alternating layers comprise epitaxial layers. The alternating silicon layers are thinner than about 30 inches. The silicon germanium layer of the alternating layer is thinner than about 50 mm. The alternating layers include one or more silicon layers and one or more silicon germanium layers. The outermost layer of the alternating layers is a silicon germanium layer. A part of the channel layer may be directly disposed on the outermost layer of the alternating layer.

  In still another embodiment of the present invention, a FinFET is formed on the gate dielectric formed in the channel layer, a gate electrode formed on a portion of the gate dielectric, and on the opposite side of the gate electrode. Source and drain regions are provided. The channel layer includes a silicon epitaxial layer. The source and drain regions comprise a silicon epitaxial layer. The fin structure and the source and drain regions include a plurality of different material layers. The fin structure and the source and drain regions comprise alternating layers of silicon and silicon germanium. The alternating layers comprise epitaxial layers. The gate electrode includes a polysilicon layer. In a specific embodiment of the present invention, the channel layer includes a portion deformed in a direction parallel to the gate width. The gate dielectric and the gate electrode have a damascene structure.

  The FinFET may further include a first dielectric layer formed on the substrate, the fin structure may extend through the first dielectric layer, and the channel layer may include the channel layer. A fin structure is disposed on a portion of the fin structure that extends beyond the first dielectric layer. The fin structure includes a portion of the substrate, and the portion of the fin structure provided by the substrate extends beyond the first dielectric layer. Alternatively, the fin structure includes a portion of the substrate, and the portion of the fin structure provided by the substrate does not extend beyond the first dielectric layer.

  An embodiment of the present invention includes an inner channel structure including a plurality of different material layers having sidewalls extending from a semiconductor substrate, and an outer channel layer formed on the sidewalls of the inner channel structure and having sidewalls. A FinFET and a method for manufacturing the same are provided. The outer channel layer also includes sidewalls. A gate dielectric layer is provided that is formed on the sidewalls and the top surface of the outer channel layer and includes the sidewalls and the top surface on the opposite side of the outer channel layer. A gate electrode is provided that is formed on a portion of the sidewall and upper surface of the gate dielectric layer. A source region and a drain region disposed on opposite sides of the gate electrode are provided.

  In another embodiment of the present invention, the external channel layer comprises a silicon epitaxial layer. Further, each of the plurality of different material layers includes an upper surface which is basically parallel to the substrate on the opposite side of the substrate and a side wall surface which is basically perpendicular to the substrate. The channel layer may be directly formed on a sidewall surface of the plurality of different material layers.

  In yet another embodiment of the present invention, the inner channel structure comprises alternating layers of silicon and silicon germanium. The alternating layers comprise epitaxial layers. The alternating layers include one or more silicon layers and one or more silicon germanium layers. The outermost layer of the alternating layers is a silicon germanium layer. A part of the channel layer may be directly disposed on the outermost layer of the alternating layer. The gate electrode includes a polysilicon layer.

  In another embodiment of the present invention, a first dielectric layer is provided on the substrate. The inner channel structure extends through the first dielectric layer, and the outer channel layer is disposed on a portion of the inner channel structure that extends beyond the first dielectric layer. The inner channel structure includes a portion of the substrate, and a portion of the inner channel structure provided by the substrate extends beyond the first dielectric layer. Alternatively, the inner channel structure includes a portion of the substrate, and the portion of the inner channel structure provided by the substrate does not extend beyond the first dielectric layer.

  In still another embodiment of the present invention, the substrate comprises a silicon substrate. The outer channel layer includes a portion deformed in a direction parallel to the gate width. The gate dielectric and the gate electrode have a damascene structure. The outer channel layer includes a deformed portion and an undeformed portion. The deformed portion and the undeformed portion include sidewalls of the outer channel layer.

  In one embodiment of the present invention, an inner channel structure is formed on a semiconductor substrate and includes a sidewall extending from the substrate and an upper surface opposite to the substrate, and on the sidewall and upper surface of the inner channel structure. Provided is a FinFET having an outer channel layer formed and having an opposite side wall and an upper surface of the inner channel structure, and a method of manufacturing the same. A portion of the outer channel layer formed on the sidewall of the inner channel structure is deformed. A gate dielectric layer is provided on the sidewalls and top surface of the outer channel layer, with the sidewalls and top surface opposite the outer channel layer. A gate electrode is provided on a portion of the sidewall and upper surface of the gate dielectric layer. A source region and a drain region are disposed on the opposite side of the gate electrode.

  In still another embodiment of the present invention, the external channel layer comprises a silicon epitaxial layer. The inner channel structure includes a plurality of different material layers. Each of the plurality of different material layers includes an upper surface which is basically parallel to the substrate on the opposite side of the substrate and a side wall surface which is basically perpendicular to the substrate. The outer channel layer may be directly formed on a sidewall surface of the plurality of different material layers. The inner channel structure includes alternating layers of silicon and silicon germanium. The alternating layers comprise epitaxial layers. The alternating layers include one or more silicon layers and one or more silicon germanium layers. The outermost layer of the alternating layers is a silicon germanium layer. A part of the channel layer may be directly disposed on the outermost layer of the alternating layer. The gate electrode includes a polysilicon layer.

  In yet another embodiment of the present invention, a first dielectric layer is provided on the substrate. The inner channel structure may extend through the first dielectric layer, and the outer channel layer may be disposed on a portion of the inner channel structure that extends beyond the first dielectric layer. The inner channel structure includes a portion of the substrate, and a portion of the inner channel structure provided by the substrate extends beyond the first dielectric layer. Alternatively, the inner channel structure includes a portion of the substrate, and the portion of the inner channel structure provided by the substrate does not extend beyond the first dielectric layer.

  In still another embodiment of the present invention, the substrate comprises a silicon substrate. The outer channel layer includes a portion deformed in a direction parallel to the gate width. The gate dielectric and the gate electrode have a damascene structure. The outer channel layer includes a deformed portion and an undeformed portion. The deformed portion and the undeformed portion include sidewalls of the outer channel layer.

  According to the present invention, the current mobility characteristic of the semiconductor element is improved by forming the deformation layer that improves the electron mobility in at least a part of the channel layer.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; such embodiments are intended to complete the disclosure and embrace the spirit of the invention; It is provided in order to fully communicate to the contractor. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like reference numbers generally refer to like elements.

  An embodiment of the present invention will be described with reference to FIGS. 4A to 7 showing a FinFET structure having a channel region in which at least a part of the channel region is deformed and a method of manufacturing the FinFET. However, the present invention should not be construed as limited to FinFET structures and may be used for other structures in which the channel is formed on the sidewalls of the underlying structure. Thus, for example, a modified channel can be provided for RCAT or GAAT in addition to the FinFET structures described herein. Accordingly, an embodiment of the present invention is used in an FET structure having a channel layer on a sidewall of the structure, wherein at least a part of the channel layer of the FET is deformed in a direction in which the sidewall of the structure extends from the semiconductor substrate. Is done.

  FIG. 4A is a cross-sectional view illustrating a portion of a FinFET according to some embodiments of the present invention. 4B is an isometric view of the gate and channel region of the FinFET of FIG. 4A. As shown in FIGS. 4A and 4B, the substrate 110 includes an inner fin structure 400 that includes a layer that is lattice-matched to the outer fin structure 410 and a layer that is lattice-mismatched, and the outer fin structure 410 includes: A channel in which at least a portion of the outer fin structure 410 is deformed in a direction perpendicular to the direction of current in the outer fin structure 410 (eg, the vertical direction shown in FIGS. 4A and 4B) is provided. As will be described later, if the difference in lattice constant between the two layers is not sufficient to induce sufficient strain to improve carrier mobility, the layers used here are lattice matched. If the difference between the lattice constants of the two layers is sufficient to induce sufficient strain to improve carrier mobility, then the lattice mismatch. In particular embodiments of the present invention, the substrate 110 is a silicon substrate and / or an SOI substrate. The internal fin structure 400 includes a silicon germanium layer 120 and a silicon layer 140, each of which is an epitaxial layer. In addition, the external fin structure 410 is a silicon layer 160 formed by selective epitaxial growth on the sidewalls. In some embodiments, the silicon layer 160 is directly on the silicon germanium layer 120 and the silicon layer 140. The inner fin structure 400 may be directly formed on the sidewall. In some embodiments, the outermost layer of the inner fin structure 400 is a silicon germanium layer 120.

  In particular embodiments of the present invention, the gate dielectric layer 180 is provided on the outer fin structure 410 and the gate electrode 220 is provided on the gate dielectric layer 180. In some embodiments of the invention, the gate electrode 180 is a polysilicon layer. A first dielectric layer 200 is shown in FIGS. 4A and 4B, and a portion of the inner fin structure 400 extends through the first dielectric layer 200. The gate dielectric layer 180 includes an oxide such as silicon dioxide, and is a layer suitable for use in a FinFET structure or a suitable gate dielectric layer. Similarly, the first dielectric layer 200 is a suitable dielectric material including, for example, silicon dioxide. In the embodiment shown in FIGS. 4A and 4B, a portion of the inner fin structure 400 provided by the substrate 110 does not basically extend beyond the first dielectric layer 200. However, in an alternative embodiment, as shown in FIG. 7, the substrate 110 ′ and the first dielectric layer 200 ′ are part of the inner fin structure 400 ′ provided by the substrate 110 ′. Provided in a position extending beyond the dielectric layer 200 ', the outer fin structure 410' is provided on a portion of the substrate 110 'protruding from the first dielectric layer 200'.

  4C illustrates an S / D region 300 (not shown in FIGS. 4A, 4B, and 7) provided on the opposite side of the gate electrode 220. As shown in FIG. The S / D region 300 may be doped at a higher concentration than the channel region of the inner fin structure 400 or the outer fin structure 410. The particular dopant used to dope the S / D region 300 is determined by whether the device provided is an nMOS device or a pMOS device. In some embodiments, the S / D region 300 may be provided with alternating layers of silicon germanium 120 and silicon 140. Further, the S / D region 300 may be provided by the silicon epitaxial layer 160. In addition, the S / D region 300 may be provided by a silicon or silicon germanium region. The silicon germanium provided in the S / D region 300 may be doped at a higher concentration than if only silicon was provided in the S / D region 300. Further, the S / D region 300 may be limited by a region that is counter-doped through ion implantation to limit the S / D region.

  In some embodiments of the invention, the silicon layer 140 and the silicon germanium layer 120 are provided as epitaxial layers. The silicon germanium layer 120 may include about 30% germanium so as to provide a 1.2% difference in lattice constant between the silicon germanium layer 120 and the silicon epitaxial layer 160. The silicon germanium layer 120 is as thick as possible, but is not so thick as to significantly reduce the quality of the silicon germanium layer 120 due to, for example, dislocation defects in the silicon germanium layer.

  The specific thickness of the silicon germanium layer 120 depends on the amount of germanium in the layer, but in some embodiments, a thickness of about 20 nm for a silicon germanium layer having about 30% germanium. Can be provided. In some embodiments, the silicon layer 140 has a thickness of about 5 nm and the silicon germanium layer 120 has a thickness of about 20 nm. The number of silicon layers 140 and silicon germanium layers 120 depends on the overall height of the internal fin structure 400 and the thickness of the individual layers. However, in some embodiments, more than one silicon layer and more than one silicon germanium layer may be provided. In particular embodiments of the present invention, the silicon layer 140 has a thickness of about 30 mm or less, and the silicon germanium layer has a thickness of about 50 mm or less. In some embodiments of the present invention, the overall height of the inner fin structure 400 is about 100 nm to about 150 nm. The alternating outermost layer is a silicon germanium layer 120 as shown in FIG. 4A.

  The outer fin structure 410 may be provided by a silicon epitaxial layer 160 formed on the inner fin structure 400. The silicon epitaxial layer 160 has a thickness that is at least the expected channel depth of the device. However, in some embodiments, the silicon epitaxial layer 160 is thinner than the expected depth of the device channel such that the channel extends into the internal fin structure 400 in operation. The silicon epitaxial layer 160 may be grown to a thickness of about 20 to about 100 inches prior to the formation of the gate oxide 180, although other thicknesses may be used. The gate oxide 180 is formed by thermal oxidation and may consume part of the silicon epitaxial layer 160. About 45% of the silicon epitaxial layer 160 can be consumed during the thermal oxidation process to provide the gate oxide 180. After forming the gate oxide 180, at least about 10% of the silicon epitaxial layer 160 is left. The thickness of the grown silicon epitaxial layer 160 is different when other techniques for forming the gate oxide 180, such as evaporation, are used.

  Accordingly, as shown in FIGS. 4A and 4B, the inner channel structure is provided by the inner fin structure 400 and includes a plurality of different material layers and has sidewalls extending from the semiconductor substrate 110. The different material layers of the plurality of layers basically include an upper surface located on the opposite side in parallel to the substrate 110 and a side wall surface that is basically perpendicular to the substrate 110. The plurality of different material layers may be provided as a multilayer stack of different semiconductor materials. The outer channel layer is provided by the outer fin structure 410 and is formed on the sidewalls of the inner channel structure. The outer channel layer also has sidewalls and can be formed directly on the sidewalls of different material layers of the inner channel structure. At least a part of the outer channel layer formed on the sidewall of the inner channel structure is deformed. A gate dielectric layer 180 is provided on the sidewalls and top surface of the outer channel layer, with the sidewalls and top surface opposite the outer channel layer. A gate electrode 220 is provided on the sidewall and a portion of the top surface of the gate dielectric layer 180.

  5A and 5B are diagrams schematically illustrating a lattice structure of an inner fin structure 400 and an outer fin structure 410 that provide a channel layer according to some embodiments of the present invention. As shown in FIGS. 5A and 5B, the inner fin structure 400 is basically lattice-matched with the silicon layer at the (100) plane, but is lattice-mismatched with the silicon layer of the outer fin structure at the (110) face. A silicon germanium layer. Accordingly, the outer fin structure 410 providing the channel layer is deformed at a position where the outer fin structure 410 is formed on the silicon germanium layer of the inner fin structure 400, but the outer fin structure 410 is the inner fin structure. It is not deformed at the position formed on the silicon layer of the object 400. As used herein, the terms lattice match and lattice mismatch are related to the difference in the lattice constants of the two materials. If the lattice constant difference is sufficient to induce strain in one of the two layers and at least partially improve carrier mobility as a result of the strain induced in that layer, the difference in lattice constant is It is considered sufficient.

  As shown in FIG. 5B, the outer fin structure that provides the channel layer includes a deformed portion and an undeformed portion as a result of lattice mismatch between the inner fin structure and the outer fin structure. The strain direction is parallel to the width of the gate / channel because the strain is vertical in FIG. 5B and the current goes in or out of the page in the FinFET configuration. Since the silicon germanium layer has a larger lattice constant than the silicon layer, the strain in the silicon layer on the silicon germanium layer is tensile. Ge et al., “Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering” (Eltron Devices Meeting, 2003, IEDM '03 Technical Digest. 3 IE7. Therefore, the tensile strain perpendicular to the current and gate width can improve the performance of both the nMOS and pMOS devices. Therefore, the fin structure according to the embodiment of the present invention is suitable for use in both nMOS and pMOS devices.

  6A to 6E are views illustrating a method of manufacturing an FET including a modified channel layer according to some embodiments of the present invention. As shown in FIG. 6A, alternating layers of silicon germanium 312 and silicon 314 are formed on the silicon substrate 310. Alternate layers of silicon germanium 312 and silicon 314 may be formed by epitaxial growth and have the dimensions described above. Optionally, if a counter-doping implant is performed on the structure of FIG. 6A, a buffer layer (not shown) such as an oxide layer is formed between the silicon substrate 310 and alternating layers of silicon germanium 312 and silicon 314. Can be provided in between. As another alternative, a full ion implantation is performed on the resultant of FIG. 6A, and thus no counterdoping is required.

As shown in FIG. 6B, the inner fin structure 400 of FIGS. 4A and 4B provides silicon germanium 312 and silicon 314 to provide the substrate 110, silicon germanium layer 120, and silicon layer 140 that form the inner fin structure. 6A can be formed by etching the structure of FIG. A silicon nitride layer 322 may be provided on the internal fin structure and used as an etch mask. Further, an oxide layer 320 such as SiO ₂ may be formed on the substrate 110 so as to surround the fin structure. In some embodiments of the present invention, after formation of the fin structure, an oxide layer is formed on the structure, and the oxide corresponding to the fin structure to provide an oxide layer 320. A trench is etched in the layer. The trench is then filled with a silicon nitride layer and then a chemical mechanical polishing process is performed to provide a silicon nitride layer 322 in the trench. As previously described, the silicon nitride layer 322 can serve as a mask during subsequent etchbacks to the oxide layer 320.

  FIG. 6C is a diagram illustrating etch back of the oxide layer 320 to provide the oxide layer 200. As shown in FIG. 6C, the oxide layer 320 can be recessed to the substrate 110, and in some embodiments shown in FIG. 7, it can be recessed beyond the portion of the substrate 110 that forms part of the fin structure. Alternatively, the fin structure may be trimmed or senned so that the width of the fin structure is reduced.

  FIG. 6D illustrates the formation of the silicon layer 160 on the inner fin structure 400. The silicon layer 160 providing the outer fin structure 410 is formed by selective epitaxial growth of a silicon layer on the silicon germanium layer 120 and the silicon layer 140 such that the silicon layer 160 is formed on the sidewalls of the inner fin structure 400. Can be done. The silicon layer 160 may be formed by solid phase epitaxy by forming an amorphous silicon layer on the inner fin structure 400 and then performing annealing to convert the amorphous layer to crystalline.

  FIG. 6E illustrates the formation of the gate oxide 180 and the gate electrode 220. As described above, the gate oxide 180 can be formed by thermal oxidation of the silicon layer 160. The gate electrode 220 can be formed using conventional gate patterning techniques. Optionally, after forming the gate electrode 220, the S / D region can be expanded by selective epitaxial growth within the S / D region.

  In some embodiments of the invention, the gate structure is formed by a damascene process to provide a damascene gate structure. In such an embodiment, the gate is formed in a recess around the fin structure and a chemical mechanical polishing process is performed after the gate material has been fully deposited or the gate material not present in the recess is removed. Other planarization methods can be performed. In this case, it is not necessary to expand the S / D area.

  The preferred embodiments of the present invention have been specifically described above. However, the present invention is not limited to the above-described embodiments, and may vary depending on the technical level of those skilled in the art without departing from the technical idea of the present invention. It is possible to make changes to

  The present invention is applicable to a technical field related to semiconductor elements.

It is sectional drawing which shows the conventional planar FET. It is sectional drawing which shows the conventional ultra-thin body transistor. It is sectional drawing which shows the conventional double gate FET. It is sectional drawing of the semiconductor substrate which shows the conventional method of forming the conventional double gate FinFET. It is sectional drawing of the semiconductor substrate which shows the conventional method of forming the conventional double gate FinFET. It is sectional drawing of the semiconductor substrate which shows the conventional method of forming the conventional double gate FinFET. It is sectional drawing of the semiconductor substrate which shows the conventional method of forming the conventional double gate FinFET. It is sectional drawing of the semiconductor substrate which shows the conventional method of forming the conventional triple gate FinFET. It is sectional drawing of the semiconductor substrate which shows the conventional method of forming the conventional triple gate FinFET. 2 is a cross-sectional view of a FinFET according to some embodiments of the invention. FIG. FIG. 6 is an isometric view of a FinFET channel and gate region according to some embodiments of the present invention. 2 is a plan view of a FinFET according to some embodiments of the present invention. FIG. FIG. 3 is a schematic diagram illustrating a lattice structure with a portion of a FinFET fin according to some embodiments of the present invention. FIG. 3 is a schematic diagram illustrating a lattice structure with a portion of a FinFET fin according to some embodiments of the present invention. It is sectional drawing which shows the manufacturing method of FinFET by some embodiment of this invention. It is sectional drawing which shows the manufacturing method of FinFET by some embodiment of this invention. It is sectional drawing which shows the manufacturing method of FinFET by some embodiment of this invention. It is sectional drawing which shows the manufacturing method of FinFET by some embodiment of this invention. It is sectional drawing which shows the manufacturing method of FinFET by some embodiment of this invention. It is sectional drawing of FinFET by other embodiment of this invention.

Explanation of symbols

110 substrate 120 silicon germanium layer,
140,160 silicon layer,
180 gate dielectric layer,
200 first dielectric layer;
220 gate electrode,
400 internal fin structure,
410 External fin structure.

Claims (65)

  A field effect transistor comprising a channel layer formed on a side wall of a structure formed on a semiconductor substrate, wherein at least a part of the channel layer is deformed in a direction in which the side wall of the structure extends from the semiconductor substrate.   The field effect transistor according to claim 1, wherein the transistor includes a FinFET, the structure includes a fin structure, and the sidewall includes a sidewall of the fin structure.   The field effect transistor according to claim 2, wherein the channel layer includes a silicon epitaxial layer.   The field effect transistor of claim 3, wherein the channel layer is thinner than about 100 inches.   The field effect transistor according to claim 2, wherein the fin structure includes a plurality of different material layers. Each of the plurality of different material layers includes an upper surface on the opposite side of the substrate, which is basically parallel to the substrate, and a sidewall surface that is basically perpendicular to the substrate,
6. The field effect transistor according to claim 5, wherein the channel layer is directly formed on a sidewall surface of the plurality of different material layers.   The field effect transistor of claim 2, wherein the fin structure comprises alternating layers of silicon and silicon germanium.   The field effect transistor according to claim 7, wherein the alternating layer includes an epitaxial layer.   8. The field effect transistor of claim 7, wherein the alternating silicon layers are thinner than about 30 inches.   8. The field effect transistor of claim 7, wherein the silicon germanium layers of the alternating layers are thinner than about 50 inches.   The field effect transistor according to claim 7, wherein the alternating layer comprises one or more silicon layers and one or more silicon germanium layers.   The field effect transistor according to claim 7, wherein an outermost layer of the alternating layers is a silicon germanium layer.   The field effect transistor according to claim 12, wherein a part of the channel layer is directly disposed on the outermost layer of the alternating layer. A gate dielectric formed in the channel layer;
A gate electrode formed on a portion of the gate dielectric;
The field effect transistor according to claim 2, further comprising a source region and a drain region formed on opposite sides of the gate electrode.   The field effect transistor of claim 14, wherein the channel layer comprises a silicon epitaxial layer.   The field effect transistor of claim 15, wherein the source and drain regions comprise a silicon epitaxial layer.   The field effect transistor of claim 14, wherein the fin structure and the source and drain regions include a plurality of different material layers.   The field effect transistor of claim 14, wherein the fin structure and the source and drain regions comprise alternating layers of silicon and silicon germanium.   The field effect transistor of claim 18, wherein the alternating layers comprise epitaxial layers.   The field effect transistor of claim 14, wherein the gate electrode comprises a polysilicon layer.   The fin structure further comprising a first dielectric layer formed on the substrate, the fin structure extending through the first dielectric layer, and the channel layer extending beyond the first dielectric layer. The field effect transistor according to claim 2, wherein the field effect transistor is disposed on a part of the field effect transistor.   23. The fin structure of claim 21, wherein the fin structure includes a portion of the substrate, and the portion of the fin structure provided by the substrate extends beyond the first dielectric layer. Field effect transistor.   22. The fin structure includes a portion of the substrate, and the portion of the fin structure provided by the substrate does not extend beyond the first dielectric layer. Field effect transistor.   The field effect transistor according to claim 2, wherein the substrate comprises a silicon substrate.   15. The field effect transistor according to claim 14, wherein the channel layer includes a portion deformed in a direction parallel to the gate width.   The field effect transistor of claim 14, wherein the gate dielectric and the gate electrode have a damascene structure.   The field effect transistor of claim 2, wherein the channel layer includes a deformed portion and an undeformed portion.   28. The field effect transistor according to claim 27, wherein the deformed portion and the undeformed portion comprise sidewalls of the channel layer. An internal channel structure comprising a plurality of different material layers having sidewalls extending from the semiconductor substrate;
And an external channel layer formed on the sidewall of the internal channel structure and having the sidewall. A gate dielectric layer formed on a sidewall and an upper surface of the outer channel layer, and having a sidewall and an upper surface on the opposite side of the outer channel layer;
A gate electrode formed on a part of the sidewall and upper surface of the gate dielectric layer;
30. The fin field effect transistor of claim 29, further comprising a source region and a drain region disposed on opposite sides of the gate electrode.   The fin field effect transistor according to claim 30, wherein the external channel layer comprises a silicon epitaxial layer. Each of the plurality of different material layers comprises an upper surface that is essentially parallel to the substrate on the opposite side of the substrate and a sidewall surface that is essentially perpendicular to the substrate,
The fin field effect transistor according to claim 30, wherein the channel layer is formed directly on a sidewall surface of the plurality of different material layers.   32. The fin field effect transistor of claim 30, wherein the inner channel structure comprises alternating layers of silicon and silicon germanium.   34. The fin field effect transistor of claim 33, wherein the alternating layers comprise epitaxial layers.   34. The fin field effect transistor of claim 33, wherein the alternating layers comprise one or more silicon layers and one or more silicon germanium layers.   34. The fin field effect transistor according to claim 33, wherein an outermost layer of the alternating layers is a silicon germanium layer.   37. The fin field effect transistor according to claim 36, wherein a part of the channel layer is disposed directly on the outermost layer of the alternating layer.   The fin field effect transistor according to claim 30, wherein the gate electrode comprises a polysilicon layer.   A first dielectric layer formed on the substrate, wherein the inner channel structure extends through the first dielectric layer, and the outer channel layer extends beyond the first dielectric layer. The fin field effect transistor according to claim 30, wherein the fin field effect transistor is disposed on a part of the channel structure.   40. The inner channel structure includes a portion of the substrate, and a portion of the inner channel structure provided by the substrate extends beyond the first dielectric layer. The fin field-effect transistor as described.   40. The inner channel structure includes a portion of the substrate, and a portion of the inner channel structure provided by the substrate does not extend beyond the first dielectric layer. A fin field effect transistor according to 1.   The fin field effect transistor according to claim 30, wherein the substrate comprises a silicon substrate.   31. The fin field effect transistor according to claim 30, wherein the external channel layer includes a portion deformed in a direction parallel to a gate width.   31. The fin field effect transistor of claim 30, wherein the gate dielectric and the gate electrode comprise a damascene structure.   The fin field effect transistor of claim 30, wherein the outer channel layer includes a deformed portion and an undeformed portion.   46. The fin field effect transistor of claim 45, wherein the deformed portion and the undeformed portion comprise sidewalls of the external channel layer. An internal channel structure formed on a semiconductor substrate and comprising a sidewall extending from the substrate and an upper surface opposite the substrate;
An outer channel layer formed on the sidewalls and upper surface of the inner channel structure and having opposite sidewalls and upper surfaces of the inner channel structure, formed on the sidewalls of the inner channel structure. The outer channel layer in which a part of the outer channel layer is deformed;
A gate dielectric layer formed on a sidewall and an upper surface of the outer channel layer, and having a sidewall and an upper surface on the opposite side of the outer channel layer;
A gate electrode formed on a part of the sidewall and upper surface of the gate dielectric layer;
A fin field effect transistor comprising a source region and a drain region disposed on opposite sides of the gate electrode.   48. The fin field effect transistor according to claim 47, wherein the external channel layer comprises a silicon epitaxial layer.   48. The fin field effect transistor of claim 47, wherein the inner channel structure comprises a plurality of different material layers. Each of the plurality of different material layers comprises an upper surface that is essentially parallel to the substrate on the opposite side of the substrate and a sidewall surface that is essentially perpendicular to the substrate,
50. The fin field effect transistor of claim 49, wherein the external channel layer is directly formed on a sidewall surface of the plurality of different material layers.   48. The fin field effect transistor of claim 47, wherein the inner channel structure comprises alternating layers of silicon and silicon germanium.   52. The fin field effect transistor of claim 51, wherein the alternating layers comprise epitaxial layers.   52. The fin field effect transistor of claim 51, wherein the alternating layers comprise one or more silicon layers and one or more silicon germanium layers.   52. The fin field effect transistor according to claim 51, wherein an outermost layer of the alternating layers is a silicon germanium layer.   55. The fin field effect transistor according to claim 54, wherein a part of the channel layer is disposed directly on the outermost layer of the alternating layer.   48. The fin field effect transistor according to claim 47, wherein the gate electrode comprises a polysilicon layer.   A first dielectric layer formed on the substrate, wherein the inner channel structure extends through the first dielectric layer, and the outer channel layer extends beyond the first dielectric layer. 48. The fin field effect transistor according to claim 47, wherein the fin field effect transistor is disposed on a part of the channel structure.   58. The inner channel structure includes a portion of the substrate, and a portion of the inner channel structure provided by the substrate extends beyond the first dielectric layer. The fin field-effect transistor as described.   58. The inner channel structure includes a portion of the substrate, and a portion of the inner channel structure provided by the substrate does not extend beyond the first dielectric layer. A fin field effect transistor according to 1.   48. The fin field effect transistor of claim 47, wherein the substrate comprises a silicon substrate.   48. The fin field effect transistor according to claim 47, wherein the outer channel layer includes a portion deformed in a direction parallel to a gate width.   48. The fin field effect transistor of claim 47, wherein the gate dielectric and the gate electrode comprise a damascene structure.   48. The fin field effect transistor of claim 47, wherein the outer channel layer includes a deformed portion and an undeformed portion.   64. The fin field effect transistor of claim 63, wherein the deformed portion and the undeformed portion comprise sidewalls of the external channel layer.   Forming a channel layer on a side wall of the structure on the semiconductor substrate, the channel layer including a portion at least deformed in a direction in which the side wall of the structure extends from the semiconductor substrate. Effect transistor manufacturing method.

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