JP2006090727A - On-chip logic analyzer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein the use of an externally connected logic analyzer has been a factor causing a memory capacity shortage when status values in an LSI are recorded and making debugging work inefficient. <P>SOLUTION: In the case where waveform data of monitor signals outputs different status values, memory addresses are counted up, and its status values is written in a memory 5. In the case of outputting continuous and identical status values, the status values are compressed and processed and a count value of the number of repetitions of the identical data is superposed on a count value of the number of items of data having different values and recorded. While a trigger is not generated in waveform data, memory addresses and memory data are repeatedly overwritten in memory effective addresses. When a trigger is generated, a counter of a count signal generating circuit 13 is decremented. When the counter is zeroized, a memory writing operation is halted to report a notice of a status of a signal of completion. A shift is made to memory read of data stored in the memory on the basis of information on the status. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention is provided with a logic analyzer function in an LSI chip in order to improve the efficiency of LSI evaluation debugging in a breadboard evaluation environment and a field test environment for small devices.

A conventional LSI chip debugging operation will be described with reference to the drawings. As shown in FIG. 14, the logic analyzer 141 connected to the outside reads out the data output to the debugging observation terminal (monitor terminal) of the LSI chip on the breadboard and performs debugging.
However, although the monitor terminal can be easily connected on a breadboard, it is extremely difficult to connect the monitor terminal in the case of a small device, and it is difficult to acquire waveform data in a field test.
In addition, for example, in order to debug an LSI or analyze a failure thereof, it is required to continuously grasp the state value inside the LSI with a logic analyzer 141 connected to the outside. It is also necessary to solve the cause of failure while analyzing. However, the degree of integration of LSIs in recent years has been further improved, and the amount of data to be collected by the tracer has been greatly increased accordingly. Therefore, there is a problem in that trace data exceeding the capacity of the memory to be recorded concentrates and an incapable analysis state is caused due to a lack of data capacity.
Further, when the same value is repeated for the trace data, there is a problem that processing of the trace data suitable for characteristic evaluation cannot be performed unless data compression processing is performed.
Furthermore, since the data acquired by the logic analyzer connected to the outside cannot be subjected to data compression processing, there is a problem that a great deal of labor must be spent processing the data when the same value is repeated.

  Therefore, prior art for incorporating a data trace function and a debug function into an LSI for the purpose of solving such problems is disclosed in Japanese Unexamined Patent Application Publication Nos. 2002-24201 “Semiconductor Integrated Circuit” and Japanese Unexamined Patent Application Publication No. 08-63374 “Trace Function”. It is disclosed by “built-in LSI” or the like.

Japanese Patent Laid-Open No. 2002-24201 Japanese Patent Laid-Open No. 08-63374 JP 2001-175510 A

As described above, when using a logic analyzer with an external connection in a breadboard evaluation environment, it is not possible to provide sufficient information to solve the problem, such as insufficient memory capacity when the state value inside the LSI is recorded Brought about. In addition, it is impossible to obtain waveform data in field tests even with small devices that do not have a monitor terminal, and observation data processing suitable for characteristic evaluation is not performed, leading to inefficiency in debugging work There was a point.

Since the data compression method of the on-chip logic analyzer circuit is for the purpose of efficiently recording only the data necessary for debugging in the memory and reducing unnecessary data accumulation, the signal waveform is the same as shown in FIG. There are an overwhelming number of cases where values occur continuously. In such a case, waveform data for a longer time can be stored in the same memory capacity by storing the number of repetitions than storing all the data as it is.
An object of the present invention is to provide a function in an LSI chip in order to improve the efficiency of LSI evaluation debugging in a breadboard evaluation environment and in a field test environment of a small device, so that the small device does not have a monitor terminal in a field test. However, an object is to provide an on-chip logic analyzer that enables trace of waveform data of the built-in LSI.
Another object of the present invention is to debug LSI design in comparison with the prior art, which can collect only data necessary for solving problems and can process observation data suitable for characteristic evaluation. The object is to provide an on-chip logic analyzer that can greatly improve the efficiency.

In view of the above problems, the on-chip logic analyzer of the present invention includes a register group initial setting unit that performs initial setting of a register group according to an instruction from the central processing unit, and a read permission or a read permission set in the register group initial setting unit. A data load signal generating means for outputting a START signal or an END signal based on the write permission, and data initialized by the register group initial setting means are loaded, and a ½ cycle delay signal of the MON signal given from the outside MON latch circuit that generates and outputs together with the MON signal, and detects waveform data that matches a preset value for each target register of the register group, and is based on a 1/2 cycle delay signal of the MON signal Generated by a trigger generating means for generating a trigger signal and the MON signal given from the outside and the MON latch circuit. If both signals are at the same level, the EQU signal is "1" level, and the CLR signal is derived from the 1 cycle delay signal of the EQU signal and the inverted signal of the EQU signal. The control signal generating means for generating and outputting the STOP signal as the "1" level from the 1 cycle delay signal and the EQU signal at the 1 "level and the data initialized by the register group initial setting means are loaded. At the same time, the counter is decremented based on the trigger signal, and when the counter value is not “0”, the COUNT_NZ signal is output. When the counter reaches “0”, the COUNT_NZ signal is stopped to indicate the end of the memory writing. Count signal generating means for notifying the register group initial setting means of status information, and loading data initialized by the register group initial setting means In addition, the RUN signal generating means for generating a RUN signal indicating the number of repetitions of the same data based on the COUNT_NZ signal, the EQU signal, and the START signal and the data initialized by the register group initial setting means are loaded, LENGTH signal generating means for generating a LENGTH signal indicating the total number of data whose values have changed alternately within the specified number of times based on the COUNT_NZ signal, the EQU signal, the START signal, and the CLR signal, and the register group initial setting If the waveform signal data collected is loaded in the state where the value changes alternately and frequently less than the specified number of times, the memory address is incremented by 1 count and the data is stored in the memory. If the collected waveform data is “a state where the same value continues for a certain number of times”, the same data is counted repeatedly. And a memory address generating means that repeats memory writing while not receiving the STOP signal and within the effective address range of the memory, and superimposing the count value of the number of data of different values on the compressed observation data and writing to the memory, and the center A logic analyzer comprising memory data output generation means for outputting stored data from the memory by designating a read address of the memory based on an instruction from a processing device is configured on one LSI chip.

In the present invention, by using a logic analyzer function in an LSI chip and using it, it is possible to perform data compression processing for continuous writing of the same repetitive data, thereby improving the efficiency of use of data stored in the memory. There is an effect to improve.
Further, by providing a data processing function suitable for performing the characteristic evaluation, an effect of improving the debugging efficiency is achieved. Furthermore, even with a small device that does not have a monitor terminal, it is possible to acquire waveform data in field tests, coupled with the fact that an external logic analyzer is not required and the hardware itself can be miniaturized, greatly increasing the overall configuration. There is an effect of downsizing.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. 1 to 13 are configuration diagrams showing an embodiment of the present invention.

FIG. 1 is a configuration block diagram showing an LSI chip and a breadboard on which the on-chip logic analyzer of the present invention is mounted. In the LSI chip (the part surrounded by the dotted line in the figure), the monitor signal in the chip obtained via the SEL (selector) circuit 2 is input to the logic analyzer circuit 1, and the breadboard and the small size are obtained from the terminal 3 such as a PC. The CPU 4 mounted on the device is instructed to execute the evaluation program, and the CPU 4 performs data processing, whereby the CPU 4 accesses the register group initial setting circuit 11 incorporated in the logic analyzer circuit 1. Based on this access, the waveform data flowing in the monitor signal is taken into the SRAM memory 5 and the acquired data is transferred to the terminal 3 through the CPU 4 and displayed after being processed into an appropriate format.
FIG. 2 is a detailed configuration block diagram of the logic analyzer circuit 1 in the LSI chip of the present embodiment. Hereinafter, a series of waveform signal tracing operations will be described in detail with reference to FIG.
First, the CPU 4 accesses the register group initial setting circuit 11 built in the logic analyzer 1 to initialize the register group. Finally, when the CPU 4 performs write access to the register WR_ENABLE, the initialized data is loaded to the memory address generation circuit 12, the COUNT signal generation circuit 13, the RUN signal generation circuit 14, and the LENGTH signal generation circuit 15, respectively. Is done. Further, when the CPU 4 performs write access to the register WR_ENABLE, the COUNT_NZ signal generated by the COUNT signal generation circuit 13 becomes “1”. As a result, both the MEMWEB signal and MEMCSB signal of the memory 5 become “0”, and the waveform signal acquisition mode operation is started, and the address and data write operations are performed on the memory 5.
At this time, if the waveform data flowing in the monitor signal is in the “value changes” state shown in FIG. 15, the memory address generation circuit 12 writes the data to the memory 5 while counting up the memory address. Conversely, if the waveform data is in the “same value continuous” state, the “same data repetition count value” and “count value of the number of data with different values” output from the RUN signal generation circuit 14 and the LENGTH signal generation circuit 15 respectively. Is compressed into observation data and written to the memory 5. While the trigger is not generated, the memory 5 is overwritten repeatedly within the effective address of the memory 5.
The trigger (TRIG) generated by the TRIG generation circuit 16 is effective only for the first trigger after the start of the waveform signal collection operation, and is generated by detecting the same waveform data as the value set in the TARGET register. When TRIG occurs, the counter of the COUNT signal generation circuit 13 is decremented. When the counter reaches “0”, the memory accumulation operation stops, and the COUNT signal generation circuit 13 displays the status information of the memory write end signal as the register group initial setting circuit 11. Notify Based on the status information, the CPU 4 shifts to the memory read mode of the data stored in the memory 5 through the CPU 4.
The CPU 4 shifts to the memory read mode by enabling RD_ENABLE of the register group initial setting circuit 11. The memory storage data is output as the storage data MEMBDI (31: 0) from the memory 5 by designating the memory read address to the CPU 4, transferred to the terminal 3 via the CPU 4, and waveform data suitable for characteristic evaluation. Is displayed after being processed.
FIG. 3 is a detailed block diagram of the MON latch circuit 17. If all the values set in the PHASE register of the register group initial setting circuit 11 are “0”, the debug monitor terminal MON [31: 0] signal of the LSI chip to be inspected passes through the selector SEL34 through. When the clock of F / F32 rises, 1T cycle delay CURR_MON [31: 0] is output for the MON [31: 0] signal of memory 5, and the CURR_MON [31: 0] signal of F / F33 rises the clock. 1T cycle delay OLD_MON [31: 0] is output. Normally, the waveform data flowing in the monitor signal is operated without using the PHASE register, but the operation guarantee backup circuit takes into account the circuit delay and wiring delay of the monitor signal output from each block in the LSI chip. As a result, the PHASE register that gives a half-cycle delay of the MON [31: 0] signal can also be used. Depending on the value set in the PHASE register, a half-cycle delay of the MON [31: 0] signal is provided for each bit of the 32-bit PHASE [31: 0].
Next, a detailed block diagram of the TRIG generation circuit 16 is shown in FIG. The trigger signal TRIG is generated by CURR_MON [31: 0] generated by the MON latch circuit 17 and TARGET [31: 0] and MASK [31: 0] set by the TARGET register and MASK register of the register group initial setting circuit 11, respectively. Is generated. This TRIG is a signal generated by a match between the value stored in the TARGET register and CURR_MON [31: 0], and the value is compared only at the bit position where the value stored in the MASK register is “1”. . FIG. 5 shows the relationship among CURR_MON [31: 0], TARGET [31: 0], and MASK [31: 0]. The TRIG generated by the trigger signal (TRIG) generation circuit 16 is also used as a start signal for the decrement processing of the COUNT register (REG_COUNT) in the COUNT signal generation circuit 13 of FIG. 8 described later.
FIG. 6 is a detailed block diagram of the control signal generation circuit 18. There are three types of control signals: EQU signal, CLR signal, and STOP signal. The generation process and operation of each signal will be described in order. First, the EQU signal is output as EQU signal level "1" when CURR_MON [31: 0] and OLD_MON [31: 0] generated by the MON latch circuit 17 are equal. Along with this, in the RUN register (REG_RUN) in the RUN signal generation circuit 14, when the count enable (COUNT_NZ) is valid and the EQU signal is “1” level, the clock rises and the count operation of the same data repeat count is started. . Conversely, if CURR_MON [31: 0] and OLD_MON [31: 0] are different, the EQU signal is output as “0”. In a RUN register (REG_RUN), which will be described later, when the count enable (COUNT_NZ) is valid and the EQU signal is at “0” level, the clock rises and the number of repetitions of the same data is reset to the initial value “0”. The EQU signal is also used for a LENGTH (REG_LENGTH) register of the LENGTH signal generation circuit 15 which will be described later. In the LENGTH register (REG_LENGTH), when the count enable (COUNT_NZ) is valid and the EQU signal is “1” level, the clock holds the count value before rising. Further, in the LENGTH register (REG_LENGTH), when the count enable (COUNT_NZ) is valid and the EQU signal is at the “0” level, the clock rises and starts counting the number of data having different values.
Next, the CLR (clear) signal will be described. The CLR signal is a 1T-level 1T-width signal generated by using an AND gate for the 1T cycle delay signal of the EQU signal and the inverted signal of the EQU signal, and not (EQU) at the rising edge of the F / F 62 clock. . This CLR signal is used for the LENGTH (REG_LENGTH) register in the LENGTH signal generation circuit 15 in FIG. It rises and restores the LENGTH register from the state in which the count value was held to the initial value “0” state.
Next, the STOP signal will be described. This signal is generated by using an AND gate for the 1T cycle delay signal of the EQU signal and the EQU signal at the rising edge of the F / F 62 clock. This STOP signal is also a signal used in the COUNT register (REG_COUNT) of the COUNT signal generation circuit 13 of FIG. 8 and the pointer register (REG_PTR) of the memory address signal generation circuit 12 of FIG.
In the COUNT register (REG_COUNT) of FIG. 8, when the count enable (COUNT_EN) is valid and the 1T cycle delay signal of the STOP signal due to the rising edge of the F / F 82 is “1” level, the COUNT register is turned on at the rising edge of the clock. Holds the decremented count data. On the other hand, when the count enable (COUNT_EN) is valid and the 1T cycle delay signal of the STOP signal due to the rising edge of the F / F 82 is “0” level, the COUNT register starts the count decrement operation at the rising edge of the clock. . Further, in the pointer register of FIG. 11, when the count enable (COUNT_NZ) is valid and the STOP signal is “1” level, the address count data is held at the rising edge of the clock. On the other hand, when the count enable (COUNT_NZ) is valid and the STOP signal is “0” level, the address count count-up operation is started at the rising edge of the clock.
FIG. 7 is a block diagram showing a detailed configuration of the data load signal generation circuit (also serves as a write end signal generation circuit) 19. The START signal generated from this circuit is initialized in the memory address generation circuit 12, the COUNT signal generation circuit 13, the RUN signal generation circuit 14, and the LENGTH signal generation circuit 15 when the CPU 4 performs write access to the register WR_ENABLE. This is a clock 1T-wide signal generated to load the generated data. When START becomes valid, the COUNT_NZ signal of the COUNT signal generation circuit 13 becomes “1”, so that the MEMWEB signal and MEMCSB signal of the memory become “0”, the waveform data collection operation is started, and the address and data to the memory 5 are started. The write operation starts. END_FLG also becomes a set condition by performing write access to the register WR_ENABLE, and becomes “1” at the rising edge of the clock. This END_FLG is used as a MEMWR_END generation condition, which is a write end signal for the memory 5. The MEMWR_END generation condition is that the COUNT_NZ signal becomes “0” only when writing to the memory 5 is completed, and “1” is output as MEMWR_END by using the following logical expression.
MEMWR_END = END_FLG * not (COUNT_NZ)
MEMWR_END reflects the status value of “1” to the read register on the CPU I / F, and notifies the register group initial setting circuit 11 of the status of the memory write end signal. Based on this status information, the CPU 4 shifts to memory read of stored data in the memory 5 through the CPU 4. The memory read becomes the memory read mode by enabling the register RD_ENABLE from the CPU 4. Also, by enabling the register RD_ENABLE, the reset condition of END_FLG is established, and becomes “0” at the rising edge of the clock.
As described above, FIG. 8 is a block diagram showing a detailed configuration of the COUNT signal generation circuit 13. The COUNT register (REG_COUNT) indicates the number of data accumulated in the memory after the trigger arrives. Prior to data collection, the COUNT number stored in the memory after the trigger has arrived is set in the COUNT register from the CPU. The START generated by the data load signal generation circuit 19 is used to load the initial setting of the COUNT signal generation circuit 13 (the number of COUNT accumulated in the memory after the trigger arrives at the COUNT register). In the COUNT register, the clock rises when START is at the “1” level of the clock 1T width, and the COUNT register (REG_COUNT) is loaded with the initial setting value, and at the same time, the CMP circuit in the COUNT signal generation circuit 13 has the initial value “0”. "And the setting data of the COUNT register (REG_COUNT) are compared. If the data values do not match as a result of the comparison, the COUNT_NZ_TMP1 signal outputs “0” level. An inverter is connected immediately before the output of the COUNT_NZ_TMP1 signal, and the COUNT_NZ signal becomes “1” level by passing through the inverter. The COUNT_NZ signal is also generated in the RUN register (REG_RUN) in the RUN signal generation circuit 14 in FIG. 9, the LENGTH register (REG_LENGTH) in the LENGTH signal generation circuit 15 in FIG. 10, and the memory address signal generation circuit 12 in FIG. Also used as a count enable signal for each of the pointer registers (REG_PTR). While the COUNT_NZ signal is kept at “1” level, the count operation is valid in both the LENGTH register and the pointer register. The COUNT_NZ signal is also used for memory write operations. While the COUNT_NZ signal is held at “1” level, the MEMWEB signal and MEMCSB signal necessary for memory write are both set to “0” level, waveform acquisition operation is started, and address and data memory write operation is executed. Is done.
When the TRIG signal generated by the trigger signal (TRIG) generation circuit 16 is received after the COUNT_NZ signal becomes “1” level, the COUNT_EN signal becomes “1” level. The COUNT signal generation circuit 13 is provided with a circuit that holds the level of the TRIG signal every time the clock of the F / F 87 rises. The COUNT_EN signal holds the “1” level until the COUNT_NZ signal becomes the “0” level. to continue. The COUNT_EN signal is also used as an enable signal for the count decrement of the COUNT register (REG_COUNT). The count decrement is valid while the COUNT_EN signal holds “1” level, and the COUNT register (REG_COUNT) is “0”. The count decrement operation is executed until 'is reached. After the COUNT register (REG_COUNT) becomes “0”, the CMP circuit 85 in the COUNT signal generation circuit 13 compares the initial value “0” with the COUNT register (REG_COUNT) “0”, and the data values match. In this case, the COUNT_NZ_TMP1 signal is output at “1” level. At this time, as described above, the COUNT_NZ signal becomes “0” level in the COUNT signal generation circuit 13 (see FIG. 9), so that the subtraction count enable signal (COUNT_EN) of the COUNT register (REG_COUNT) also becomes “0” level. Update of the count decrement operation of the COUNT register (REG_COUNT) is stopped.
If the 1T cycle delay signal of the STOP signal is “1” level at the rising edge of the F / F 82 when the COUNT_EN signal output from the COUNT signal generation circuit 13 holds “1” level, the COUNT register Count decrement count data is held at the rising edge of the clock. Conversely, if the 1T cycle delay signal of the STOP signal is at “0” level at the rising edge of the F / F 82 clock, the count decrement operation is performed at the rising edge of the clock. COUNT_RD [9: 0] output from the COUNT register (REG_COUNT) is a signal connected to the read register in order to recognize the state of the COUNT register from the CPU I / F.
FIG. 9 is a block diagram showing a detailed configuration of the RUN signal generation circuit 14. Before data collection, the CPU 4 sets an initial value “0” in the RUN register (REG_RUN). When START is “1” level, the initial setting value is loaded to the RUN register (REG_RUN) at the rising edge of the clock. At the same time, the COUNT_NZ signal (see FIG. 8) becomes “1” level. The COUNT_NZ signal is also used as a count enable signal of the RUN register (REG_RUN). After the COUNT register (REG_COUNT) of the COUNT signal generation circuit 13 becomes “0”, the COUNT_NZ signal becomes “0” level. As a result, the update of the repetition count of the same data in the RUN register (REG_RUN) is stopped. Similarly, in the RUN register (REG_RUN), when the count enable (COUNT_NZ) is “1” level and the EQU signal is “1” level, the counting operation of the same data repetition count is selected in both SEL91 and SEL92. As a result, the RUN register (REG_RUN) counts the number of times the same data is repeated at the rising edge of the clock. When the count enable (COUNT_NZ) is “1” level and the EQU signal is “0” level, “0” level is selected in SEL92, so the same data stored in the RUN register (REG_RUN) at the rising edge of the clock Is repeated to the initial value “0”.
Furthermore, in the RUN signal generation circuit 14, since the value that can count the number of repetitions of the same data is set to 'F / FF / Fh', the CMP circuit when the EQU signal continues to be “1” level with 65535 clocks or more. The output signal 94 becomes “1” level, the state value “F / FF / Fh” of the RUN register (REG_RUN) is selected by the SEL 91, and “F / FF / Fh” is held as the RUN register (REG_RUN). RUN [15: 0] output from the RUN register (REG_RUN) is a signal connected to the read register in order to know the state of the RUN register from the CPU I / F, and the memory data output generation of FIG. This signal is connected to the circuit 20.
FIG. 10 shows a detailed configuration of the LENGTH signal generation circuit 15. Before data collection, the CPU 4 sets an initial value “0” to the LENGTH register (REG_LENGTH). In the LENGTH register, when START is at the “1” level of the clock 1T width, the LENGTH register (REG_LENGTH) is loaded with the initial setting value at the rising edge of the clock, and at the same time, the COUNT_NZ signal becomes the “1” level. The COUNT_NZ signal is also used as a count enable signal of the LENGTH register (REG_LENGTH). After the COUNT register (REG_COUNT) of the COUNT signal generation circuit 13 becomes “0”, the count enable signal (COUNT_NZ) of the LENGTH register (REG_LENGTH) becomes “0” level because the COUNT_NZ signal becomes “0” level. The updating of the count indicating the number of data having different values in the LENGTH register (REG_LENGTH) is stopped. In addition, in the LENGTH register (REG_LENGTH), when the count enable (COUNT_NZ) is “1” level and the EQU signal is “0” level, the LENGTH register state value +1 is selected in the SEL 101. At this time, when the CLR signal is at the “0” level, the LENGTH register state value + 1 is selected also in the SEL 102, and this LENGTH register (REG_LENGTH) performs a count-up operation at the rising edge of the clock. Further, in the LENGTH register (REG_LENGTH), when the count enable (COUNT_NZ) is “1” level and the EQU signal is also “1” level, the LENGTH register state value holding operation is selected in SEL101. At this time, if the CLR signal is at the “0” level, the LENGTH register state is retained by selecting the state value retaining operation of the LENGTH register also in the SEL 102. In the LENGTH register (REG_LENGTH), when the count enable (COUNT_NZ) is “1” level and the CLR signal is also “1” level, “0” level is selected in the SEL 102. At this time, the selection state of the SEL 101 by the EQU signal is ignored, and the LENGTH register is returned to the initial value “0” state from the state where the clock rises and holds the count value. Further, LENGTH [9: 0] output from the LENGTH register (REG_LENGTH) is a signal connected to the read register to know the state of the LENGTH register from the CPU I / F, and the memory data output generation circuit of FIG. It is also a signal to connect to.
FIG. 11 shows a detailed block diagram of the memory address signal generation circuit 12. Before data collection, the CPU 4 sets a memory address initial setting value in the pointer register (REG_PTR). In the pointer register (REG_PTR), when START is at a “1” level of the clock 1T width, the initial value is loaded to the pointer register (REG_PTR) at the rising edge of the clock, and at the same time, the COUNT_NZ signal becomes the “1” level. The COUNT_NZ signal is also used as a count enable signal of the pointer register (REG_PTR). After the COUNT register (REG_COUNT) of the COUNT signal generation circuit 13 becomes “0”, the COUNT_NZ signal becomes “0” level. Thus, the count enable signal (COUNT_NZ) of the pointer register (REG_PTR) becomes “0”, the update of the address count UP operation of the pointer register (REG_PTR) is stopped, and the memory address of the last stored data is stored. As a function of the STOP signal, when the count enable (COUNT_NZ) is “1” level and the STOP signal is “1” level, the pointer register (REG_PTR) holds the address count data at the rising edge of the clock. In the pointer register (REG_PTR), when the count enable (COUNT_NZ) is “1” level and the STOP signal is “0” level, the address count is counted up by the rising edge of the clock. Furthermore, the memory address MEM_AB [9: 0] to be output to the memory outputs the state value of the pointer register (REG_PTR) through when the STOP signal is “1” level, and pointer register when the STOP signal is “0” level By outputting the (REG_PTR) state value +1, the write address value is adjusted in the memory when the same data is repeated (when the CLR signal is “1” level state). PTR_RD [9: 0] output from the pointer register (REG_PTR) is a signal connected to the read register in order to know the state of the pointer register from the CPU I / F.
Next, the operation of the memory data output generation circuit 20 will be described with reference to FIG. When the EQU signal is “1” level, the same data repetition count value RUN [15: 0] generated by the RUN register and LENGTH register is used as the write data to the memory. Output as MEMDBO. This is a function for outputting, as memory data, the result of compression processing of the count value of the same data repetition count and the count value of the number of data having different values. When the EQU signal is “0” level, the current value of the MON signal (CURR_MON) is output to MEMDBO.

FIG. 13 shows the operation waveform of each signal in the waveform acquisition mode. In the waveform collection operation, the register group initial setting circuit 11 in the logic analyzer 1 starts write access from the CPU 4 to set the initial settings necessary for waveform collection in the register, and finally, the CPU 4 performs write access to the register WR_ENABLE. As a result, the logic analyzer 1 of the present invention starts the waveform collection operation.
When the CPU 4 performs write access to the register WR_ENABLE, the memory address generation circuit 12, the COUNT signal generation circuit 13, the RUN signal generation circuit 14, and the LENGTH signal generation circuit 15 are initially loaded with data. The COUNT_NZ signal generated by the COUNT signal generation circuit 13 becomes “1”, and the MEMWEB signal and MEMCSB signal of the memory become “0” along with this, so that the waveform collection mode operation is started and the address and data memory Writing begins. If the waveform data flowing in the monitor signal is data of different status values, the data is written to the memory while counting up the memory address, and if it is continuous data of the same status value, the RUN signal generation circuit 14 and LENGTH signal generation circuit 15 The same data repetition count value output from each circuit and the count value of the number of data having different values are compressed into observation processing data suitable for characteristic evaluation and written to the memory. While the trigger does not occur, the address and data are overwritten many times in the effective address of the memory. COUNT at which the first trigger is generated after the operation starts is decremented, and the operation stops when COUNT becomes “0”. While COUNT is not “0”, data is always stored. By setting the value of COUNT to about half of the memory size, the time before and after the trigger can be set to the same time. In the waveform acquisition mode, only the first trigger after the start of operation is valid for one waveform acquisition operation.
After waveform collection, the status that informs the end of memory writing in the read register MEMWR_END remains. Based on this status information, the CPU 4 shifts to memory read of stored data. The method for expanding the stored data from the memory 5 is that if the read register PTR_RD is read and the address written at the end of the memory is found and then LENGTH_RD is read, the memory 5 can be traced to the data compressed address. it can. If the address where the data compression has been performed can be found, the stored data can be developed as the original waveform data by following the previous address in order.
FIG. 16 is a diagram showing an example of a state of storage in a memory subjected to logic repetitive data compression processing using the waveform acquisition mode. (A) When a signal like the example of input data is inputted, the value first changes. During this time, 32 bits (D0, D1, D2, D3) are stored in the memory as they are. Since the value has changed until the first data of D4, it is stored in the memory as it is. From the second data of D4, the number N of changed values is stored in the lower 16 bits, and the value obtained by subtracting 2 from the number M of D4 (M-2) is converted into the upper 16 bits, and the same address is set. Saved. When D4 continues and D5 comes, store this value as it is at the next address, and as before, while the value is changing (D5, D6, D7, first D8) When the value is repeated and the value repeats, the number of changed data and the number of repeats are stored in the memory. By storing data in this way, the data to be stored can be compressed. Use the pointer register (PTR) that indicates the address of the last written memory and the register that counts the number of changed values and the number of repetitions (LENGTH, RUN, details will be described later). By tracing to the address, the stored waveform data can be expanded to the original waveform data. In the example of FIG. 16, the value of address 10 is read, and the address obtained by subtracting L + 2 from this address becomes the address containing the previous count value. Similarly, N + 2 should be subtracted from the address at address 5. By providing such a data compression processing mechanism, it is possible to process observation data suitable for characteristic evaluation.

1 is a diagram illustrating an embodiment of the present invention, and is a block diagram illustrating an LSI chip and a breadboard on which an on-chip logic analyzer is mounted. 1 is an overall block diagram showing a detailed configuration of a logic analyzer circuit 1 in an LSI chip of an embodiment. 3 is a partial block diagram showing a configuration of a MON latch circuit 17 in the LSI chip of the present embodiment. FIG. It is a partial block diagram which shows the structure of the TRIG generation circuit 16 in the LSI chip of this embodiment. FIG. 6 is a diagram illustrating a relationship among signals CURR_MON [31: 0], TARGET [31: 0], and MASK [31: 0] generated by the TRIG generation circuit 16. 3 is a partial block diagram showing a configuration of a control signal generation circuit 18 in the LSI chip of the present embodiment. FIG. 3 is a partial block diagram showing a configuration of a data load signal generation circuit (also serves as a write end signal generation circuit) 19 in the LSI chip of the present embodiment. FIG. It is a partial block diagram which shows the structure of the COUNT signal generation circuit 13 in the LSI chip of this embodiment. 3 is a partial block diagram showing a configuration of a RUN signal generation circuit 14 in the LSI chip of the present embodiment. FIG. 3 is a partial block diagram showing a configuration of a LENGTH signal generation circuit 15 in the LSI chip of the present embodiment. FIG. 3 is a partial block diagram showing a configuration of a memory address signal generation circuit 12 in the LSI chip of the present embodiment. FIG. 3 is a partial block diagram showing a configuration of a memory data output generation circuit 20 in the LSI chip of the present embodiment. FIG. It is a chart which shows the operation waveform of each signal in waveform collection mode. It is the figure which showed the prior art which debugs an LSI chip using an external logic analyzer. It is the figure which showed an example of the signal waveform in a logic analyzer. It is the figure which showed the example of the storage state to the memory which carried out the logic repetition data compression process using the waveform acquisition mode.

Explanation of symbols

1 Logic Analyzer 2 Selector 3 Terminal (PC)
4 CPU
5 SRAM (memory)
11 register group initial setting circuit 12 memory address generation circuit 13 COUNT signal generation circuit 14 RUN signal generation circuit 15 LENGTH signal generation circuit 16 TRIG generation circuit 17 MON latch 18 control signal generation circuit 19 data load signal generation circuit (also as write end signal) Generation circuit)
20 Memory data output generation circuit

Claims (4)

A semiconductor integrated circuit characterized in that a logic analyzer function is provided on an LSI chip in order to improve debugging efficiency of LSI evaluation in a breadboard evaluation environment and a field test environment for small devices. 2. The semiconductor integrated circuit according to claim 1, wherein the waveform data of the built-in LSI is displayed on an external terminal even in a small device having no monitor terminal in the field test. A circuit that processes waveform data suitable for characteristic evaluation is provided, and when the waveform data flowing in the monitor signal is data in which different state values are repeated alternately and frequently, the data of the different state values is recorded. 3. When the waveform data is continuous data having the same state value, the same state value data is compressed and stored together with supplementary information related to the compression processing. Semiconductor integrated circuit. A register group initial setting means for initial setting of the register group according to an instruction of the central processing unit;
A data load signal generating means for outputting a START signal or an END signal based on read permission or write permission set in the register group initial setting means;
A MON latch circuit that loads data initialized by the register group initial setting means, generates a ½ cycle delay signal of a MON signal given from the outside, and outputs the signal together with the MON signal;
Trigger generating means for detecting waveform data matching a preset value for each target register of the register group, and generating a trigger signal based on a 1/2 cycle delay signal of the MON signal;
Comparing the externally supplied MON signal and the 1/2 cycle delayed MON signal generated by the MON latch circuit, when both signals are at the same level, the EQU signal is set to "1" level, and the EQU signal Control signal generating means for generating and outputting the CLR signal from the 1 cycle delay signal and the inverted signal of the EQU signal at the "1" level, and the STOP signal from the 1 cycle delay signal and the EQU signal as the "1" level, respectively. ,
The data initialized by the register group initial setting means is loaded, the counter is decremented based on the trigger signal, and the COUNT_NZ signal is output when the counter value is not “0”, and the counter is set to “0”. Then, the count signal generating means for stopping the COUNT_NZ signal and notifying the register group initial setting means of status information indicating the end of memory writing,
RUN signal generating means for loading the data initialized by the register group initial setting means and generating a RUN signal indicating the number of repetitions of the same data based on the COUNT_NZ signal, the EQU signal, and the START signal, and the register LENGTH indicating the total number of data whose values are alternately changed within the specified number of times based on the COUNT_NZ signal, the EQU signal, the START signal, and the CLR signal while loading the data initialized by the group initial setting means LENGTH signal generation means for generating a signal;
The data initialized by the register group initial setting means is loaded, and if the collected waveform signal data is “a state where the value changes alternately and frequently less than the specified number of times”, the memory address is incremented by 1 count. While the data is written to the memory, if the collected waveform data is “a state in which the same value continues for a certain number of times”, the same data repeat count count value and the count value of the number of different data values are superimposed on the compressed observation data Memory address generation means for writing to the memory and repeating the memory writing while not receiving the STOP signal and within the effective address range of the memory;
A logic analyzer constituted by a memory data output generation means for outputting stored data from the memory by designating a read address of the memory based on an instruction from the central processing unit is provided on the chip. On-chip logic analyzer.

Images