JP2006085868A - Rewrite restriction method and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability of data by surely preventing rewriting in an area where the permissible number of rewriting times of a nonvolatile memory is exceeded, to effectively use the rewriting of the entire nonvolatile memory, and to make decision of an error in a writing process within a short period of time. <P>SOLUTION: In the rewrite limiting method of the electrically erasable nonvolatile memory, signals inhibiting the rewriting in the area when the number of rewriting times reaches a predetermined value are outputted to the respective areas of the nonvolatile memory. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a rewrite restriction method and a semiconductor device, and more particularly to a restriction circuit for restricting rewriting of an electrically erasable nonvolatile memory and a semiconductor device having a rewrite restriction function.

  In general, a nonvolatile memory has a limit on the number of times of rewriting. If the number of times of rewriting exceeds the allowable number of times of rewriting, it becomes difficult to correctly write data, and the reliability of data is significantly lowered. For this reason, it is necessary to monitor the number of rewrites in the nonvolatile memory. In the case of a semiconductor device including a nonvolatile memory and a CPU, the number of rewrites can be monitored by a program. However, in this case, since the number of programs to be executed by the CPU increases and the load on the CPU increases, it takes time to monitor the number of rewrites.

  In Patent Literature 1, the number of times of rewriting of the nonvolatile memory is incremented by a monitoring circuit, and when the increment result reaches a limit value, an interrupt request signal is output to an external control device.

  Patent Document 2 counts the number of times of rewriting to an external nonvolatile memory, generates a warning when the limit value is reached, and prohibits rewriting.

  In Patent Document 3, the number of rewrites is counted for each area of the nonvolatile memory, and writing to an area with a large number of rewrites is rearranged or prohibited from being written to an area with a small number of rewrites.

In Patent Document 4, when the frequency of rewriting to a specific area of a nonvolatile memory is high, conversion to another area is performed.
Japanese Patent Laid-Open No. 11-66869 Japanese Patent Laid-Open No. 10-64290 JP 2001-290792 A JP 2000-20252 A

  In Patent Document 1, since an interrupt request signal is output to a control device, rewriting to a non-volatile memory is prohibited, so rewriting of a non-volatile memory that reaches a limit value is not prohibited by hardware. Absent. For this reason, for example, if the interrupt program performs an incorrect operation, writing to the non-volatile memory that has reached the limit value may not be prohibited. In such a case, the reliability of the data is lowered.

  In Patent Document 2, since the rewrite restriction of the nonvolatile memory is not managed for each area, rewriting of the entire nonvolatile memory cannot be effectively used.

  In Patent Document 3, since address conversion is performed for each area of the nonvolatile memory to an area with a small number of rewrites, the address conversion process takes time, and error determination in the write process, that is, rewriting cannot be performed. It takes time to become clear.

  In Patent Document 4, if the frequency of rewriting to a specific area of a nonvolatile memory is high, the process of converting to a rewrite to another area is performed, so that the process takes time, and it takes time to determine an error in the write process. It takes.

  Therefore, conventionally, the rewriting of the area exceeding the allowable number of times of rewriting of the nonvolatile memory is surely prevented to improve the reliability of the data, the rewriting of the entire nonvolatile memory is effectively used, and the writing process is performed. There is a problem that the error judgment cannot be performed in a short time.

  Therefore, the present invention reliably prevents rewriting of an area exceeding the allowable number of times of rewriting of the nonvolatile memory to improve data reliability, effectively uses rewriting of the entire nonvolatile memory, and performs write processing. An object of the present invention is to provide a rewrite restriction method and a semiconductor device capable of performing error determination in a short time.

  The above problem is a method for restricting rewriting of an electrically erasable non-volatile memory, and for each area of the non-volatile memory, when a rewrite count reaches a predetermined value, a signal for prohibiting rewriting of the area is issued. This can be achieved by a rewriting restriction method including an output step.

  The above-described problem is a method for restricting rewriting of an electrically erasable nonvolatile memory, and when the number of times of rewriting has not reached a predetermined value for each area of the nonvolatile memory, This can also be achieved by a rewrite restriction method that includes a step of rewriting an area and executing a warning program when the number of rewrites reaches a predetermined value and prohibiting rewriting of the area.

  The above-described problems include a nonvolatile memory composed of a plurality of electrically erasable areas, a counter unit that monitors and holds the number of rewrites in each area, and when the number of rewrites reaches a predetermined value for each area. And a signal generation circuit that outputs a prohibition signal for prohibiting rewriting of the area, and rewriting of the area of the nonvolatile memory is prohibited based on the prohibition signal.

  According to the present invention, it is possible to reliably prevent rewriting of an area exceeding the allowable number of times of rewriting of the nonvolatile memory to improve data reliability, to effectively use rewriting of the entire nonvolatile memory, and to perform writing processing. Thus, it is possible to realize a rewrite restriction method and a semiconductor device that can perform error determination in a short time.

  Embodiments of a rewrite restriction method according to the present invention and a semiconductor device according to the present invention will be described below with reference to the drawings.

  In the following description, “rewrite” includes erasure. Therefore, in the following description, data rewriting based on the data rewriting command may be erasing data based on the data erasing command.

  FIG. 1 is a block diagram showing an embodiment of a semiconductor device according to the present invention. This embodiment of the semiconductor device employs an embodiment of the rewrite limiting method according to the present invention. In this embodiment, the present invention is applied to a one-chip microcomputer (microcomputer), but the present invention is not limited to this.

  A one-chip microcomputer 1 shown in FIG. 1 includes a CPU 2, a monitoring circuit 4, an interface (I / F) unit 11, and a nonvolatile memory 15 connected by a bus 3. The monitoring circuit 4 includes a counter unit 5, a rewrite limit number setting register unit 6, a comparison unit 7, a signal generation circuit 8, and a rewrite limit number excess display register unit 9. The I / F unit 11 includes changeover switches 12 and 16. The non-volatile memory 15 includes a plurality of areas, and in this embodiment, includes a program area 13 that stores a rewrite program, a program area 14 that stores a warning program, and a plurality of access areas R1 to R5. In FIG. 1, for convenience of explanation, five access areas R1 to R5 are shown, but the number of access areas can be arbitrarily set.

  In the present embodiment, the case where there is one nonvolatile memory 15 will be described, but it goes without saying that two or more nonvolatile memories may be provided. The program areas 13 and 14 need not be provided in the same nonvolatile memory, and may be provided in different nonvolatile memories. Furthermore, in the present embodiment, each of the access areas R1 to R5 has a fixed length, but may have a variable length.

  In this embodiment, since the nonvolatile memory 15 has five access areas R1 to R5, the counter unit 5 is composed of the corresponding five counters C1 to C5, and the rewrite limit count excess display register unit 9 is the corresponding five registers. It consists of r1-r5.

  Although not shown in FIG. 1 because it is not directly related to the gist of the present invention, an interface unit that can be connected to the outside of the one-chip microcomputer 1 is connected to the CPU 2. This interface unit may also be used as the I / F unit 11.

  The monitoring circuit 4 monitors a data rewrite command sent from the CPU 2 to the I / F unit 11 via the bus 3. The counter unit 5 of the monitoring circuit 4 counts the number of times of rewriting every time the access areas R1 to R5 of the nonvolatile memory 15 are rewritten, and holds the count values in the corresponding counters C1 to C5. In the rewrite limit number setting register unit 6, a common rewrite limit number for each of the regions R1 to R5 of the nonvolatile memory 15 is set in advance. The comparison unit 7 includes a count value held in a counter of the counter unit 5 corresponding to an access area indicated by a write address (rewrite address) of the nonvolatile memory 15 obtained via the bus 3 and a rewrite limit number setting register unit. 6 is compared with the rewrite limit number set to 6, and when the comparison results are equal, a flag is set in the corresponding register of the rewrite limit number excess display register unit 9.

  At the time of rewriting, when the signal generation circuit 8 reads the write address (rewrite address) obtained via the bus 3 and matches the access area indicated by the flag set in the register in the rewrite limit number excess display register unit 9, The write inhibit signal 10 is output to the I / F unit 11. The write inhibit signal 10 is input to the changeover switches 12 and 16 in the I / F unit 11.

  When the write address obtained via the bus 3 does not coincide with the access area indicated by the flag set in the register within the rewrite limit count display register unit 9, rewriting to the write address is possible, and the signal generating circuit 8 Does not output the write inhibit signal 10. That is, a signal for prohibiting writing is not output from the signal generation circuit 8 to the I / F unit 11. In this case, the changeover switch 16 does not receive the write inhibit signal 10, and therefore outputs the write enable signal WEX for the write address to the nonvolatile memory 15. Further, since the changeover switch 12 is not input with the write prohibition signal 10, the changeover control is performed so that the rewrite program for rewriting is read from the program area 13 of the nonvolatile memory 15, and the CPU 2 executes the rewrite program to the write address. Rewrite.

  On the other hand, when the write inhibit signal 10 is output from the signal generation circuit 8 to the I / F unit 11, the changeover switch 16 responds to the write inhibit signal 10 to the nonvolatile memory 15 of the write enable signal WEX for the write address. Stop the output of. As a result, rewriting to the write address is prohibited. Further, the changeover switch 12 is controlled so as to read out the warning program from the program area 14 of the non-volatile memory 15 in response to the write inhibit signal 10, and the CPU 2 executes the warning program to perform arbitrary error processing, etc. Rewriting to the write address is not performed.

  FIG. 2 is a flowchart for explaining the operation of the semiconductor device. In FIG. 2, in step S1, the CPU 2 permits writing to the nonvolatile memory 15 in response to an external request. In step S2, a known write command sequence is performed based on the writing permitted by the CPU 2, and a data write command, a write address, and write data are output. For convenience of explanation, it is assumed here that a data rewrite command is output as a data write command.

  In step S3, based on the write address, the monitoring circuit 4 exceeds the rewrite limit count set in the rewrite limit count setting register 6 so that the count value of the rewrite area held in the counter unit 5 exceeds the rewrite limit count setting register 6. The comparison unit 7 determines whether or not it exists. If the determination result in step S3 is NO, the signal prohibition signal 10 is not output from the signal generation circuit 8. Therefore, in step S4, the changeover switch 12 switches to read the rewrite program from the program area 13 of the nonvolatile memory 15. Thus, the changeover switch 16 is controlled to output the write permission signal WEX for the write address to the nonvolatile memory 15, so that the rewrite to the write address is permitted. In step S5, the CPU 2 executes a rewriting program and performs a writing process for rewriting to a write address.

  In step S6, the CPU 2 determines whether or not the final address of the writing process has been reached. If the determination result is NO, the process proceeds to the next address in step S7, and the process returns to step S2. On the other hand, the process ends if the decision result in the step S6 is YES.

  If the decision result in the step S3 is YES, the processes ST1 and ST2 are performed. Process ST1 consists of step S8. The process ST2 includes steps S11 to S13.

  In process ST1, since the changeover switch 12 is controlled to read out the warning program from the program area 14 of the non-volatile memory 15 in response to the write inhibit signal 10, the CPU 2 executes the warning program in step S8 and executes any error. Software processing such as processing is performed, and rewriting to the write address is not performed.

  In process ST2, in step S11, the changeover switch 16 stops outputting the write permission signal WEX for the write address to the nonvolatile memory 15 in response to the write prohibition signal 10, so that rewriting to the write address is prohibited. In step S12, the CPU 2 performs data polling and determines by software whether an error due to time over (time over error) has occurred. When data polling is performed and write data cannot be written to the nonvolatile memory 15 within a predetermined time, in step S13, the CPU 2 recognizes that a write error has occurred and performs software processing such as arbitrary error processing.

  When the write inhibit signal 10 is output, the changeover switch 12 is controlled to be switched and the warning program is executed, so that the write operation is not performed. Therefore, for example, if the warning program jumps to error processing, error processing can be performed without waiting for the processing ST2, and the time for error determination is shortened.

  As described above, in this embodiment, the rewrite of the area exceeding the allowable number of rewrites of the nonvolatile memory 15 is reliably prevented by the write inhibit signal 10, so that the reliability of data can be improved and the nonvolatile memory can be improved. The entire 15 rewrites can be used effectively. Also, address conversion to an area with a small number of rewrites or processing to convert to another area when the frequency of rewriting to a specific area is high is not performed, so error determination in the writing process can be performed in a short time. it can.

  Furthermore, if the warning program jumps to the error process in the process ST1, the error process can be performed without waiting for the process ST2, so that the error determination time can be further shortened.

  In the above embodiment, at least a part of the functions of the monitoring circuit 4 may be realized by the CPU 2. Similarly, at least some of the functions of the I / F unit 11 may be realized by the CPU 2.

  The functions of the rewrite limit count setting register 6 and / or the rewrite limit count excess display register 9 may be provided not on the monitoring circuit 4 side but on the nonvolatile memory 15 side.

The present invention includes the inventions appended below.
(Appendix 1) A method for restricting rewriting of an electrically erasable nonvolatile memory,
A method for restricting rewriting, comprising a step of outputting a signal for prohibiting rewriting of each area when the number of times of rewriting reaches a predetermined value for each area of the nonvolatile memory.
(Appendix 2) A method for restricting rewriting of an electrically erasable nonvolatile memory,
For each area of the non-volatile memory, if the number of rewrites has not reached the predetermined value, the rewrite program is executed to rewrite the area. When the number of rewrites reaches the predetermined value, the warning program is executed and the area is rewritten. A rewriting restriction method comprising a step of prohibiting rewriting of
(Supplementary note 3) The rewrite restriction method according to supplementary note 2, wherein the rewrite program and the warning program are stored in a program area of the nonvolatile memory.
(Additional remark 4) The rewriting restriction | limiting method of Additional remark 1 or 2 characterized by the above-mentioned step outputting a write prohibition signal with respect to the said area | region of the said non-volatile memory.
(Supplementary Note 5) Non-volatile memory composed of a plurality of electrically erasable areas;
A counter unit that monitors and holds the number of rewrites in each area;
For each area, a signal generation circuit that outputs a prohibition signal for prohibiting rewriting of the area when the number of times of rewriting reaches a predetermined value,
A semiconductor device, wherein rewriting of the area of the nonvolatile memory is prohibited based on the prohibition signal.
(Supplementary Note 6) A CPU is further provided.
The nonvolatile memory includes a program area for storing a rewrite program and a warning program,
The CPU executes the rewriting program for each area of the non-volatile memory when the number of rewrites does not reach the predetermined value, and rewrites the area, and when the number of rewrites reaches the predetermined value, 6. The semiconductor device according to appendix 5, wherein a warning program is executed.
(Supplementary note 7) The semiconductor device according to supplementary note 6, wherein the rewriting program and the warning program are stored in a program area of the same nonvolatile memory or different nonvolatile memories.
(Additional remark 8) It further has an interface part into which the prohibition signal is inputted,
The interface unit includes a first switch for switching between the rewriting program executed by the CPU and the warning program in response to the prohibition signal, and rewriting each area of the nonvolatile memory in response to the prohibition signal. The semiconductor device according to appendix 6 or 7, further comprising a second switch for switching over prohibition of rewriting.
(Supplementary note 9) The semiconductor device according to supplementary note 8, wherein at least one of the counter unit, the signal generation circuit, and the interface unit is realized by the CPU.
(Additional remark 10) At least one of the said counter part and the said signal generation circuit is implement | achieved by the said CPU, The semiconductor device of any one of additional marks 6-8 characterized by the above-mentioned.
(Additional remark 11) The said warning program is a program which jumps to the error processing by said CPU, The semiconductor device of any one of additional marks 6-10 characterized by the above-mentioned.
(Supplementary Note 12) The semiconductor device according to any one of Supplementary Notes 6 to 11, wherein the nonvolatile memory, the counter unit, the signal generation circuit, and the CPU are provided in a single chip. .

  As mentioned above, although this invention was demonstrated by the Example, this invention is not limited to the said Example, It cannot be overemphasized that various deformation | transformation and improvement are possible.

It is a block diagram which shows one Example of the semiconductor device which becomes this invention. 3 is a flowchart illustrating an operation of a semiconductor device.

Explanation of symbols

1 Microcomputer 2 CPU
4 Monitoring circuit 5 Counter unit 6 Rewrite limit count setting register 7 Comparison unit 8 Signal generation circuit 9 Rewrite limit count excess display register 11 I / F units 12, 16 Changeover switch 15 Non-volatile memory

Claims (5)

A method for restricting rewriting of electrically erasable nonvolatile memory,
A method for restricting rewriting, comprising a step of outputting a signal for prohibiting rewriting of each area when the number of times of rewriting reaches a predetermined value for each area of the nonvolatile memory. A method for restricting rewriting of electrically erasable nonvolatile memory,
If the number of rewrites does not reach the predetermined value for each area of the nonvolatile memory, the rewrite program is executed to rewrite the area, and when the number of rewrites reaches the predetermined value, the warning program is executed and the area is rewritten. A rewriting restriction method comprising a step of prohibiting rewriting of A nonvolatile memory composed of a plurality of electrically erasable areas;
A counter unit that monitors and holds the number of rewrites in each area;
For each area, a signal generation circuit that outputs a prohibition signal that prohibits rewriting of the area when the number of times of rewriting reaches a predetermined value,
A semiconductor device, wherein rewriting of the area of the nonvolatile memory is prohibited based on the prohibition signal. A CPU;
The nonvolatile memory includes a program area for storing a rewrite program and a warning program,
The CPU executes the rewrite program for each area of the non-volatile memory when the number of rewrites does not reach the predetermined value, and rewrites the area, and when the number of rewrites reaches the predetermined value, 4. The semiconductor device according to claim 3, wherein a warning program is executed. The semiconductor device according to claim 4, wherein at least one of the counter unit and the signal generation circuit is realized by the CPU.

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