JP2006060410A - Gain adjustment circuit, signal processing circuit equipped with the same, and electric equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gain adjustment circuit whose gain control speed is fast. <P>SOLUTION: The gain adjustment circuit 100 is equipped with a comparator 11 which compares the output signal of a band-pass filter 4 with a noise level voltage V<SB>T</SB>noise, an addition/subtraction value calculating circuit 15 which outputs a specified addition value or specified subtraction value according to a signal based upon the output of the comparator 11, a gain register 17 which temporarily stores a gain value, an adder subtracter 16 which performs calculation based upon the specific addition value or specific subtraction value outputted from the addition/subtraction value calculating circuit 15 and the gain value outputted from the gain register 17 and outputs the calculation result as the gain value to the gain register 17, and a voltage-current converting circuit 18 which controls the gain of an amplifier 3 according to the gain value outputted from the gain register 17. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a gain adjustment circuit that adjusts the gain of a variable gain device (variable gain amplifier or variable gain attenuator) that inputs a signal that is repeated with a long pause interval, and a signal processing circuit and an electric device that include the gain adjustment circuit.

A signal processing circuit (for example, an optical signal transmitted from an infrared remote control transmitter for an overseas manufacturer) that processes a signal repeated across a long pause period RT (2 to 4 times the signal generation period ST) as shown in FIG. In the light receiving circuit or the like for receiving the light, a signal recognition unit for recognizing the signal using the signal recognition level V _T signal is provided. In such a signal processing circuit, periodic noise as shown in FIG. 8 enters when there is no signal, and when the noise level is higher than the signal recognition level V _T signal, the noise is recognized as a signal by the signal recognition unit. It becomes the main factor of malfunction.

Therefore, in order to prevent malfunction, a determination unit for determining the signal and noise and detecting the signal and noise respectively is provided. When noise is detected by the determination unit, a variable gain provided before the signal recognition unit is provided. It is possible to reduce the gain of the device so that the noise level does not become higher than the signal recognition level V _T signal.

Here, as a discriminating means for discriminating a signal and noise and detecting each of the signal and noise, for example, a technique disclosed in Patent Document 1 can be cited. The technique disclosed in Patent Document 1 is a method of discriminating a signal and noise that are repeated across a long pause period Tp, which is longer than the period of noise during the check period Tcheck (for example, 96 mS) and the pause period Tp. If a shorter pause interval Td (for example, 24 mS) occurs, the signal is recognized, and if the pause interval Td does not occur during the check interval Tcheck, it is recognized as noise.
JP-T-2001-502147

  However, when the technique disclosed in Patent Document 1 described above is used, there is a problem that the gain adjustment speed is slow because the signal or noise is recognized for each check section Tcheck. For example, when the signal has 128 stages and the signal as shown in FIG. 7 is processed, 12.7S (= 127 × 100 mS) is required to shift from the minimum gain to the maximum gain, and the maximum gain to the minimum gain. 12.7S (= 127 × 100 mS) is required to shift to.

  In view of the above problems, an object of the present invention is to provide a gain adjustment circuit having a high gain adjustment speed, a signal processing circuit including the gain adjustment circuit, and an electric device.

  In order to achieve the above object, a gain adjustment circuit according to the present invention includes a comparison circuit that compares an input signal with a predetermined noise level voltage, and a predetermined addition value or a predetermined value according to a signal based on the output of the comparison circuit. Addition / subtraction value calculation circuit for outputting a subtraction value, gain register for temporarily storing a gain value, a predetermined addition value output from the addition / subtraction value calculation circuit or a predetermined subtraction value and a gain output from the gain register An adder / subtractor that calculates a value and outputs the calculation result as the gain value to the gain register, and a gain control unit that adjusts the gain of the external variable gain device according to the gain value output from the gain register. The configuration (hereinafter also referred to as a first configuration) is used.

  According to such a configuration, instead of recognizing signal or noise for each check section Tcheck as in the technique disclosed in Patent Document 1, it is determined whether the input signal is a signal or noise. Since the gain adjustment is performed without performing the gain adjustment, the gain adjustment speed can be increased.

  In the gain adjustment circuit having the first configuration, an oscillator that oscillates a clock signal having a predetermined period, an output of the comparison circuit is input to a set terminal, the clock signal is input to a reset terminal, and the addition / subtraction value calculation is performed. A set-reset flip-flop that sends output data to the circuit may be provided, and the gain register may perform a clock operation based on the clock signal.

  According to such a configuration, the predetermined period is longer than the period of noise and shorter than the rest period RT shown in FIG. 7, so that the gain adjustment speed can be increased even when the gain is increased or decreased. Can do.

  Further, in the gain adjustment circuit having the first configuration, an oscillator that oscillates a clock signal, and a first counter that outputs a pulse output every first time when the output of the determination unit is input to a reset terminal and is not reset. And a second counter that inputs the output of the first counter to a reset terminal and outputs a pulse every second time if the output is not reset, the gain register, the first counter, and the second counter A counter operates based on the clock signal, and the addition / subtraction value calculation circuit outputs a predetermined subtraction value when a pulse output from the second counter is input, and a predetermined output when a pulse output from the first counter is input. The added value may be output.

  According to such a configuration, the first time is longer than the period of the noise and shorter than the pause interval RT shown in FIG. 7, and the second time is added to the signal generation interval ST and the pause interval RT shown in FIG. By setting the time, the gain adjustment speed when increasing the gain can be increased.

  Further, from the viewpoint of enabling the return to the required gain during the rest period RT shown in FIG. 7 even when the gain of the external variable gain device falls more than necessary, or from the viewpoint of further increasing the gain adjustment speed when increasing the gain. In any of the above-described gain adjustment circuits, it is preferable that the predetermined addition value is larger than the absolute value of the predetermined subtraction value.

  In addition, from the viewpoint of suppressing the fluctuation of the gain value, the gain adjustment circuit having any one of the above configurations includes storage means for temporarily storing the previous predetermined addition value or the predetermined subtraction value, and the adder / subtractor includes: If the previous predetermined addition value or predetermined subtraction value stored in the storage means is not the same as the predetermined addition value or predetermined subtraction value output from the addition / subtraction value calculation circuit, the addition / subtraction value calculation circuit The gain value output from the gain register is directly output to the gain register as the gain value without calculating the predetermined addition value or the predetermined subtraction value output from the gain value and the gain value output from the gain register. You may make it do.

  The signal processing circuit according to the present invention receives a variable gain device, a signal processing unit that processes a signal based on the output of the variable gain device, and a signal based on the output of the variable gain device, and the variable gain device. And a gain adjustment circuit for adjusting the gain of the gain adjustment circuit according to the present invention described above. Moreover, the electric equipment according to the present invention is configured to include the signal processing circuit according to the present invention described above.

  According to the present invention, it is possible to realize a gain adjustment circuit having a high gain adjustment speed, a signal processing circuit and an electric device including the gain adjustment circuit.

  An embodiment of the present invention will be described below with reference to the drawings. As a signal processing circuit according to the present invention, here, a light receiving circuit that receives an optical signal transmitted from an infrared remote control transmitter for an overseas manufacturer will be described as an example.

  One structural example of the light receiving circuit according to the present invention is shown in FIG. The light receiving circuit shown in FIG. 1 includes a photodiode 1, a current-voltage conversion circuit 2, an amplifier 3 with variable gain, a bandpass filter 4, an operational amplifier 5, a constant voltage source 6, and a pulse modulation signal demodulation circuit. 7, a transistor 8, a pull-up resistor 9, an output terminal 10, and a gain adjustment circuit 100.

  An optical signal transmitted from an infrared remote control transmitter (not shown) is converted into a current signal by the photodiode 1, the current signal is converted into a voltage signal by the current-voltage conversion circuit 2, and the voltage signal is converted by the amplifier 3. The amplified signal is input to the bandpass filter 4.

  The bandpass filter 4 passes only the frequency components in a predetermined range of the input signal and sends them to the non-inverting input terminal of the operational amplifier 5 and the gain adjustment circuit 100.

The operational amplifier 5 amplifies the comparison result between the output signal of the bandpass filter 4 and the signal recognition level voltage V _T signal output from the constant voltage source 6 and outputs the result to the pulse modulation signal demodulation circuit 7. Since the optical signal sent from the infrared remote control transmitter (not shown) to the photodiode 1 is a pulse modulation signal, the output signal of the operational amplifier 5 is also a pulse modulation signal. The pulse modulation signal demodulation circuit 7 demodulates the output signal of the operational amplifier 5 which is a pulse modulation signal, and outputs the demodulated signal to the base of the transistor 8. The emitter of the transistor 8 is grounded, the collector of the transistor 8 is connected to the pull-up resistor 9, and the output terminal 10 is connected to the connection node between the collector of the transistor 8 and the pull-up resistor 9. This signal becomes an inverted signal of the signal output from the pulse modulation signal demodulation circuit 7.

  The gain adjustment circuit 100 adjusts the gain of the amplifier 3 according to the output signal of the bandpass filter 4.

As described above, the light receiving circuit shown in FIG. 1 receives the optical signal, which is a pulse modulation signal, and has a low level corresponding to the generation of the pulse of the optical signal and a high level corresponding to the non-occurrence of the pulse of the optical signal. A code signal can be output. In addition, since the gain adjustment circuit 100, which will be described in detail later, adjusts the gain of the amplifier 3, it is possible to prevent noise from becoming larger than the signal recognition level voltage V _T signal.

  Here, the gain adjustment circuit 100 which is a characteristic part of the present invention will be described in detail. The gain adjustment circuit 100 includes a comparator 11, a constant voltage source 12, an oscillator (OSC) 13, a set / reset flip-flop 14, an addition / subtraction value calculation circuit 15, an adder / subtractor 16, a gain register 17, a voltage − And a current conversion circuit 18. Since the gain register 17 that temporarily stores the gain value is a 7-bit register, the gain value can be adjusted in 128 steps.

The comparator 11 does not determine whether the output signal of the bandpass filter 4 is a signal or noise, and the noise level voltage V _T from which the output signal of the bandpass filter 4 is output from the constant voltage source 12. If it is larger than noise (<V _T signal), a high level signal is set. If the output signal of the bandpass filter 4 is not larger than the noise level voltage V _T noise output from the constant voltage source 12, a low level signal is set and reset. Output to the set terminal of

  The set / reset flip-flop 14 is set at every predetermined period by a clock signal having a predetermined period (longer than the period of noise and shorter than the rest period RT shown in FIG. 7, 20 mS in this embodiment) oscillated from the oscillator 13. Reset.

  The addition / subtraction value calculation circuit 15 outputs a predetermined subtraction value (-1 in this embodiment) if the output of the set / reset flip-flop 14 is High level, and predetermined if the output of the set / reset flip-flop 14 is Low level. Is added (2 in this embodiment). The adder / subtractor 16 calculates the gain value (7-bit digital data) output from the gain register 17 and the subtraction value or addition value output from the addition / subtraction value calculation circuit 15, and outputs the calculation result as a gain value (7-bit digital data). ) To the gain register 17.

  The gain register 17 performs a clock operation for each predetermined period based on the clock signal oscillated from the oscillator 13. The gain value (7-bit digital data) output from the gain register 17 is output to the voltage-current conversion circuit 18 in addition to the adder / subtractor 16. The voltage-current conversion circuit 18 converts a gain value (7-bit digital data) that is a voltage signal into an analog current signal, and varies the gain of the amplifier 3 by the analog current signal.

  In the gain adjustment circuit 100 of the light receiving circuit shown in FIG. 1, for example, when processing a signal as shown in FIG. 7, 1.27 S (= 127 × 20 mS ÷ 2 (addition value) is required to shift from the minimum gain to the maximum gain. )) Necessary and 2.54S (= 127 × 20 mS) is required to shift from the maximum gain to the minimum gain. On the other hand, when the technique disclosed in Patent Document 1 is used, 12.7S is required to shift from the minimum gain to the maximum gain under the same conditions, and 12 shifts from the maximum gain to the minimum gain. .7S is required. Thus, the gain adjustment circuit 100 of the light receiving circuit shown in FIG. 1 has a higher gain adjustment speed than the case where the technique disclosed in Patent Document 1 is used. Therefore, the light receiving circuit shown in FIG. 1 is more smoothly adapted when noise suddenly occurs (for example, when a fluorescent lamp suddenly lights up).

  Further, when the technique disclosed in Patent Document 1 is used, a counter including a plurality of flip-flops that count the check section Tcheck is necessary. However, the gain adjustment circuit 100 of the light receiving circuit shown in FIG. Are provided with a calculation circuit block (addition / subtraction value calculation circuit 15 and adder / subtractor 16) comprising a plurality of logic gates. Comparing the circuit scale of the counter and the calculation circuit block, the circuit scale of the calculation circuit block can be remarkably reduced as compared with the counter. Therefore, the gain adjustment circuit 100 of the light receiving circuit shown in FIG. Can be achieved.

The gain adjustment circuit 100 of the light receiving circuit shown in FIG. 1 does not discriminate between noise and signal. For this reason, when the light receiving circuit shown in FIG. 1 continues to receive a signal, the gain of the amplifier 3 may decrease more than necessary because the signal is larger than the noise level voltage V _T noise. However, since there is a pause interval RT (see FIG. 7) between the signal interval ST and the signal interval ST, no problem occurs if the required gain can be recovered during the pause interval RT. Note that it is desirable to set the added value larger than the absolute value of the subtracted value so that the necessary gain can be restored during the rest period RT. As the added value is increased, the return of the gain is assured. However, if the added value is increased too much, noise may be recognized as a signal. Therefore, it is necessary to set the added value to an appropriate value.

  Next, another configuration example of the light receiving circuit according to the present invention is shown in FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The light receiving circuit shown in FIG. 2 has a configuration in which the gain adjusting circuit 100 of the light receiving circuit shown in FIG. The gain adjustment circuit 101 is configured by replacing the adder / subtractor 16 and the gain register 17 of the gain adjustment circuit 100 with an adder / subtractor 16 'and a gain register 17', respectively.

  Hereinafter, the gain adjustment circuit 101 will be described. The gain adjustment circuit 101 includes a comparator 11, a constant voltage source 12, an oscillator (OSC) 13, a set / reset flip-flop 14, an addition / subtraction value calculation circuit 15, an adder / subtractor 16 ', a gain register 17', And a voltage-current conversion circuit 18. The gain register 17 ′ that temporarily stores the gain value is a 9-bit register, and the upper 7 bits are used for temporary storage of the gain value. Therefore, the gain value can be adjusted in 128 steps.

The comparator 11 does not determine whether the output signal of the bandpass filter 4 is a signal or noise, and the noise level voltage V _T from which the output signal of the bandpass filter 4 is output from the constant voltage source 12. If it is larger than noise (<V _T signal), a high level signal is set. If the output signal of the bandpass filter 4 is not larger than the noise level voltage V _T noise output from the constant voltage source 12, a low level signal is set and reset. Output to the set terminal of

  The set / reset flip-flop 14 is set at every predetermined period by a clock signal having a predetermined period (longer than the period of noise and shorter than the rest period RT shown in FIG. 7, 20 mS in this embodiment) oscillated from the oscillator 13. Reset.

  The addition / subtraction value calculation circuit 15 outputs a predetermined subtraction value (-1 in this embodiment) if the output of the set / reset flip-flop 14 is High level, and predetermined if the output of the set / reset flip-flop 14 is Low level. Is added (2 in this embodiment).

  The adder / subtractor 16 ′ includes the gain value (upper 7-bit digital data) output from the gain register 17 ′ and the previous addition / subtraction value (lower 2-bit digital data) and the subtraction value or addition value output from the addition / subtraction value calculation circuit 15. (The current addition / subtraction value) is input (step # 10 in FIG. 3).

  If the previous addition / subtraction value (low-order 2-bit digital data) output from the gain register 17 ′ is the same as the subtraction value or addition value (current addition / subtraction value) output from the addition / subtraction value calculation circuit 15 (FIG. 3). In step # 20, the adder / subtractor 16 'calculates the gain value (high-order 7-bit digital data) output from the gain register 17' and the subtraction value or addition value (current addition / subtraction value) output from the addition / subtraction value calculation circuit 15. And outputs the calculation result as a gain value (high-order 7-bit digital data) to the gain register 17 ′ (step # 30 in FIG. 3), and the subtraction value or addition value (this time) output by the addition / subtraction value calculation circuit 15 (Addition / subtraction value) is output to the gain register 17 'as an addition / subtraction value (low-order 2-bit digital data) to be held (step # 40 in FIG. 3). On the other hand, if the previous addition / subtraction value (low-order 2-bit digital data) output from the gain register 17 ′ is different from the subtraction value or addition value (current addition / subtraction value) output from the addition / subtraction value calculation circuit 15 (FIG. 3, NO at step # 20), the adder / subtractor 16 ′ outputs the gain value (upper 7-bit digital data) output from the gain register 17 ′ as it is to the gain register 17 ′ as the gain value (upper 7-bit digital data). At the same time (step # 50 in FIG. 3), the subtraction value or addition value (current addition / subtraction value) output by the addition / subtraction value calculation circuit 15 is output to the gain register 17 ′ as the addition / subtraction value (low-order 2-bit digital data) to be held. (Step # 60 in FIG. 3).

  The gain register 17 ′ performs a clock operation for each predetermined period based on the clock signal oscillated from the oscillator 13. The gain value (high-order 7-bit digital data) output from the gain register 17 ′ is also output to the voltage-current conversion circuit 18 in addition to the adder / subtractor 16 ′. The voltage-current conversion circuit 18 converts a gain value (upper 7-bit digital data), which is a voltage signal, into an analog current signal, and varies the gain of the amplifier 3 by the analog current signal.

  The gain adjusting circuit 101 of the light receiving circuit shown in FIG. 2 has the same effect as the gain adjusting circuit 100 of the light receiving circuit shown in FIG. 1, and the gain value is not input unless the addition value is continuously input to the adder / subtractor 16 ′. Since the gain value does not decrease unless the subtraction value is continuously input to the adder / subtractor 16 'without increasing, fluctuation of the gain value can be suppressed.

  Next, still another configuration example of the light receiving circuit according to the present invention is shown in FIG. 4 that are the same as those in FIG. 1 are assigned the same reference numerals and detailed descriptions thereof are omitted. The light receiving circuit shown in FIG. 4 has a configuration in which the gain adjusting circuit 100 of the light receiving circuit shown in FIG. The gain adjustment circuit 102 is configured by replacing the set-reset flip-flop 14 of the gain adjustment circuit 100 with counters 19 and 20.

  Hereinafter, the gain adjustment circuit 102 will be described. The gain adjustment circuit 102 includes a comparator 11, a constant voltage source 12, an oscillator (OSC) 13, an addition / subtraction value calculation circuit 15, an adder / subtractor 16, a gain register 17, a voltage-current conversion circuit 18, and a counter. 19 and 10. Since the gain register 17 that temporarily stores the gain value is a 7-bit register, the gain value can be adjusted in 128 steps.

The comparator 11 does not determine whether the output signal of the bandpass filter 4 is a signal or noise, and the noise level voltage V _T from which the output signal of the bandpass filter 4 is output from the constant voltage source 12. If it is greater than noise (<V _T signal), a high level signal is output. If the output signal of the bandpass filter 4 is not greater than the noise level voltage V _T noise output from the constant voltage source 12, a low level signal is output. Output to the reset terminal. The output of the counter 19 is sent to the reset terminal of the counter 20 and the addition / subtraction value calculation circuit 15. The output of the counter 20 is sent to the addition / subtraction value calculation circuit 15.

  The counters 19 and 20 perform a counter operation based on the clock signal oscillated from the oscillator 13. For example, as shown in FIG. 5, the counters 19 and 20 may be configured by a plurality of flip-flops FF1 to FFn, a negative circuit INV1, and a logical product circuit AND1.

  If not reset, the counter 19 outputs a pulse every predetermined time (20 mS in the present embodiment) longer than the period of noise and shorter than the rest period RT shown in FIG. The counter 19 is reset when the output of the comparator 11 becomes High level. If not reset, the counter 20 outputs a pulse every time (100 mS in this embodiment) obtained by adding the signal generation period ST and the pause period RT shown in FIG. The counter 20 is reset by the pulse output of the counter 19.

  Therefore, the timing chart of the output OUT11 of the comparator 11, the output OUT20 of the counter 20, and the output OUT19 of the counter 19 when there is no signal is as shown in FIG. In FIG. 6, T1 indicates a section without noise, and T2 indicates a section with noise.

  The addition / subtraction value calculation circuit 15 outputs a predetermined subtraction value (-1 in this embodiment) when a pulse output from the counter 20 is input, and a predetermined addition value (in this embodiment) when a pulse output from the counter 19 is input. 1) is output. The adder / subtractor 16 calculates the gain value (7-bit digital data) output from the gain register 17 and the subtraction value or addition value output from the addition / subtraction value calculation circuit 15, and outputs the calculation result as a gain value (7-bit digital data). ) To the gain register 17.

  The gain register 17 performs a clock operation for each predetermined period based on the clock signal oscillated from the oscillator 13. The gain value (7-bit digital data) output from the gain register 17 is output to the voltage-current conversion circuit 18 in addition to the adder / subtractor 16. The voltage-current conversion circuit 18 converts a gain value (7-bit digital data) that is a voltage signal into an analog current signal, and varies the gain of the amplifier 3 by the analog current signal.

  In the gain adjustment circuit 102 of the light receiving circuit shown in FIG. 4, for example, when processing a signal as shown in FIG. 7, 2.54S (= 127 × 20 mS) is required to shift from the minimum gain to the maximum gain. It takes 12.7S (= 127 × 100mS) to shift from the maximum gain to the minimum gain. On the other hand, when the technique disclosed in Patent Document 1 is used, 12.7S is required to shift from the minimum gain to the maximum gain under the same conditions, and 12 shifts from the maximum gain to the minimum gain. .7S is required. As described above, the gain adjustment circuit 102 of the light receiving circuit shown in FIG. 4 has a faster gain adjustment speed when the gain is increased as compared with the case where the technique disclosed in Patent Document 1 is used. Further, by setting the added value larger than the absolute value of the subtracted value, the gain adjustment speed when increasing the gain can be further increased.

  Also in the light receiving circuit shown in FIG. 4, a change similar to the change from the light receiving circuit shown in FIG. 1 to the light receiving circuit shown in FIG. 2 can be made. By performing such deformation, it is possible to suppress fluctuation of the gain value.

  Note that the light receiving circuit according to the present invention shown in FIGS. 1, 2, and 4 described above includes various electric devices (for example, TV and audio) having a control unit that controls the entire device based on a signal output from the light receiving circuit. Equipment). In this embodiment, a photodiode is used as the light receiving element, but another light receiving element such as a phototransistor may be used. Further, various setting values (the number of gain steps, the numerical value of the signal generation section ST, the numerical value of the pause section RT, the addition value, the subtraction value, etc.) are not limited to the values used in the above-described embodiment.

These are figures which show the example of 1 structure of the light-receiving circuit based on this invention. These are figures which show the other structural example of the light-receiving circuit based on this invention. These are the operation | movement flowcharts of the adder / subtracter which the light-receiving circuit shown in FIG. 2 comprises. These are figures which show the further another structural example of the light receiving circuit which concerns on this invention. These are figures which show one structural example of the counter which the light-receiving circuit shown in FIG. 4 comprises. These are the timing charts of the respective outputs of the light receiving circuit shown in FIG. These are figures which show an example of the waveform of the signal repeated on both sides of the long rest area RT. These are figures which show an example of the waveform of periodic noise.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photodiode 2 Current-voltage conversion circuit 3 Amplifier 4 Band pass filter 6, 12 Constant voltage source 7 Pulse modulation signal demodulation circuit 8 Transistor 9 Pull-up resistor 10 Output terminal 11 Comparator 13 Oscillator 14 Set reset flip-flop 15 Addition / subtraction value calculation Circuit 16, 16 'Adder / Subtractor 17, 17' Gain register 18 Voltage-current conversion circuit 19, 20 Counter 100-102 Gain adjustment circuit AND1 AND circuit FF1-FFn Flip-flop INV1 Negative circuit

Claims (7)

A comparison circuit that compares the input signal with a predetermined noise level voltage;
An addition / subtraction value calculation circuit for outputting a predetermined addition value or a predetermined subtraction value according to a signal based on the output of the comparison circuit;
A gain register that temporarily stores the gain value;
An adder / subtractor that calculates a predetermined addition value or a predetermined subtraction value output from the addition / subtraction value calculation circuit and a gain value output from the gain register, and outputs a calculation result to the gain register as the gain value;
A gain control circuit comprising: a gain control unit that adjusts the gain of the external variable gain device in accordance with a gain value output from the gain register. An oscillator that oscillates a clock signal having a predetermined period; a set reset flip-flop that inputs an output of the comparison circuit to a set terminal; inputs the clock signal to a reset terminal; and sends output data to the addition / subtraction value calculation circuit; With
The gain adjustment circuit according to claim 1, wherein the gain register performs a clock operation based on the clock signal. An oscillator that oscillates a clock signal, an output of the determination unit is input to a reset terminal, and if not reset, a first counter that outputs a pulse every first time, and an output of the first counter to a reset terminal And a second counter that outputs a pulse every second time if it is not reset,
The gain register, the first counter, and the second counter operate based on the clock signal, and the addition / subtraction value calculation circuit outputs a predetermined subtraction value when a pulse output from the second counter is input, 2. The gain adjustment circuit according to claim 1, wherein when a pulse output from the first counter is input, a predetermined added value is output.   The gain adjustment circuit according to claim 1, wherein the predetermined addition value is larger than an absolute value of the predetermined subtraction value. Storage means for temporarily storing the previous predetermined addition value or the predetermined subtraction value;
In the adder / subtracter, if the previous predetermined addition value or the predetermined subtraction value stored in the storage means is not the same as the predetermined addition value or the predetermined subtraction value output from the addition / subtraction value calculation circuit, Without calculating the predetermined addition value or the predetermined subtraction value output from the addition / subtraction value calculation circuit and the gain value output from the gain register, the gain value output from the gain register is directly used as the gain value. The gain adjustment circuit according to claim 1, wherein the gain adjustment circuit outputs the gain to the gain register. A variable gain device; a signal processing unit that processes a signal based on the output of the variable gain device; and a gain adjustment circuit that inputs a signal based on the output of the variable gain device and adjusts the gain of the variable gain device. ,
A signal processing circuit, wherein the gain adjustment circuit is the gain adjustment circuit according to claim 1.   An electric device comprising the signal processing circuit according to claim 6.

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