JP2006060164A - Nitride semiconductor device and nitride semiconductor crystal growth method - Google Patents
Nitride semiconductor device and nitride semiconductor crystal growth method Download PDFInfo
- Publication number
- JP2006060164A JP2006060164A JP2004243242A JP2004243242A JP2006060164A JP 2006060164 A JP2006060164 A JP 2006060164A JP 2004243242 A JP2004243242 A JP 2004243242A JP 2004243242 A JP2004243242 A JP 2004243242A JP 2006060164 A JP2006060164 A JP 2006060164A
- Authority
- JP
- Japan
- Prior art keywords
- nitride semiconductor
- substrate
- thin film
- crystal growth
- growth method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
本発明は、III−Ｖ族窒化物半導体薄膜の結晶成長方法とその成長方法によって形成された窒化物半導体膜を利用した半導体デバイスに関し、特に、微傾斜面を有するオフ基板上に窒化物半導体膜を結晶成長させる方法とその成長方法によって形成された窒化物半導体膜を利用した半導体デバイスに関するものである。 The present invention relates to a crystal growth method of a group III-V nitride semiconductor thin film and a semiconductor device using the nitride semiconductor film formed by the growth method, and more particularly to a nitride semiconductor film on an off-substrate having a slightly inclined surface. And a semiconductor device using a nitride semiconductor film formed by the growth method.
窒化物半導体は青色・紫外光デバイス及び高出力・高周波電子デバイスの応用に重要な材料として注目されている。しかし、窒化物半導体薄膜を結晶成長させるのに適切な基板がなく、現在格子ミスマッチの大きいサファイア基板及びＳｉＣ基板の使用が主流である。そのため、窒化物半導体薄膜中に転位密度が非常に高い（約１０10/ｃｍ2）。この高密度転位はデバイス動作特性に多大な悪影響を与えることが既に実証されている。例えば、ＩｎＧａＮ/（Ａｌ，Ｇａ）Ｎ量子井戸構造を基本とするレーザーダイオードの出力パワーと動作寿命は転位密度に大きく依存し、転位密度が低ければ出力パワーが高く寿命が長くなる。また、ＡｌＧａＮ/ＧａＮヘテロ構造を基本とする電子デバイスでも高密度の転位によるリーク電流の増大や出力パワーの低下などが問題となっている。従って、薄膜中の転位密度低減がデバイス性能の向上に極めて重要である。 Nitride semiconductors have attracted attention as important materials for blue / ultraviolet light devices and high power / high frequency electronic devices. However, there is no suitable substrate for crystal growth of the nitride semiconductor thin film, and the use of sapphire substrates and SiC substrates having a large lattice mismatch is currently the mainstream. For this reason, the dislocation density in the nitride semiconductor thin film is very high (about 10 10 / cm 2 ). This high density dislocation has already been demonstrated to have a significant adverse effect on device operating characteristics. For example, the output power and operating life of a laser diode based on an InGaN / (Al, Ga) N quantum well structure depend greatly on the dislocation density, and the lower the dislocation density, the higher the output power and the longer the life. Further, even in an electronic device based on an AlGaN / GaN heterostructure, there are problems such as an increase in leakage current and a decrease in output power due to high density dislocations. Therefore, reducing the dislocation density in the thin film is extremely important for improving the device performance.
従来、窒化物半導体薄膜結晶成長技術として分子線エピタキシャル成長 (ＭＢＥ：molecular beam epitaxy) 法、有機金属化学気相成長(ＭＯＣＶＤ：metal-organic chemical vapor deposition)法、ハイドライド気相成長(ＨＶＰＥ：hydride vapor phase epitaxy)法などが主に用いられてきたが、いずれの方法を用いても転位密度の低減は容易ではなく、高品位の結晶成長に向けて様々な試みが重ねられてきた。その一つは、横方向エピタキシャル成長法である（例えば、非特許文献１参照）。これは、基板上にＡｌＮバッファ層を介してＧａＮ下地層を成長させ、その上にストライプ状のＳｉＯ２マスクを形成し、ＧａＮ下地層からマスク上にＧａＮを結晶成長させる方法である。また、複数の中間層を挿入する方法も提案されている（例えば、非特許文献２参照）。この方法は、窒化物半導体（例えばＡｌＧａＮ）層とＳｉＡｌＮ合金層とを交互に複数層積層するものである。
上述した方法によると、転位を効果的に低減することができるが、横方向エピタキシャル成長法では、フォトリソグラフィ工程やエッチング工程が必要となるなど工程が複雑な上に多くの工数が必要となる。しかも、横方向エピタキシャル成長膜をマスク上で連結するためには、厚い膜を成長させなければならない。また、中間層挿入法では、デバイスを構成するのには使用されない転位を低減させるためだけの積層膜を、数〜十数回反応ガスを切り替えて形成しなければならないため、やはり工程が複雑で多くの工数が必要となる上に厚い膜を形成しなければならないものである。 According to the method described above, dislocations can be effectively reduced. However, the lateral epitaxial growth method requires complicated steps such as a photolithography process and an etching process, and requires a lot of man-hours. Moreover, in order to connect the lateral epitaxial growth films on the mask, a thick film must be grown. In addition, in the intermediate layer insertion method, a laminated film only for reducing dislocations that are not used to constitute a device must be formed by switching the reaction gas several to dozens of times. A lot of man-hours are required, and a thick film must be formed.
本発明の課題は、上述した従来方法の問題点を解決することであって、その目的は、十分に転位の低減された窒化物半導体膜とその半導体膜を利用した窒化物半導体デバイスを、簡単な方法でしかも厚い膜を形成することなく実現できるようにすることである。 An object of the present invention is to solve the problems of the conventional method described above, and the object is to simplify a nitride semiconductor film having sufficiently reduced dislocations and a nitride semiconductor device using the semiconductor film. In other words, it can be realized without forming a thick film.
上記の目的を達成するため、本発明によれば、基板上に窒化物半導体をエピタキシャル成長させて形成した窒化物半導体デバイスにおいて、基板が０．５°以上の微傾斜面を有する基板であることを特徴とする窒化物半導体デバイス、が提供される。 In order to achieve the above object, according to the present invention, in a nitride semiconductor device formed by epitaxially growing a nitride semiconductor on a substrate, the substrate is a substrate having a slightly inclined surface of 0.5 ° or more. A nitride semiconductor device is provided.
また、上記の目的を達成するため、本発明によれば、基板上に窒化物半導体をエピタキシャル成長させて形成した窒化物半導体デバイスにおいて、エピタキシャル成長結晶層の少なくとも一つは多原子層高さのマクロステップを有していることを特徴とする窒化物半導体デバイス、が提供される。 In order to achieve the above object, according to the present invention, in a nitride semiconductor device formed by epitaxially growing a nitride semiconductor on a substrate, at least one of the epitaxially grown crystal layers is a macro step having a polyatomic layer height. A nitride semiconductor device is provided.
また、上記の目的を達成するため、本発明によれば、基板上に窒化物半導体薄膜をエピタキシャル成長させる窒化物半導体結晶成長方法において、０．５°以上の微傾斜面を有する基板を用いることを特徴とする窒化物半導体結晶成長方法、が提供される。 In order to achieve the above object, according to the present invention, in a nitride semiconductor crystal growth method for epitaxially growing a nitride semiconductor thin film on a substrate, a substrate having a slightly inclined surface of 0.5 ° or more is used. A nitride semiconductor crystal growth method is provided.
また、上記の目的を達成するため、本発明によれば、基板上に窒化物半導体薄膜をエピタキシャル成長させる窒化物半導体結晶成長方法において、薄膜表面に多原子層高さを持つマクロステップを形成することを特徴とする窒化物半導体結晶成長方法、が提供される。 In order to achieve the above object, according to the present invention, in a nitride semiconductor crystal growth method for epitaxially growing a nitride semiconductor thin film on a substrate, a macro step having a polyatomic layer height is formed on the surface of the thin film. A nitride semiconductor crystal growth method is provided.
また、上記の目的を達成するため、本発明によれば、基板上に窒化物半導体薄膜をエピタキシャル成長させる窒化物半導体結晶成長方法において、基板上に垂直方向に伝播する転位の外に斜め方向に伸びる転位を生じさせ、斜め方向に伸びる転位によって転位の垂直方向の伝播を抑制することを特徴とする窒化物半導体結晶成長方法、が提供される。 In order to achieve the above object, according to the present invention, in a nitride semiconductor crystal growth method for epitaxially growing a nitride semiconductor thin film on a substrate, it extends in an oblique direction out of dislocations propagating vertically on the substrate. There is provided a nitride semiconductor crystal growth method characterized in that dislocations are generated and the propagation of dislocations in the vertical direction is suppressed by dislocations extending in an oblique direction.
本発明においては、0.5°以上のオフ角度の基板を用いて窒化物半導体の結晶成長が行われる。オフ角度が0.5°以上になると、成長する薄膜表面に形成されるステップは多原子層高さのマクロステップとなる。そして、ジャスト基板（0°基板）上の薄膜中のような真上に走る転位以外に傾斜方向に進行する転位線が発生する。この傾斜方向に走っている転位線が真上に走っている転位線と相互作用し、転位ループなどを作り真上に伝搬する転位を止める。これが、本発明の転位密度低減の原理であり、従来の技術と全く異なる原理に基づく転位密度低減方法である。
本発明の方法は、単に微傾斜のオフ基板を用いるだけの方法であり、複雑なプロセスや多くの繰り返し工程などの必要がないので、容易にかつ短時間の作業により転位の少ない高品質の窒化物半導体膜を得ることができる。
In the present invention, crystal growth of a nitride semiconductor is performed using a substrate having an off angle of 0.5 ° or more. When the off angle is 0.5 ° or more, the step formed on the surface of the growing thin film becomes a macro step having a polyatomic layer height. Then, dislocation lines traveling in the tilt direction are generated in addition to the dislocations that run directly above the thin film on the just substrate (0 ° substrate). This dislocation line running in the tilt direction interacts with the dislocation line running directly above, thereby creating a dislocation loop and stopping the dislocation propagating directly above. This is the principle of dislocation density reduction according to the present invention, and is a dislocation density reduction method based on a completely different principle from the prior art.
The method of the present invention is merely a method using a slightly inclined off-substrate, and there is no need for complicated processes and many repeated processes. A physical semiconductor film can be obtained.
次に、本発明の実施の形態について図面を参照して詳細に説明する。図１は、本発明の実施の形態を説明するための断面図である。基板としては、オフ角度αの微傾斜基板１が用いられる。基板材料は、サファイア（Ａｌ２Ｏ３）、６Ｈ−ＳｉＣ、ＺｎＯ、Ｓｉ、ＧａＡｓ、ＭｇＡｌ２Ｏ４、ＬｉＧａＯ２またはＬｉＡｌＯ２などが用いられる。オフ角度αの下限は、基板上に成長させる窒化物半導体膜の表面に多原子層高さのマクロステップが形成される値に選定される。その下限は、結晶成長方法およびプロセス条件によって異なるので、一意的に定めることはできないが、概ね0.5°以上は必要である。 Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view for explaining an embodiment of the present invention. As the substrate, a slightly inclined substrate 1 with an off angle α is used. As the substrate material, sapphire (Al 2 O 3 ), 6H—SiC, ZnO, Si, GaAs, MgAl 2 O 4 , LiGaO 2 or LiAlO 2 is used. The lower limit of the off angle α is selected to a value at which a macro step having a polyatomic layer height is formed on the surface of the nitride semiconductor film grown on the substrate. The lower limit varies depending on the crystal growth method and process conditions, and cannot be uniquely determined. However, the lower limit is generally 0.5 ° or more.
この微傾斜基板１上に、窒化物半導体膜２、３がエピタキシャル成長される。窒化物半導体膜は、III−Ｖ族窒化物半導体であって、ＢＮ、ＡｌＮ、ＧａＮ、ＩｎＮまたはこれらの混晶（四元窒化物を含む）である。窒化物半導体膜２はバッファ層であって、ＡｌＮ、ＧａＮあるいはそれらの混晶が好適に用いられる。窒化物半導体膜３は、デバイスを構成するための半導体膜であって、ＧａＮ、ＡｌＧａＮ、ＧａＩｎＮなどの積層膜によって構成され、ヘテロ接合を含み、ＳＱＷ（シングル量子井戸）またはＭＱＷ（多重量子井戸）を含んでいてもよい。また、ＡｌＧａＮ、ＧａＩｎＮなどは超格子構造であってもよい。 Nitride semiconductor films 2 and 3 are epitaxially grown on the slightly inclined substrate 1. The nitride semiconductor film is a group III-V nitride semiconductor, and is BN, AlN, GaN, InN, or a mixed crystal thereof (including quaternary nitrides). The nitride semiconductor film 2 is a buffer layer, and AlN, GaN, or a mixed crystal thereof is preferably used. The nitride semiconductor film 3 is a semiconductor film for constituting a device, is constituted by a laminated film of GaN, AlGaN, GaInN or the like, includes a heterojunction, and includes SQW (single quantum well) or MQW (multiple quantum well). May be included. Moreover, AlGaN, GaInN, etc. may have a superlattice structure.
窒化物半導体膜２、３のエピタキシャル成長には、ＭＯＣＶＤ法、ＭＢＥ法またはＨＶＰＥ法が用いられる。これらを組み合わせて用いることも可能である。
ＭＯＣＶＤ法を用いる場合、反応管内のサセプタ上に基板を保持し、この反応管に、アンモニアと１種の有機金属ガスまたは２種以上の有機金属ガスの混合ガスを窒素などのキャリアガスと共に供給して、所望の窒化物半導体を成長させる。Ｇａの原料としては例えばトリメチルガリウム（ＴＭＧ；（ＣＨ３）３Ｇａ）またはトリエチルガリウム（ＴＥＧ；（Ｃ２Ｈ５）３Ｇａ）を用い、Ａｌの原料として例えばトリメチルアルミニウム（（ＣＨ３）３Ａｌ）を用い、Ｂの原料として例えばトリエチルホウ素（（Ｃ２Ｈ５）３Ｂ）を用い、Ｉｎの原料としては、例えばトリメチルインジウム（（ＣＨ３）３Ｇａ）を用いる。
成長する窒化物半導体に導電型不純物を付与する場合には、ｎ型の場合、例えばシラン（ＳｉＨ４）または塩化ケイ素（ＳｉＣｌ４）を同時に供給し、ｐ型の場合には、例えばビス＝シクロペンタジエニルマグネシウム（Ｃ５Ｈ５）２Ｍｇ）やジメチル亜鉛（（ＣＨ３）２Ｚｎ）を同時に供給する。
MOCVD, MBE, or HVPE is used for epitaxial growth of the nitride semiconductor films 2 and 3. A combination of these can also be used.
When the MOCVD method is used, a substrate is held on a susceptor in a reaction tube, and a mixed gas of ammonia and one organic metal gas or two or more organic metal gases is supplied to the reaction tube together with a carrier gas such as nitrogen. Then, a desired nitride semiconductor is grown. For example, trimethyl gallium (TMG; (CH 3 ) 3 Ga) or triethyl gallium (TEG; (C 2 H 5 ) 3 Ga) is used as the Ga source, and trimethyl aluminum ((CH 3 ) 3 Al is used as the Al source. ), For example, triethylboron ((C 2 H 5 ) 3 B) is used as a raw material for B, and trimethylindium ((CH 3 ) 3 Ga) is used as a raw material for In, for example.
In the case of imparting conductivity-type impurities to the growing nitride semiconductor, in the case of n-type, for example, silane (SiH 4 ) or silicon chloride (SiCl 4 ) is simultaneously supplied, and in the case of p-type, for example, bis = cyclo Pentadienylmagnesium (C 5 H 5 ) 2 Mg) and dimethyl zinc ((CH 3 ) 2 Zn) are supplied simultaneously.
ＭＢＥ法を用いる場合、Ｇａ蒸発源、Ａｌ蒸発源、Ｉｎ蒸発源、Ｂ蒸発源およびＮ供給源を備えたＭＢＥ装置のチャンバ内に基板を配置し、窒素フラックスとともに１種または２種以上のIII族金属フラックスを基板に照射して、所望の窒化物半導体を成長させる。このとき、ＲＦにより窒素を活性化させ、窒素ラジカルを照射するようにしてもよい（ＲＦ−ＭＢＥ法）。 When the MBE method is used, a substrate is placed in a chamber of an MBE apparatus equipped with a Ga evaporation source, an Al evaporation source, an In evaporation source, a B evaporation source, and an N supply source, and one or more types of III together with a nitrogen flux. The substrate is irradiated with a group metal flux to grow a desired nitride semiconductor. At this time, nitrogen may be activated by RF and irradiated with nitrogen radicals (RF-MBE method).
ＨＶＰＥ法を用いる場合、反応管内のサセプタ上に基板を保持し、Ｇａ、Ａｌ、Ｉｎ、ＢのIII族金属の中の１種または２種以上を反応管に装填し、反応管にＨＣｌガスを導入して塩化金属ガスを生成させ、これとアンモニアガスを反応させて基板上に所望の窒化物半導体を堆積させる。窒素の原料としては、アンモニアに代えヒドラジンなどの他の窒素化合物を用いてもよい。また、III族金属と反応させるハロゲン化水素としては、ＨＣｌに代え、ＨＦ、ＨＢｒまたはＨＩを用いることもできる。 When using the HVPE method, a substrate is held on a susceptor in a reaction tube, one or more of Ga, Al, In, and B group III metals are loaded into the reaction tube, and HCl gas is charged into the reaction tube. Introduced metal chloride gas is generated, and this is reacted with ammonia gas to deposit a desired nitride semiconductor on the substrate. As a raw material of nitrogen, other nitrogen compounds such as hydrazine may be used instead of ammonia. In addition, HF, HBr, or HI can be used in place of HCl as the hydrogen halide to be reacted with the group III metal.
次に、本発明の実施例１を比較例とともに説明する。微傾斜サファイア（０００１）基板を使用し、比較のために、ジャストサファイア（０００１）基板も使用した。膜成長にはRF-ＭＢＥ法を用いた。使われている微傾斜サファイア（０００１）基板のオフ角度を0.5〜2°まで変化させ、最適な基板条件を見出す。
膜成長に先立って、まず、ＭＢＥチャンバ中において窒素プラズマによるサファイア基板の窒化を行う。その時の基板温度は280℃で、窒化時間は２時間までとする。プラズマのパワーは350ワットで、窒素流量を3sccmとした。窒化終了後、基板温度を700℃まで上げ、ＡｌＮ薄膜を成長させそのＡｌＮ薄膜上にＧａＮ薄膜を成長させた。ＡｌＮとＧａＮの成長速度はそれぞれ約0.4μm/hrと0.6μm/hrである。ＡｌＮ薄膜とＧａＮ薄膜の厚みはそれぞれ0.2μｍと1μｍである。
Next, Example 1 of this invention is demonstrated with a comparative example. A slightly inclined sapphire (0001) substrate was used, and a just sapphire (0001) substrate was also used for comparison. The RF-MBE method was used for film growth. Change the off-angle of the vicinal sapphire (0001) substrate used from 0.5 to 2 ° to find optimum substrate conditions.
Prior to film growth, a sapphire substrate is first nitrided with nitrogen plasma in an MBE chamber. The substrate temperature at that time is 280 ° C., and the nitriding time is up to 2 hours. The plasma power was 350 watts and the nitrogen flow rate was 3 sccm. After completion of nitriding, the substrate temperature was raised to 700 ° C., an AlN thin film was grown, and a GaN thin film was grown on the AlN thin film. The growth rates of AlN and GaN are about 0.4 μm / hr and 0.6 μm / hr, respectively. The thicknesses of the AlN thin film and the GaN thin film are 0.2 μm and 1 μm, respectively.
成長したＧａＮ薄膜をX線回折及び透過型電子顕微鏡による断面観察により評価する。図２は、X線回折を示すグラフであって、図２（ａ）、（ｂ）にそれぞれX線回折の対称反射(002)と非対称反射(102)の結果を示す。対称反射(002)の場合、ＧａＮのピーク半値幅が傾斜角度あまり大きく依存せず、100〜200 arcsec(秒角)に留まる。このピーク半値幅は薄膜のモザイク状態を表しており、得られた結果から薄膜のモザイク特性は傾斜角度に対する依存性が小さいと考えられる。一方、非対称反射(102)の場合、ＧａＮのピーク半値幅が傾斜角度に大きく依存している。傾斜角度が0°から2°へと変化すると、ピーク半値幅は約1400から400 arcsecへと狭くなる。このピーク半値幅は薄膜中の転位密度に対応し、ピーク半値幅が狭ければ転位密度が小さいことになる。また、0°と0.5°オフの基板の場合、ピーク半値幅があまり変わらないことがわかる。これは0°と0.5°オフ基板の場合に薄膜表面に単原子層ステップしかなく、マクロステップ（多原子層ステップ）が形成されていないからである。つまりマクロステップの形成が転位密度の低減に大きな役割を果たしているのである。この結論は、次の透過型電子顕微鏡による断面観察の結果からはっきりわかる。 The grown GaN thin film is evaluated by X-ray diffraction and cross-sectional observation with a transmission electron microscope. FIG. 2 is a graph showing X-ray diffraction, and FIGS. 2A and 2B show the results of symmetric reflection (002) and asymmetric reflection (102) of X-ray diffraction, respectively. In the case of symmetrical reflection (002), the peak half-value width of GaN does not depend on the inclination angle so much, and remains at 100 to 200 arcsec (second angle). This peak half-value width represents the mosaic state of the thin film, and it is considered that the mosaic characteristic of the thin film is less dependent on the tilt angle from the obtained results. On the other hand, in the case of asymmetric reflection (102), the peak half-width of GaN greatly depends on the tilt angle. When the tilt angle changes from 0 ° to 2 °, the peak half-value width decreases from about 1400 to 400 arcsec. This peak half width corresponds to the dislocation density in the thin film. If the peak half width is narrow, the dislocation density is small. It can also be seen that the half width of the peak does not change much in the case of the 0 ° and 0.5 ° off substrates. This is because in the case of 0 ° and 0.5 ° off-substrates, there are only monoatomic layer steps on the thin film surface, and no macro steps (polyatomic layer steps) are formed. In other words, the formation of macrosteps plays a major role in reducing the dislocation density. This conclusion can be clearly seen from the results of cross-sectional observation using the following transmission electron microscope.
次に、上記の薄膜の断面を透過型電子顕微鏡(TEM)にて観察した結果について説明する。図３にTEMによる観察像を示す。サンプルは二種類で、図３（ａ）、（ｂ）は、それぞれジャスト基板（オフ角0°）と2.0°オフ基板上に成長したＧａＮ薄膜の断面像である。ジャスト基板上に成長したＧａＮ薄膜中には高い密度の転位（白い線）が成長方向（真上）に走っている。これは従来技術で成長させた薄膜に典型的に現れるものである。しかし、2.0°オフ基板上のＧａＮ薄膜中の転位（白い線）密度は先の0°基板上のＧａＮ薄膜の場合と比べて大きく減少している。特徴的な点は、転位線の伝播方向が二種類あることである。ジャスト基板上のＧａＮ薄膜中において支配的な転位線方向（真上）以外に傾斜方向に走っている転位線が存在している。この傾斜方向に走っている転位線が真上に走っている転位線と相互作用し、転位ループなどを作り真上に伝搬する転位を止める。この新規な原理により、転位密度を大きく低減させることができる。 Next, the result of observing the cross section of the thin film with a transmission electron microscope (TEM) will be described. FIG. 3 shows an observation image by TEM. There are two types of samples. FIGS. 3A and 3B are cross-sectional images of a GaN thin film grown on a just substrate (off angle 0 °) and a 2.0 ° off substrate, respectively. In the GaN thin film grown on the just substrate, high-density dislocations (white lines) run in the growth direction (directly above). This is typical for thin films grown by the prior art. However, the dislocation (white line) density in the GaN thin film on the 2.0 ° off-substrate is greatly reduced compared to the GaN thin film on the 0 ° substrate. A characteristic point is that there are two types of propagation directions of dislocation lines. In the GaN thin film on the just substrate, there exist dislocation lines running in the tilt direction other than the dominant dislocation line direction (directly above). This dislocation line running in the tilt direction interacts with the dislocation line running directly above, thereby creating a dislocation loop and stopping the dislocation propagating directly above. With this novel principle, the dislocation density can be greatly reduced.
以上の結果により、窒化物半導体薄膜中の転位密度低減を実現するには、薄膜表面にマクロステップを形成することが必要条件である。微傾斜基板の必要な傾斜角度は成長方法によって異なるが、ＭＢＥ法による場合には1.0°以上で、MOCVDの場合には0.5°以上であることが必要条件になる。 From the above results, it is necessary to form a macro step on the surface of the thin film in order to reduce the dislocation density in the nitride semiconductor thin film. The required tilt angle of the slightly tilted substrate differs depending on the growth method, but it is necessary that the tilt angle is 1.0 ° or more in the case of MBE and 0.5 ° or more in the case of MOCVD.
本発明の上述した特徴を産業上で活用するものとして、以下のような応用分野が考えられる。
第１に、低転位密度ＧａＮエピタキシャル層を利用し、その上に(Ｉｎ,Ｇａ,Ａｌ)Ｎ/(Ａｌ,Ｇａ)Ｎ量子井戸を作製し、高性能な光デバイス（ＬＥＤとＬＤなど）への応用が可能である。
The following application fields are conceivable as industrial applications of the above-described features of the present invention.
First, a low dislocation density GaN epitaxial layer is used, and an (In, Ga, Al) N / (Al, Ga) N quantum well is fabricated thereon to provide a high-performance optical device (such as LED and LD). Can be applied.
第２に、低転位密度ＧａＮエピタキシャル層を利用し、その上にＧａＮ/(Ａｌ,Ｇａ)Ｎ量子井戸を作製し、サブバンド間遷移(inter-subband transition)を利用した高速な通信用デバイスへの応用が可能である。 Second, a low dislocation density GaN epitaxial layer is used, a GaN / (Al, Ga) N quantum well is fabricated thereon, and a high-speed communication device using inter-subband transition. Can be applied.
第３に、低転位密度ＧａＮエピタキシャル層を利用し、その上に(Ａｌ,Ｇａ)Ｎ/ＧａＮヘテロ構造を作製し、高い二次元電子ガス移動度が期待できる。それにより、高周波、高出力電子デバイスへの応用が可能である。 Third, by using a low dislocation density GaN epitaxial layer and forming an (Al, Ga) N / GaN heterostructure thereon, high two-dimensional electron gas mobility can be expected. Thereby, it can be applied to high-frequency and high-power electronic devices.
１ 微傾斜基板
２ 窒化物半導体膜（バッファ層）
３ 窒化物半導体膜
４ マクロステップ
1 Slightly inclined substrate 2 Nitride semiconductor film (buffer layer)
3 Nitride semiconductor film 4 Macro step
Claims (6)
4. The epitaxial growth of a nitride semiconductor thin film is performed using any of MBE (molecular beam epitaxial growth), MOCVD (metal organic chemical vapor deposition), or HVPE (hydride vapor deposition). 4. The nitride semiconductor crystal growth method according to 4 or 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004243242A JP2006060164A (en) | 2004-08-24 | 2004-08-24 | Nitride semiconductor device and nitride semiconductor crystal growth method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004243242A JP2006060164A (en) | 2004-08-24 | 2004-08-24 | Nitride semiconductor device and nitride semiconductor crystal growth method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2006060164A true JP2006060164A (en) | 2006-03-02 |
Family
ID=36107355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004243242A Pending JP2006060164A (en) | 2004-08-24 | 2004-08-24 | Nitride semiconductor device and nitride semiconductor crystal growth method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2006060164A (en) |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008010446A (en) * | 2006-06-27 | 2008-01-17 | Nec Corp | Semiconductor laser element |
| JP2009147271A (en) * | 2007-12-18 | 2009-07-02 | Tohoku Univ | Substrate manufacturing method and group III nitride semiconductor crystal |
| JP2009224704A (en) * | 2008-03-18 | 2009-10-01 | Sumitomo Electric Ind Ltd | Nitride semiconductor light-emitting device, epitaxial wafer, and method of manufacturing the nitride semiconductor light-emitting device |
| JP2010103578A (en) * | 2006-12-22 | 2010-05-06 | Showa Denko Kk | Method for manufacturing group-iii nitride semiconductor layer |
| WO2013021464A1 (en) * | 2011-08-09 | 2013-02-14 | 創光科学株式会社 | Nitride semiconductor ultraviolet light emitting element |
| WO2014065019A1 (en) * | 2012-10-22 | 2014-05-01 | シャープ株式会社 | Nitride semiconductor light-emitting element |
| CN105742442A (en) * | 2011-08-09 | 2016-07-06 | 创光科学株式会社 | Manufacturing method of nitride semiconductor ultraviolet light emitting component |
| WO2017013729A1 (en) * | 2015-07-21 | 2017-01-26 | 創光科学株式会社 | Nitride semiconductor ultraviolet light-emitting element |
| JP2018037539A (en) * | 2016-08-31 | 2018-03-08 | 旭化成株式会社 | Ultraviolet light emitting element and ultraviolet irradiation module |
| WO2018233950A1 (en) * | 2017-06-19 | 2018-12-27 | Osram Opto Semiconductors Gmbh | SEMICONDUCTOR CHIP COMPRISING INTERNAL INTERIOR BEARINGS SIMILAR TO TERRACES AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP |
| JP2019004178A (en) * | 2018-09-20 | 2019-01-10 | Ｄｏｗａエレクトロニクス株式会社 | Group III nitride semiconductor light emitting device |
| JP2019029607A (en) * | 2017-08-03 | 2019-02-21 | 旭化成株式会社 | Uv light-emitting element and uv light irradiation module |
| WO2019102557A1 (en) * | 2017-11-22 | 2019-05-31 | 創光科学株式会社 | Nitride semiconductor light-emitting element |
| JPWO2021260849A1 (en) * | 2020-06-24 | 2021-12-30 | ||
| WO2021260850A1 (en) * | 2020-06-24 | 2021-12-30 | 創光科学株式会社 | Nitride semiconductor uv light-emitting element and production method therefor |
| CN115084331A (en) * | 2022-04-06 | 2022-09-20 | 南昌大学 | Nitride thin film structure for manufacturing red light Micro-LED |
| TWI881114B (en) * | 2020-07-07 | 2025-04-21 | 日商日機裝股份有限公司 | Nitride semiconductor ultraviolet light emitting element and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5659699A (en) * | 1979-10-17 | 1981-05-23 | Matsushita Electric Ind Co Ltd | Gallium nitride growing method |
| JPH07131068A (en) * | 1993-10-29 | 1995-05-19 | Toyoda Gosei Co Ltd | Nitrogen-group-iii element compound semiconductor light emitting element |
| JPH1174562A (en) * | 1997-06-30 | 1999-03-16 | Nichia Chem Ind Ltd | Nitride semiconductor device |
| JP2000156348A (en) * | 1998-09-16 | 2000-06-06 | Nichia Chem Ind Ltd | Nitride semiconductor substrate and element thereof |
| JP2001160539A (en) * | 1999-09-24 | 2001-06-12 | Sanyo Electric Co Ltd | Forming method for nitride semiconductor device and nitride semiconductor |
-
2004
- 2004-08-24 JP JP2004243242A patent/JP2006060164A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5659699A (en) * | 1979-10-17 | 1981-05-23 | Matsushita Electric Ind Co Ltd | Gallium nitride growing method |
| JPH07131068A (en) * | 1993-10-29 | 1995-05-19 | Toyoda Gosei Co Ltd | Nitrogen-group-iii element compound semiconductor light emitting element |
| JPH1174562A (en) * | 1997-06-30 | 1999-03-16 | Nichia Chem Ind Ltd | Nitride semiconductor device |
| JP2000156348A (en) * | 1998-09-16 | 2000-06-06 | Nichia Chem Ind Ltd | Nitride semiconductor substrate and element thereof |
| JP2001160539A (en) * | 1999-09-24 | 2001-06-12 | Sanyo Electric Co Ltd | Forming method for nitride semiconductor device and nitride semiconductor |
Cited By (49)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008010446A (en) * | 2006-06-27 | 2008-01-17 | Nec Corp | Semiconductor laser element |
| US8492186B2 (en) | 2006-12-22 | 2013-07-23 | Toyoda Gosei Co., Ltd. | Method for producing group III nitride semiconductor layer, group III nitride semiconductor light-emitting device, and lamp |
| JP2010103578A (en) * | 2006-12-22 | 2010-05-06 | Showa Denko Kk | Method for manufacturing group-iii nitride semiconductor layer |
| JP2009147271A (en) * | 2007-12-18 | 2009-07-02 | Tohoku Univ | Substrate manufacturing method and group III nitride semiconductor crystal |
| JP2009224704A (en) * | 2008-03-18 | 2009-10-01 | Sumitomo Electric Ind Ltd | Nitride semiconductor light-emitting device, epitaxial wafer, and method of manufacturing the nitride semiconductor light-emitting device |
| CN105742442A (en) * | 2011-08-09 | 2016-07-06 | 创光科学株式会社 | Manufacturing method of nitride semiconductor ultraviolet light emitting component |
| KR101855053B1 (en) * | 2011-08-09 | 2018-05-04 | 소코 가가쿠 가부시키가이샤 | Nitride semiconductor ultraviolet light emitting element |
| WO2013021464A1 (en) * | 2011-08-09 | 2013-02-14 | 創光科学株式会社 | Nitride semiconductor ultraviolet light emitting element |
| US20140158983A1 (en) * | 2011-08-09 | 2014-06-12 | Soko Kagaku Co., Ltd. | Nitride semiconductor ultraviolet light-emitting element |
| JPWO2013021464A1 (en) * | 2011-08-09 | 2015-03-05 | 創光科学株式会社 | Nitride semiconductor ultraviolet light emitting device |
| EP2747220A4 (en) * | 2011-08-09 | 2015-07-08 | Soko Kagaku Co Ltd | ELEMENT EMITTING ULTRAVIOLET LIGHT WITH A NITRIDE SEMICONDUCTOR |
| US9356192B2 (en) * | 2011-08-09 | 2016-05-31 | Soko Kagaku Co., Ltd. | Nitride semiconductor ultraviolet light-emitting element |
| CN105742442B (en) * | 2011-08-09 | 2018-10-09 | 创光科学株式会社 | The manufacturing method of nitride-based semiconductor ultraviolet ray emitting element |
| US20160240727A1 (en) * | 2011-08-09 | 2016-08-18 | Soko Kagaku Co., Ltd. | Nitride semiconductor ultraviolet light-emitting element |
| CN103733449A (en) * | 2011-08-09 | 2014-04-16 | 创光科学株式会社 | Nitride semiconductor ultraviolet light emitting element |
| KR101859355B1 (en) | 2011-08-09 | 2018-05-18 | 소코 가가쿠 가부시키가이샤 | Nitride semiconductor ultraviolet light emitting element |
| US9502606B2 (en) * | 2011-08-09 | 2016-11-22 | Soko Kagaku Co., Ltd. | Nitride semiconductor ultraviolet light-emitting element |
| JPWO2014065019A1 (en) * | 2012-10-22 | 2016-09-08 | シャープ株式会社 | Nitride semiconductor light emitting device |
| US9450150B2 (en) | 2012-10-22 | 2016-09-20 | Sharp Kabushiki Kaisha | Nitride semiconductor light-emitting element |
| WO2014065019A1 (en) * | 2012-10-22 | 2014-05-01 | シャープ株式会社 | Nitride semiconductor light-emitting element |
| JPWO2017013729A1 (en) * | 2015-07-21 | 2017-10-12 | 創光科学株式会社 | Nitride semiconductor ultraviolet light emitting device |
| TWI617051B (en) * | 2015-07-21 | 2018-03-01 | Soko Kagaku Co Ltd | Nitride semiconductor ultraviolet light emitting element and manufacturing method thereof |
| WO2017013729A1 (en) * | 2015-07-21 | 2017-01-26 | 創光科学株式会社 | Nitride semiconductor ultraviolet light-emitting element |
| US10297715B2 (en) | 2015-07-21 | 2019-05-21 | Soko Kagaku Co., Ltd. | Nitride semiconductor ultraviolet light-emitting element |
| JP2018037539A (en) * | 2016-08-31 | 2018-03-08 | 旭化成株式会社 | Ultraviolet light emitting element and ultraviolet irradiation module |
| WO2018233950A1 (en) * | 2017-06-19 | 2018-12-27 | Osram Opto Semiconductors Gmbh | SEMICONDUCTOR CHIP COMPRISING INTERNAL INTERIOR BEARINGS SIMILAR TO TERRACES AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP |
| CN110915003A (en) * | 2017-06-19 | 2020-03-24 | 欧司朗Oled股份有限公司 | Semiconductor chip having terraced inner steps and method of manufacturing semiconductor chip |
| US11031526B2 (en) | 2017-06-19 | 2021-06-08 | Osram Oled Gmbh | Seminconductor chip having internal terrace-like steps and method for producing a semiconductor chip |
| CN110915003B (en) * | 2017-06-19 | 2023-08-29 | 欧司朗Oled股份有限公司 | Semiconductor chip having terraced inner step portion and method of manufacturing semiconductor chip |
| JP6998146B2 (en) | 2017-08-03 | 2022-01-18 | 旭化成株式会社 | Ultraviolet light emitting element and ultraviolet irradiation module |
| JP2019029607A (en) * | 2017-08-03 | 2019-02-21 | 旭化成株式会社 | Uv light-emitting element and uv light irradiation module |
| WO2019102557A1 (en) * | 2017-11-22 | 2019-05-31 | 創光科学株式会社 | Nitride semiconductor light-emitting element |
| JPWO2019102557A1 (en) * | 2017-11-22 | 2020-01-16 | 創光科学株式会社 | Nitride semiconductor light emitting device |
| CN111373552A (en) * | 2017-11-22 | 2020-07-03 | 创光科学株式会社 | Nitride semiconductor light emitting device |
| US11152543B2 (en) | 2017-11-22 | 2021-10-19 | Soko Kagaku Co., Ltd. | Nitride semiconductor light-emitting element |
| CN111373552B (en) * | 2017-11-22 | 2023-09-05 | 日机装株式会社 | Nitride semiconductor light emitting element |
| JP2019004178A (en) * | 2018-09-20 | 2019-01-10 | Ｄｏｗａエレクトロニクス株式会社 | Group III nitride semiconductor light emitting device |
| JPWO2021260850A1 (en) * | 2020-06-24 | 2021-12-30 | ||
| WO2021260849A1 (en) * | 2020-06-24 | 2021-12-30 | 創光科学株式会社 | Nitride semiconductor uv light-emitting element |
| KR20230002875A (en) * | 2020-06-24 | 2023-01-05 | 소코 가가쿠 가부시키가이샤 | Nitride semiconductor ultraviolet light emitting device and manufacturing method thereof |
| CN115699341A (en) * | 2020-06-24 | 2023-02-03 | 创光科学株式会社 | Nitride semiconductor ultraviolet light emitting element |
| WO2021260850A1 (en) * | 2020-06-24 | 2021-12-30 | 創光科学株式会社 | Nitride semiconductor uv light-emitting element and production method therefor |
| JPWO2021260849A1 (en) * | 2020-06-24 | 2021-12-30 | ||
| CN115699341B (en) * | 2020-06-24 | 2025-04-29 | 日机装株式会社 | Nitride semiconductor ultraviolet light emitting element |
| US12324279B2 (en) | 2020-06-24 | 2025-06-03 | Nikkiso Co., Ltd. | Nitride semiconductor ultraviolet light-emitting element |
| KR102833536B1 (en) | 2020-06-24 | 2025-07-11 | 니기소 가부시키가이샤 | Nitride semiconductor ultraviolet emitting device and its manufacturing method |
| US12419139B2 (en) | 2020-06-24 | 2025-09-16 | Nikkiso Co., Ltd. | Nitride semiconductor ultraviolet light-emitting element and production method therefor |
| TWI881114B (en) * | 2020-07-07 | 2025-04-21 | 日商日機裝股份有限公司 | Nitride semiconductor ultraviolet light emitting element and manufacturing method thereof |
| CN115084331A (en) * | 2022-04-06 | 2022-09-20 | 南昌大学 | Nitride thin film structure for manufacturing red light Micro-LED |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4743214B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP5705399B2 (en) | Group III nitride materials with low dislocation density and methods related to the materials | |
| JP3139445B2 (en) | GaN-based semiconductor growth method and GaN-based semiconductor film | |
| JP5244487B2 (en) | Gallium nitride growth substrate and method for manufacturing gallium nitride substrate | |
| JPH11145516A (en) | Method for manufacturing gallium nitride-based compound semiconductor | |
| JP2006060164A (en) | Nitride semiconductor device and nitride semiconductor crystal growth method | |
| CN106233471A (en) | The semi-polarity GaN layer of the nitrogen polarity in Sapphire Substrate and device | |
| JP3196833B2 (en) | Method of growing III-V compound semiconductor and method of manufacturing semiconductor light emitting device using this method | |
| US20020100412A1 (en) | Low dislocation buffer and process for production thereof as well as device provided with low dislocation buffer | |
| JP5638198B2 (en) | Laser diode orientation on miscut substrates | |
| JP2005072561A (en) | Epitaxial substrate, method for manufacturing epitaxial substrate, method for suppressing warpage of epitaxial substrate, and semiconductor multilayer structure using epitaxial substrate | |
| JP2005210084A (en) | Epitaxial substrate, semiconductor laminate structure, dislocation reduction method, and substrate for epitaxial formation | |
| CN100524621C (en) | Method for growing crystalline gallium nitride-based compound and semiconductor device comprising gallium nitride-based compound | |
| JP3934320B2 (en) | GaN-based semiconductor device and manufacturing method thereof | |
| JP2012204540A (en) | Semiconductor device and method of manufacturing the same | |
| JP2011216549A (en) | METHOD OF MANUFACTURING GaN-BASED SEMICONDUCTOR EPITAXIAL SUBSTRATE | |
| JP4679810B2 (en) | EPITAXIAL SUBSTRATE, SEMICONDUCTOR LAMINATED STRUCTURE, EPITAXIAL SUBSTRATE MANUFACTURING METHOD, AND METHOD FOR SUPPRESSING PIT GENERATION ON Epitaxial Substrate Surface | |
| JP2010267798A (en) | Manufacturing method of semiconductor light emitting device | |
| US11021789B2 (en) | MOCVD system injector for fast growth of AlInGaBN material | |
| JP2014154591A (en) | METHOD OF MANUFACTURING GaN THIN FILM AND GaN THIN FILM | |
| US8779437B2 (en) | Wafer, crystal growth method, and semiconductor device | |
| JP4140595B2 (en) | Gallium nitride compound semiconductor | |
| JP4158760B2 (en) | GaN-based semiconductor film and method for manufacturing the same | |
| JP4172444B2 (en) | Method for producing gallium nitride compound semiconductor | |
| KR20220123780A (en) | Process for production of thin film comprising multiple quantum well structure, thin film comprising multiple quantum well structure and semiconductor device comprising the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20061013 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20100916 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20101005 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20101203 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20110426 |