JP2006060080A - Multilayer capacitor - Google Patents

Abstract

A multilayer capacitor capable of holding a large capacitance while suppressing the occurrence of delamination is provided.
First and second internal electrodes 3 and 4 of a multilayer capacitor are formed by a plurality of strip-shaped conductors 3a and 3b arranged in parallel in a stripe shape with a strip-shaped blank portion therebetween. The dielectric layers adjacent to each other vertically between the strip conductors are bonded to each other, and further, from the upper surface to the lower surface of the strip conductors along two side surfaces opposed to each other among the side surfaces of the strip conductors adjacent in the juxtaposed direction. Lengths L ₁ and L _2, and distance D ₁ between the upper surfaces of adjacent strip-shaped conductors and distance D ₂ between the lower surfaces are related to (L ₁ + L ₂ ) ≧ 2D ₁ , (L ₁ + L ₂ ) ≧ 2D ₂ is set so as to satisfy at least one of the _two .
[Selection] Figure 4

Description

  The present invention relates to the structure of a multilayer capacitor.

  As a conventional multilayer capacitor, for example, as shown in FIG. 6, a rectangular dielectric layer 22 is laminated with first internal electrodes 23 and second internal electrodes 24 intervening therebetween. A structure having a structure in which external terminal electrodes 25 and 26 electrically connected to the first internal electrode 23 and the second internal electrode 24 are attached to the end face of the multilayer body 21 is known. The capacitor is formed as a capacitor by applying a predetermined voltage to the first internal electrode 23 and the second internal electrode 24 and forming a predetermined capacitance in the dielectric layer 22 disposed between the internal electrodes. Function.

  When such a multilayer capacitor is mounted on a wiring board such as a mother board, a conductive adhesive such as solder is interposed between the external capacitor electrodes 25 and 26 and the connection pads of the wiring board. After being placed on the wiring board as described above, the soldering or the like is heated and melted at a high temperature, whereby the internal electrodes 23 and 24 of the multilayer capacitor are connected to the external terminal electrodes 25 and 26 and the solder and the like. And electrically connected to the wiring conductor of the wiring board.

  However, in the conventional multilayer capacitor described above, since the adhesion between the dielectric layer 22 and the internal electrode is weak, there is a problem that delamination occurs between the dielectric layer and the internal electrode when the multilayer body 21 is fired. was there. Therefore, in order to suppress the occurrence of such delamination, by dividing the internal electrode in the same plane into a plurality of internal electrodes, the junction area between the dielectric layers is increased, thereby the dielectric layers and the internal electrodes Multilayer capacitors that are designed to prevent delamination that occurs during this period have been studied. However, when the internal electrodes in the same plane are divided into a plurality of parts, if the cross section of the divided internal electrodes is rectangular, the facing area between the internal electrodes decreases, and a desired capacitance cannot be obtained. A defect is induced.

  The present invention has been devised in view of the above drawbacks, and an object thereof is to provide a multilayer capacitor capable of ensuring a large capacitance while effectively preventing the occurrence of delamination.

In the multilayer capacitor of the present invention, a first internal electrode and a second internal electrode are alternately arranged between adjacent dielectric layers in a multilayer body formed by stacking a plurality of dielectric layers to form a rectangular parallelepiped shape. The first external terminal electrode electrically connected to the first internal electrode is disposed on one side surface of the multilayer body, and the second internal electrode is disposed on the other side surface disposed in parallel with the one side surface. In a multilayer capacitor in which a second external terminal electrode to be electrically connected is deposited, the first internal electrode and the second internal electrode are arranged in parallel in a striped manner with a band-shaped blank portion therebetween. The band-shaped conductors have side surfaces that are convexly curved and have two side surfaces that are opposed to each other among the side surfaces of the band-shaped conductors adjacent to each other in the juxtaposition direction. From top to bottom of the strip-shaped conductor along Characterized by a L _1, L _2, the distance D ₁ of the between the upper surface of the adjacent strip _conductors, the distance D ₂ and the following relationships between the underside (1), that it has set so as to satisfy at least one of (2) It is what.

(L ₁ + L ₂ ) ≧ 2D ₁ (1)
(L ₁ + L ₂ ) ≧ 2D ₂ (2)
The multilayer capacitor of the present invention is characterized in that the radius of curvature R of the side surface of the strip conductor and the thickness T of the strip conductor are set so as to satisfy the following relational expression (3).

(T × 1/2) ≧ R ≧ (T × 1/20) (3)
Furthermore, the multilayer capacitor of the present invention is characterized in that the top of the side surface of the strip conductor is set at a height position of (T × 1/5) to (T × 4/5) from the bottom surface of the strip conductor. is there.

According to the multilayer capacitor of the present invention, the first internal electrode and the second internal electrode are each formed by a plurality of strip-shaped conductors arranged in a stripe pattern with a strip-shaped blank portion therebetween, and these strip-shaped capacitors are formed. The lengths L ₁ , L ₂ from the upper surface to the lower surface of the belt-shaped conductor along the two side surfaces of the side surfaces of the strip-shaped conductors adjacent to each other in the juxtaposed direction are formed on the side surfaces of the conductor. Since the distance D ₁ between the upper surfaces of the adjacent strip-shaped conductors and the distance D ₂ between the lower surfaces satisfy the at least one of the following relational expressions (1) and (2), the dielectric layer and the internal electrode While effectively preventing the occurrence of delamination between them, the opposing area between the internal electrodes can be made large, and a large capacitance can be secured.

(L ₁ + L ₂ ) ≧ 2D ₁ (1)
(L ₁ + L ₂ ) ≧ 2D ₂ (2)
That is, since each of the first and second internal electrodes is formed by a plurality of strip-shaped conductors arranged in a stripe shape with a strip-shaped blank portion therebetween, the internal electrode is formed in the blank portion. The sandwiched dielectric layers are joined together, and the dielectric layers come into close contact with each other at this portion. As a result, the adhesive force between the internal electrode and the dielectric layer sandwiching the internal electrode also increases, so that delamination between the dielectric layer and the internal electrode can be suppressed. Further, the length L ₁ from the upper surface to the lower surface of the belt-shaped conductor along the two side surfaces facing each other among the side surfaces of the belt-shaped conductors adjacent to each other in the juxtaposed direction is formed on the side surface of the belt-shaped conductor. Since the distance D ₁ between the upper surfaces of the adjacent strip-shaped conductors and the distance D ₂ between the lower surfaces of L ₂ are set so as to satisfy at least one of the relational expressions (1) and (2), the cross section is rectangular. Compared to the case of forming a divided internal electrode having a shape, the opposing area of the internal electrodes arranged vertically opposite to each other through the dielectric layer is a portion from the upper surface of the band-shaped conductor to the top of the side surface of the band-shaped conductor and / or the band-shaped conductor. This increases the amount of bending at the portion from the lower surface to the top of the side surface of the belt-like conductor, and a relatively large capacitance can be secured.

  Further, according to the multilayer capacitor of the present invention, the curvature radius R of the side surface of the strip conductor and the thickness T of the strip conductor satisfy the relational expression (T × 1/2) ≧ R ≧ (T × 1/20). By setting, there are almost no corners at the portion where the dielectric layer and the strip conductor are in contact. As a result, when mounting the multilayer capacitor on the wiring board, the solder interposed between the external terminal electrode of the multilayer capacitor and the connection pad of the wiring board is concentrated at the corner of the multilayer capacitor when heated at a high temperature. The easy thermal stress is relieved and the occurrence of cracks can be effectively suppressed.

  Furthermore, according to the multilayer capacitor of the present invention, the top of the side surface of the strip conductor is set at a height position of (T × 1/5) to (T × 4/5) from the bottom surface of the strip conductor. A relatively large curvature portion can be obtained at the portion where the strip-shaped conductor contacts, and when mounting the multilayer capacitor on the wiring board, solder or the like interposed between the external terminal electrode of the multilayer capacitor and the connection pad of the wiring board When this is heated at a high temperature, the thermal stress that tends to concentrate on the corners of the multilayer capacitor is further relaxed, and the generation of cracks can be further suppressed.

  Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is an external perspective view of a multilayer capacitor according to an embodiment of the present invention, with a part cut away, FIG. 2 is a cross-sectional view taken along line AA ′ of the multilayer capacitor in FIG. 1, and FIG. FIG. 4 is an enlarged view of a portion C shown in FIG. 3.

  The multilayer capacitor shown in FIG. 1 forms a substantially rectangular parallelepiped laminated body 1 by laminating a plurality of rectangular dielectric layers 2, and each dielectric layer 2-2 is formed inside the laminated body 1. 2, the first internal electrode 3 and the second internal electrode 4 are alternately interposed in a state of being partially opposed to each other, and the first internal electrode 3 is electrically connected to both ends of the laminate 1. The first external terminal electrode 5 connected to the second internal electrode 4 and the second external terminal electrode 6 electrically connected to the second internal electrode 4 are deposited and formed.

  The dielectric layer 2 is formed to a thickness of 1 μm to 3 μm per layer by a dielectric material mainly composed of, for example, barium titanate, calcium titanate, strontium titanate, and the like. For example, the laminated body 1 is formed by laminating only 70 to 600 layers.

  For example, when the dielectric layer 2 is made of a dielectric material mainly composed of barium titanate, an appropriate organic solvent, glass frit, organic binder, or the like is added to and mixed with the barium titanate powder. In addition, this is formed into a ceramic green sheet having a predetermined shape and thickness by a conventionally known doctor blade method or the like, and then a predetermined number of ceramic green sheets are obtained by a conventionally known green sheet laminating method or the like. The ceramic green sheet laminate is formed by laminating and pressing only, and finally the laminate is produced by firing at a temperature of 1100 ° C. to 1400 ° C., for example. In addition, the shrinkage | contraction rate accompanying baking of the ceramic green sheet used in this process is set to about 10%-20%, for example.

  On the other hand, the first internal electrode 3 and the second internal electrode 4 interposed between the dielectric layers are made of a conductive material whose main component is nickel, copper, silver, or a composite material thereof, for example, When the outer dimensions are 2 mm × 2 mm, the thickness per layer is set to 0.5 μm to 2.0 μm.

  As shown in FIG. 2, the first internal electrode 3 is composed of a plurality of strip-like conductors 3a to 3g arranged in stripes via a strip-like blank portion 7, and one end of each strip-like conductor 3a to 3g. Is connected to the external terminal electrode 6 and the other end is open. Similarly to the first internal electrode 3, the second internal electrode 4 is composed of a plurality of strip-shaped conductors 4 a to 4 g (not shown) arranged in parallel in a strip shape via a strip-shaped blank portion. One end of each of the strip conductors 4a to 4g is connected to the external terminal electrode 5, and the other end is open. Each of the strip conductors constituting the first and second internal electrodes has a substantially rectangular planar shape. Moreover, the strip | belt-shaped conductors 3a-3g which comprise the 1st internal electrode 3, and the strip | belt-shaped conductors 4a-4g which comprise the 2nd internal electrode 4 are arrange | positioned so that it may each have a region which opposes via a dielectric material layer. ing. The number of these strip conductors can be conveniently changed depending on the size and material of the multilayer capacitor, and is not particularly limited.

  Between the strip-shaped conductors adjacent to each other in the juxtaposed direction (between 3a and 3b, between 3b and 3c,..., Between 4a and 4b, between 4b and 4c,...), An internal electrode is sandwiched. The dielectric layer 2 is embedded and filled with a dielectric. As a result, the dielectric layers sandwiching the internal electrode are joined to each other in the blank portion 7, and the dielectric layers are strongly adhered to each other at this portion. As a result, the adhesive force between the internal electrode and the dielectric layer 2 sandwiching the internal electrode also increases, so that delamination between the dielectric layer 2 and the internal electrode can be suppressed.

Next, the relationship between the strip-shaped conductors adjacent in the juxtaposed direction will be described in detail. In addition, although the relationship between the strip | belt-shaped conductors 3a-3b is described here as an example, it has the relationship similar to what is described below also between the other strip | belt-shaped conductors adjacent to a parallel arrangement direction. FIG. 4 is an enlarged cross-sectional view of the side portions of the strip-like conductors 3a and 3b, and corresponds to a portion C in FIG. As shown in FIG. 4, the intersection between the upper surface and the side surface of the strip-shaped conductor 3a is E ₁ , the top of the side surface of the strip-shaped conductor 3a is F ₁ , the intersection between the lower surface and the side surface of the strip-shaped conductor 3a is G ₁ , The thickness is T ₁ , the curvature radius of the side surface of the strip-shaped conductor 3a is R ₁ , and the length of the side surface from the intersection point E ₁ through the apex F ₁ to the intersection point G ₁ is L ₁ . On the other hand, like the strip conductor 3a also strip conductor 3b, the intersection of the upper and side surfaces, the top sides, the intersection between the lower surface and the side surface, the thickness, E ₂ of curvature of the side surface radii, _{respectively,} F _2, G ₂ , T ₂ , R _2, and the length of the side surface from the intersection E ₂ through the apex F ₂ to the intersection G ₂ is L ₂ . The distance between the upper surfaces of the strip conductors 3a and 3b is D ₁ , and the distance between the lower surfaces of the strip conductors 3a and 3b is D ₂ . Incidentally, the strip conductors 3a, refers to the distance between the intersection point _E 1 -E ₂ of the distance _{D 1} of the inter upper surface of the 3b, strip conductors 3a, between the intersection point _G 1 -G ₂ is a distance _{D 2} between the lower surface of the 3b Refer to distance.

A blank portion 7 is formed between the strip-like conductors 3a and 3b, and a dielectric filled with the dielectric layer 2 sandwiching the internal electrode 3 is present in the blank portion 7. Then, the strip conductor, with its side surface forms a cross-sectional convex curved shape, the distance D ₁ of the _inter-top, and the distance D ₂ between the lower surface, the strip conductors 3a, the top surface along the side surface of the 3b to the lower surface the relative lengths _L 1, _{L 2,} the following equation (1), are set so as to satisfy (2).

(L ₁ + L ₂ ) ≧ 2D ₁ (1)
(L ₁ + L ₂ ) ≧ 2D ₂ (2)
As a result, the opposing area of the internal electrodes disposed vertically opposite to each other through the dielectric layer is larger than the case where a divided internal electrode having a rectangular cross section is formed, from the upper surface of the strip conductor to the top of the side surface of the strip conductor. Since the portion and / or the portion extending from the lower surface of the strip conductor to the top of the side surface of the strip conductor is increased, a relatively large capacitance can be secured.

  When the strip conductors 3a and 3b do not satisfy any of the above relational expressions (1) and (2), the surface area of the internal electrode for obtaining the capacitance is smaller than when the divided internal electrode having a rectangular cross section is formed. Therefore, a desired capacitance cannot be secured.

Further, the curvature radii R ₁ and R ₂ of the side surfaces of the strip conductors 3a and 3b and the thicknesses T ₁ and T _{2 of} the strip conductors 3a and 3b are set to satisfy the following relational expression (3).

(T × 1/2) ≧ R ≧ (T × 1/20) (3)
In the present embodiment, R = (T × 1/2) is set. By setting the side surfaces of the strip conductors 3a and 3b to a curvature radius satisfying the relational expression (3), there are almost no corners at the portion where the dielectric layer and the strip conductor are in contact. As a result, when mounting the multilayer capacitor on the wiring board, the solder interposed between the external terminal electrode of the multilayer capacitor and the connection pad of the wiring board is concentrated at the corner of the multilayer capacitor when heated at a high temperature. The easy thermal stress is relieved and the generation of cracks can be effectively suppressed.

When the curvature radii R ₁ and R _{2 of the} side faces of the strip conductor do not satisfy the above relational expression (3), that is, less than 1/20 times the thickness T ₁ and T ₂ of the strip conductor, the intersection points E ₁ and E ₂ , G ₁ and G ₂ do not have extreme corners but have minute corners. Therefore, the thermal stress applied to the multilayer capacitor when the solder is heated at a high temperature after being placed on the wiring board. Concentrates on this corner, and cracks are likely to occur starting from this portion. On the other hand, when the curvature radii R ₁ and R ₂ of the side faces of the strip conductors exceed 1/2 times the thicknesses T ₁ and T ₂ of the strip conductors, the intersections E ₁ , G ₁ , E ₂ , and G ₂ of the strip conductors are obtained. Since corners are generated, cracks are also likely to occur starting from the corners.

Further, if the top portions F ₁ and F ₂ on the side surfaces of the strip-shaped conductor are set so as to be located at a height of (T × 1/5) to (T × 4/5) from the bottom surface of the strip-shaped conductor, they are placed on the wiring board. Then, the concentration of stress due to heat generated when the solder or the like is heated at a high temperature can be further relaxed, and the generation of cracks can be further suppressed. Therefore, it is preferable to set so that the top portions F ₁ and F ₂ are located at a height of T / 5 to 4T / 5 from the lower surface of the strip-shaped conductor.

  In the first internal electrode 3 and the second internal electrode 4 described above, first, a metal plating film deposited by electrolytic plating on the main surface of the transfer support is formed by striped strip-shaped conductors 3a to 3g and 4a to 4g. Etching is performed to obtain a shape, and the resulting striped metal plating film is further etched to process the side surface into a convex curved surface. The metal plating film thus obtained is transferred from the support for transfer to the ceramic green sheet, and a predetermined number of such ceramic green sheets are laminated, and then the ceramic green sheet laminate is fired and simultaneously the metal plating film is fired. As a result, the first internal electrode 3 and the second internal electrode 4 are formed.

  On the other hand, the external terminal electrodes 5 and 6 provided at both ends of the multilayer body 1 are connected to the connection pads of the wiring board via a conductive adhesive such as solder when the multilayer capacitor is mounted on the wiring board such as a mother board. The terminal 1 functions as an externally connected terminal and is applied with a conductor paste for the external terminal electrode on both ends of the laminate 1 and fired. Further, for example, solder such as nickel or gold It is formed by depositing a metal having good wettability to a predetermined thickness by a conventionally known electrolytic plating method or the like.

  The multilayer capacitor having the above-described structure applies a predetermined voltage to the first internal electrode 3 and the second internal electrode 4, and the first internal electrode 3-the second internal electrode 3-2 which are arranged to face each other via the dielectric layer 2. It functions as a capacitor by forming a predetermined capacitance between the two internal electrodes 4.

  The present invention is not limited to the above-described embodiments, and various changes and improvements can be made without departing from the scope of the present invention.

In the embodiment described above, the case where the side surface shape is all curved has been described, but the shape of the side surface is not limited to this, the cross section is convex, and the relational expression (1) described above, Any shape may be used as long as at least one of (2) is satisfied. FIG. 5 is an enlarged view of part C of FIG. 3 in another embodiment of the present invention, in which the curvature radius R of the side surface of the strip conductor is set to R = T × (1/3) with respect to the thickness T of the strip conductor. It is. Side of the strip conductor 3a is made of a linear surface connecting the curved and the two curves of radius of curvature R ₄ in contact with the curved surface and the conductor lower surface of radius of curvature R ₃ in contact with the conductor upper surface, and these curved and straight surfaces to each of the intersections between the top _F 3, _{F 4.} Also, the intersection of the upper surface of the strip-shaped conductor 3a and the curved surface is E ₁ , the intersection of the lower surface of the strip-shaped conductor 3a and the curved surface is G ₁ , and the side surface from the intersection E ₁ to the intersection G ₁ through the apexes F ₃ and F ₄ the length and _{L 3.} The strip-shaped conductor 3b also has the same side shape as that of the strip-shaped conductor 3a, and has the same sign R ₅ , R ₆ , F ₅ , E ₂ , G ₂ , F ₅ , F ₆ , L ₄ . Also in this embodiment, the same effect as the above-described embodiment can be obtained by setting so as to satisfy at least one of the relational expressions of (L ₃ + L ₄ ) ≧ 2D ₁ and (L ₃ + L ₄ ) ≧ 2D _2. It is done.

  In the above-described embodiment, a conductor material containing a metal as a main component is used as the material of the internal electrode, but an internal electrode containing ceramic fine particles can be used instead.

  Further, in the above-described embodiment, the strip conductor constituting the internal electrode is formed by transfer of the metal plating film. However, the method of forming the strip conductor is not limited to this, and for example, a thin film such as ion plating, sputtering, chemical vapor deposition, etc. You may produce by the formation method.

  In the above-described embodiment, the metal plating film is etched to process the side surface into a convex curved surface. Instead, the potential is applied to the conductor side surface by applying a potential so that the metal plating film can be dissolved. A convex curved surface may be formed.

  Furthermore, in the above-described embodiment, the internal electrode is formed of a metal plating film, but instead of this, it may be formed by printing using a paste in which metal powder, a solvent and a resin are mixed.

  In the above-described embodiment, the case where a single multilayer capacitor is manufactured alone has been described as an example, but instead of this, a so-called 'multiple picking' technique is adopted to cut out from a large-sized multilayer body. It goes without saying that a plurality of multilayer capacitors may be obtained simultaneously by firing a plurality of individual pieces.

  Furthermore, the dielectric layer outside the two internal electrodes in the thickness direction of the multilayer capacitor may be formed using a dielectric material different from the dielectric layer between the internal electrodes.

1 is an external perspective view of a multilayer capacitor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the multilayer capacitor of FIG. 1 taken along the line AA ′. FIG. 2 is a cross-sectional view of the multilayer capacitor of FIG. 1 taken along the line BB ′. It is an enlarged view of the C section shown in FIG. It is an expanded sectional view of other embodiments of the present invention. It is sectional drawing of the conventional multilayer capacitor.

Explanation of symbols

1 ... laminate 2 ... dielectric layer 3 ... first internal electrode 4 ... second internal electrodes 5 and 6 ... external terminal electrodes E _{1, E} 2 ... strip conductor intersection of the upper surface F _{1, F} 2 · · · vertex G ₁ strip conductor, _G 2 · · · strip conductor underside of intersection _{D 1,} D 2 ··· between the upper surface of the strip conductor, a distance L ₁ between the lower surface, L ₂ ... Length of strip-shaped conductor side surface R ₁ , R ₂ ... Radius of curvature of strip-shaped conductor T ₁ , T ₂ ... Thickness of strip-shaped conductor

Claims (3)

In the laminate formed by laminating a plurality of dielectric layers to form a rectangular parallelepiped, the first internal electrode and the second internal electrode are alternately interposed between adjacent dielectric layers, and the laminate A first external terminal electrode electrically connected to the first internal electrode on one side surface and a second external electrode electrically connected to the second internal electrode on another side surface arranged in parallel with the one side surface. 2 In a multilayer capacitor formed by attaching external terminal electrodes,
The first internal electrode and the second internal electrode are each composed of a plurality of strip-shaped conductors arranged in stripes with a strip-shaped blank portion therebetween, and the side surfaces of the strip-shaped conductors are convex in cross section. And the lengths L ₁ and L ₂ from the upper surface to the lower surface of the strip conductors along two side surfaces facing each other among the side surfaces of the strip conductors adjacent to each other in the juxtaposed direction, and the adjacent strip shapes A multilayer capacitor, wherein the distance D ₁ between the upper surfaces of the conductors and the distance D ₂ between the lower surfaces are set so as to satisfy at least one of the following relational expressions (1) and (2).
(L ₁ + L ₂ ) ≧ 2D ₁ (1)
(L ₁ + L ₂ ) ≧ 2D ₂ (2) 2. The multilayer capacitor according to claim 1, wherein a side surface of the strip conductor is curved, and a radius of curvature R and a thickness T of the strip conductor are set to satisfy the following relational expression (3): .
(T × 1/2) ≧ R ≧ (T × 1/20) (3) The top part of the said strip | belt-shaped conductor side surface is set to the height position of (Tx1 / 5)-(Tx4 / 5) from the strip | belt-shaped conductor lower surface, The Claim 1 or Claim 2 characterized by the above-mentioned. Multilayer capacitor.

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