JP2006049791A - Semiconductor element and semiconductor element mounting board on which the semiconductor element is mounted - Google Patents

Abstract

The present invention has been devised in view of the above problems, and an object of the present invention is to provide a semiconductor element capable of suppressing the occurrence of cracks and peeling at the joint between a lower bump and an upper bump.
A base metal layer 3 formed on a semiconductor substrate 1, a lower layer bump 5x formed on the base metal layer 3, an upper layer bump 5y formed on the lower layer bump 5x, and a lower layer bump 5x are covered. a semiconductor device comprising a resist layer 7 for, the top layer bumps 5y columnar portion 5y ₁ which is embedded in the substantially resist layer 7, the bump exposed portion 5y ₂ formed on the columnar portion 5y ₁ Consists of.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor element such as a flip chip type IC mounted on a circuit board by face-down bonding, and a semiconductor element mounting substrate on which the semiconductor element is mounted.

  2. Description of the Related Art Conventionally, in a semiconductor device mounting board on which an IC is mounted, the IC is face-down bonded to the upper surface of the circuit board having a circuit pattern, that is, the IC is circuitd with the integrated circuit forming surface of the IC facing the circuit board. Mounting on a substrate is performed.

  An IC used for this face-down bonding is called a flip-chip type IC and generally has its terminals connected to a circuit pattern on a circuit board via a conductive material such as solder.

  As a semiconductor element such as a flip-chip IC, solder bumps 25 are selectively formed on a plurality of base metal layers 23 made of nickel or the like deposited on one main surface of a semiconductor substrate 21 provided with an integrated circuit. The thing of the structure which is made is known. When such semiconductor elements are mounted on a circuit board, they are placed in a reflow furnace with the semiconductor elements placed on the circuit board so that the solder bumps 25 face the corresponding circuit patterns on the circuit board. Heat treatment. As a result, the solder bumps 25 are melted, and the solder bumps 25 of the semiconductor element are bonded to the circuit pattern on the circuit board.

  By the way, the reliability of solder bonding when the above-described semiconductor element is mounted on a circuit board largely depends on the height of the solder bump 25, and it is generally preferred that the solder bump 25 be higher.

  Therefore, as shown in FIG. 4, the solder bumps 25 are formed in a two-layer structure to increase the height thereof. As such a solder bump 25, one composed of a spherical lower layer bump 25 x formed on the base metal layer 23 and a spherical upper layer bump 25 y formed on the lower layer bump 25 x is known. . The lower bump 25x is covered with a resist layer 27 on the surrounding surface other than the top.

  For such solder bump 25, first, a lower bump 25x is formed in a spherical shape at a predetermined position of the base metal layer 23, and then a liquid precursor of a resist layer 27 is applied so as to cover the lower bump 25x and cured. Further, the resist layer 27 and the upper part of the lower bump 25x are ground so that the upper part of the lower bump 25x is exposed, and a spherical upper bump 25y is formed on the exposed lower bump 25x.

Since both the lower layer bump 25x and the upper layer bump 25y are substantially spherical, the joint between these spherical bumps has a constricted shape, and the applied resist layer 27 is formed of such a solder bump 25. Corresponding to the outer shape, the resist layer 27 has a wedge shape in which the tip of the resist layer 27 pierces the joint between the lower bump 25x and the upper bump 25y.
JP 2001-244372 A

  Incidentally, since the volume expansion coefficients of the solder bump 25 and the resist layer 27 are generally different, the ambient temperature at which the semiconductor element mounting substrate on which the semiconductor element is mounted is exposed at the joint between the lower bump 25x and the upper bump 25y. It will be affected by various changes.

  For example, when this semiconductor element mounting substrate is placed in a low temperature environment, the resist layer 27 has a volume expansion coefficient larger than that of the solder bump 25, so that the surrounding resist layer 27 tightens the lower bump 25x. This produces thermal stress that presses against

  However, at the joint portion of the solder bump 25, as described above, since the tip of the resist layer 27 is wedge-shaped so as to pierce the joint portion, the joint portion includes the resist layer 27 and the lower layer bump 25x. As a result, it is subjected to a greater stress than other portions that come into contact with each other.

  In particular, when a semiconductor element is manufactured by grinding the upper surface of the resist layer 27 and the upper surface of the lower layer bump 25x so that the lower layer bump 25x is exposed from the resist layer 27, the tip of the resist layer 27 becomes sharp, and the joint portion is formed. The stress received is greater.

  The semiconductor element is mounted on the circuit board K by connecting the above-described upper layer bump 25y to the pad portion p formed on the upper surface of the circuit board K. When the environmental temperature to which the semiconductor element mounting substrate is exposed changes, the expansion and contraction of each substrate varies depending on the difference in volume expansion coefficient between the circuit substrate K and the semiconductor substrate 21, and as a result, the lower bump 25 x is pulled to the semiconductor substrate 1. Since the upper layer bump 25y is pulled by the circuit board K, the lower layer bump 25x and the upper layer bump 25y receive reverse stress, that is, shear stress, in the solder bump.

  Further, after the semiconductor element is mounted on the circuit board K, the sealing resin f is filled between the resist layer 27 and the circuit board K. Thus, the lower bumps 25x are sealed with the resist layer 27, while the upper bumps 25y are sealed with the sealing resin f. In such a solder bump 25, the joint between the lower layer bump 25x and the upper layer bump 25y exists in substantially the same plane as the contact interface between the resist layer 27 and the sealing resin f. When a shear stress is generated between the resist layer 27 and the sealing resin f in accordance with the change in the volume expansion coefficient, the shear stress is concentrated at the joint between the lower bump 25x and the upper bump 25y. It becomes.

  When the semiconductor element mounting substrate on which the semiconductor element is mounted repeats the above-described temperature cycle with the passage of time, and various stress changes are repeated, cracks or peelings occur at the joint between the lower bump 25x and the upper bump 25y. There was a problem that it entered.

  Further, since the shape of the joint between the lower bump 25x and the upper bump 25y described above is confined, cracks due to metal fatigue may occur in the joint when such a temperature cycle is repeated.

  The present invention has been devised in view of the above problems, and an object thereof is to suppress the occurrence of cracks and peeling at the joint between the lower layer bump 25x and the upper layer bump 25y.

  The semiconductor element of the present invention is a semiconductor element comprising a base metal layer formed on a semiconductor substrate, a lower bump formed on the lower metal layer, and an upper bump formed on the lower bump. The lower bump is coated with a resist layer on the surface other than the joint with the base metal layer and the joint with the upper bump, and the upper bump is a columnar portion formed at the joint with the lower bump. And a bump exposed portion formed on the columnar portion, and the columnar portion is substantially embedded in the resist layer.

  A semiconductor element mounting board of the present invention is provided by providing a pad part for mounting the semiconductor element according to claim 1 on a circuit board, and bonding the pad part and an upper bump of the semiconductor element. The semiconductor element is mounted on the circuit board.

  The semiconductor element mounting board of the present invention is characterized in that a sealing resin is filled in a gap between the circuit board and the semiconductor element.

  According to the semiconductor element of the present invention, the semiconductor element mounting substrate on which the semiconductor element is mounted is exposed to repeated environmental temperature changes, and the resist layer is formed in a lower layer due to the difference in volume expansion coefficient between the resist layer and the solder bump. Even if the stress that presses the bumps is repeated, the resist layer that comes into contact with the joint is not sharply pointed, but has a shape that makes surface contact with almost the entire side surface of the columnar part of the upper bump. The pressing stress does not increase locally, and therefore does not promote the occurrence of cracks or peeling of the upper layer bumps at the joint.

  In addition, when a semiconductor element mounting substrate on which a semiconductor element is mounted is exposed to repeated environmental temperature changes, and the expansion and contraction amount of each substrate varies depending on the difference in volume expansion coefficient between the circuit substrate and the semiconductor substrate, the lower layer Bumps are pulled to the semiconductor substrate and upper layer bumps are pulled to the circuit board, so even if the lower layer bump and upper layer bump receive stresses in opposite directions, the joints between the lower layer bump and upper layer bump are tied together. Since it has a columnar shape rather than a different shape, cracks are unlikely to occur at the joint between the lower bump and the upper bump.

  According to the semiconductor element mounting substrate of the present invention, even when the sealing resin is filled in the gap between the resist layer covering the lower bumps and the columnar portions of the upper bumps and the circuit board, the resist Since the contact interface between the layer and the sealing resin is shifted in the height direction from the joint between the lower bump and the upper bump, the shear that occurs at the contact interface between the resist layer and the sealing resin Stress is not directly applied to the joint between the lower bump and the upper bump. This also can prevent cracks from entering the joint between the lower bump and the upper bump.

  Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

  First, the semiconductor element of the present invention will be described in detail with reference to FIG.

  FIG. 1 is a cross-sectional view of a semiconductor device manufactured by the manufacturing method of the present invention. The semiconductor device shown in FIG. 1 includes a circuit wiring 2, a base metal layer 3, a passivation layer 4, solder bumps 5, etc. on a semiconductor substrate 1. Is provided.

  The semiconductor substrate 1 is made of a semiconductor material such as single crystal silicon, and has a functional element (not shown) such as a transistor, a circuit wiring 2, a base metal layer 3, a passivation layer 4, a solder bump 5, a resist layer 7 and the like on its upper surface. And functions as a support base material that supports them.

  Such a semiconductor substrate 1 is obtained by, for example, slicing a single crystal silicon ingot formed by a conventionally known chocolate ski method (pull-up method) or the like to a predetermined thickness, and polishing the surface thereof. Thereafter, an insulating film is formed on the entire surface of the plate body by a conventionally known thermal oxidation method.

  The circuit wiring 2 formed on the semiconductor substrate 1 is deposited to a thickness of 0.5 μm to 1.5 μm with a metal material such as aluminum (Al) or copper (Cu), and functions as a transistor (not shown). It functions as a power supply wiring for supplying power from the outside, electric signals, and the like to the element.

  A plurality of base metal layers 3 are dotted on the upper surface of a part of the circuit wiring 2 so as to be arranged linearly along the end of the semiconductor substrate 1.

  When the semiconductor element is mounted on the circuit board K, the base metal layer 3 effectively erodes aluminum or the like that forms the circuit wiring 2 as the solder bumps 5 provided on the base metal layer 3 melt. In order to prevent this, it has a structure that provides good wettability to the material constituting the solder bump 5. Specifically, a three-layer structure in which zinc (Zn), nickel (Ni), and gold (Au) are sequentially stacked from the semiconductor substrate 1 side, a two-layer structure of zinc (Zn), nickel (Ni), or palladium A three-layer structure of (Pd), nickel (Ni), gold (Au), a two-layer structure of palladium (Pd), nickel (Ni), and the like.

  The circuit wiring 2 is formed in a predetermined pattern on the upper surface of the semiconductor substrate 1 by employing conventionally known sputtering, photolithography technology, and etching technology. Further, when the base metal layer 3 has a three-layer structure of zinc (Zn), nickel (Ni), and gold (Au), for example, a circuit wiring exposed from the passivation layer 4 after forming a passivation layer 4 to be described later By adopting a conventionally known electroless plating method or the like on a part of the upper surface of 2, zinc (Zn), nickel (Ni), and gold (Au) are sequentially laminated from the substrate side to form a cylindrical shape. Is done.

On the other hand, a passivation layer 4 made of an electrically insulating material such as silicon nitride (Si ₃ N ₄ ), silicon oxide (SiO ₂ ), polyimide or the like is provided in the non-formation region of the base metal layer 3 with circuit wiring 2 or a functional element (not shown). It is applied to cover.

  The passivation layer 4 effectively prevents the functional elements and the circuit wiring 2 from being corroded by contact with moisture contained in the atmosphere by blocking the functional elements and the circuit wiring 2 from the atmosphere. It is preferable that a part thereof covers the outer peripheral upper surface of the base metal layer 3.

  The passivation layer 4 is formed to a thickness of 0.5 μm to 3.0 μm on the upper surface of the semiconductor substrate 1 by employing a conventionally known sputtering, photolithography technique, etching technique or the like.

  Solder bumps 5 are formed on the upper surface of the base metal layer 3 described above.

The solder bump 5 is composed of a lower bump 5x formed on the upper surface of the underlying metal layer 3, the upper bumps 5y formed on the lower layer bumps 5x, this upper bump 5y further columnar portion 5y ₁ and the bump consisting of the exposed portion 5y ₂ Metropolitan.

  The solder bump 5 is melted by being heated when the semiconductor element is mounted on the circuit board K, and electrically and mechanically connects the base metal layer 3 of the semiconductor element and the circuit pattern on the circuit board K. Is for. The solder bump 5 is made of a conductive material such as solder in which tin (Sn), silver (Ag), and copper (Cu) are melted and solidified in a ratio of 96.5: 3.0: 0.5. Is formed to a height of 20 μm to 100 μm.

  The lower bump 5x of the solder bump 5 is formed on the base metal layer 3, and the shape thereof has a mountain-like cross section or a spherical shape. The lower surface bump 5x is covered with a resist layer 7 to be described later on the slope and side surfaces other than the joint with the upper layer bump 5y.

  And by covering the inclined surface in this way, the circuit board on which the semiconductor element is mounted is exposed to repeated environmental temperature changes, and the expansion and contraction of each board according to the difference in the volume expansion coefficient between the circuit board and the semiconductor substrate. As a result, the resist layer 7 suppresses the lower layer bump 5x from the upper side from being peeled off from the underlying metal layer 3 due to the thermal stress generated between the circuit board K and the semiconductor element. It becomes possible.

  The lower layer bump 5x preferably has a mountain shape in cross section. This is because, when the lower bump 5x is made spherical, a part of the resist layer 7 also enters the lower surface side of the sphere. Therefore, after the semiconductor element is mounted on the circuit board K, the circuit board K becomes hot during use. At this time, the resist layer 7 that has entered the layer expands thermally, and a force that lifts the lower bump 5x from the lower surface side acts, thereby causing cracks or peeling between the base metal layer 3 and the lower bump 5x. On the other hand, if the lower bump 5x has a mountain-shaped cross section, the resist layer 7 does not exist immediately below the lower bump 5x. Therefore, even if the resist layer 7 expands due to heat, the lower bump 5x The bottom surface of the lower bump 5x is not pressed so as to be pushed up by the resist layer 7 as in the case of a spherical shape. Therefore, the occurrence of peeling or cracking between the base metal layer 3 and the lower bump 5x is promoted. This is because there is no.

The top of the lower bumps 5x not covered with the resist layer 7 becomes a joint portion between the upper bump 5y, columnar section 5y ₁ of upper bump 5y from the top is erected. Further, the side surface of the columnar portion 5 y ₁ is in contact with the resist layer 7. Therefore so that the columnar portion 5y ₁ substantially resist layer 7 is embedded. The columnar portion 5y ₁ has a thickness in the height direction set to about 2 μm to 10 μm.

As a result, the circuit board K on which the semiconductor element is mounted is exposed to repeated environmental temperature changes, and the resist layer 7 presses the lower bump 5x due to the difference in volume expansion coefficient between the resist layer 7 and the solder bump 5. even if the change of the stress is repeated, the joint abutting the resist layer 7 is not a sharp shape, since it is substantially whole and the surface in contact with the shape of the side surface of the columnar section 5y ₁ of the upper bumps 5y, columnar stress from the resist layer 7 at substantially entire side parts 5y ₁ can receive the. As a result, thermal stress is not concentrated only at the joint between the lower bump 5x and the upper bump 5y, and therefore the stress applied to the joint is not locally increased. For this reason, the stress concerning the junction part of the lower layer bump 5x and the upper layer bump 5y can be reduced. Therefore, it is possible to suppress the occurrence of the problem of generating cracks in the joints from being promoted by the resist layer 7 that contacts the solder bump joints.

Furthermore, not a shape joint between the lower bump 5x and an upper bump 5y is constricted, has a columnar portion 5y ₁ of the upper bumps 5y, columnar section 5y ₁ is embedded in a substantially resist layer 7 Therefore, the circuit board K on which the semiconductor element is mounted is exposed to repeated environmental temperature changes, and the expansion / contraction amount of each board varies depending on the difference in volume expansion coefficient between the circuit board K and the semiconductor substrate 1. Sometimes, the lower layer bump 5x is pulled by the semiconductor substrate 1 and the upper layer bump is pulled by the circuit board K, and the lower layer bump 5x and the upper layer bump 5y receive stresses opposite to each other, that is, shear stress. Since the joint between the lower bump 5x and the upper bump 5y is not a constricted shape but a columnar shape, it is difficult for cracks to enter the joint between the lower bump 5x and the upper bump 5y.

Then, on the columnar portion 5y ₁ of the upper bumps 5y is bump exposed portion 5y ₂ of the upper bumps 5y are formed. The bump exposed portion 5y ₂ is by projecting from the resist layer 7 plays a role responsible for bonding between the circuit pattern of the circuit board K at the time of mounting the semiconductor device to an external circuit board K.

On the other hand, in the non-formation region of the solder bumps 5 as described above, the resist layer 7 surrounding the bump exposed portion 5y ₂ of the lower bumps 5x and upper bumps 5y is covered, the resist layer 7 and the underlying bump 5x and the upper bumps 5y a columnar portion 5y ₁ of is in a state of contact with each other.

  The resist layer 7 is used to increase the height of the solder bumps 5 when a semiconductor element is mounted on the circuit board K to form a semiconductor element mounting board. Sex can be kept high.

  As such a resist layer 7, for example, a conventionally known thermosetting epoxy resin or ultraviolet curable resin is preferably used.

  Next, a method for manufacturing the semiconductor element of the present invention will be described with reference to FIG. 2A to 2G are cross-sectional views of respective steps for explaining a method for manufacturing a semiconductor element.

  (1) First, the semiconductor substrate 1 having the circuit wiring 2, the base metal layer 3, and the passivation layer 4 deposited thereon is prepared, and the solder paste 5 ′ is applied on the base metal layer 3 (FIG. 2A). .

  At this time, when the amount of the applied solder paste 5 'is large, a spherical lower layer bump 5x is formed, and when the amount of solder paste 5' is small, the lower layer bump 5x has a mountain-like cross section.

  For the application of the solder paste 5 ', for example, a conventionally known screen printing method is employed. That is, a print mask 8 having an opening corresponding to the base metal layer 3 is disposed on the semiconductor substrate 1 and the solder paste 5 ′ placed on the print mask 8 is pushed out by a pressing means 9 such as a squeegee. Is applied onto the underlying metal layer 3 through the openings of the printing mask 8.

  As the solder paste 5 ', a solder paste adjusted to a predetermined viscosity by adding and mixing a flux or the like to a large number of solder particles is preferably used.

  (2) Next, the lower layer bumps are formed on the base metal layer 3 by heating the solder paste 5 ′ applied on the base metal layer 3 at a temperature equal to or higher than the melting point of the solder paste 5 ′ for 40 seconds to 60 seconds, for example. 5x is formed (FIG. 2B). Such lower layer bumps 5x are melted by heating, and the melted solder paste 5 'has a spherical shape, a cross-sectional mountain shape, or a flat plate shape, and is solidified while maintaining its shape.

  The shape of the lower bump 5x can be made spherical when the amount of the solder paste 5 'is increased with respect to the opening area of the base metal layer 3, and can be made into a mountain shape or a flat plate shape when it is reduced.

  The solder paste 5 ′ is heated by, for example, introducing the semiconductor substrate 1 coated with the solder paste 5 ′ into a reflow furnace and heat from a heater provided in the reflow furnace.

  (3) Next, when the lower-layer bump 5x formed as described above is viewed in plan, a resin that does not adhere to the resist such as flux 6 is applied to a region corresponding to the center of the lower-layer bump 5x (FIG. 2 (c)). . The area corresponding to the center corresponds to the highest apex portion of the lower bump 5x if it is spherical, for example. The resin that does not adhere to the resist needs to have a property that it is difficult to adhere to the resist layer 7 described later. Specifically, the flux 6 is preferably used.

  Since the area of the lower layer bump 5x exposed from the resist layer 7 can be secured larger as the area of the flux 6 applied on the lower layer bump 5x is larger, the bonding with the upper layer bump 5y formed on the lower layer bump 5x is possible. Since the area of the portion is increased and the degree of tightness is reduced, the bonding strength of the solder bumps 5 is improved. Therefore, when it is desired to ensure the bonding strength of the solder bumps 5, the application area of the flux 6 may be increased.

  In addition, the flux 6 is covered with a resist layer 7 to be described later, and the upper surface of the resist layer 7 is higher than the upper surface of the flux 6 in order to prevent the upper layer bump 5y from being formed on the lower layer bump 5x. However, if the upper surface of the flux 6 is increased by increasing the thickness of the flux 6 at this time, the upper surface of the resist layer 7 can be positioned higher by that amount.

The difference in height between the upper surface of the top portion and the resist layer 7 of the lower bumps 5x is substantially coincident with the columnar portion of the selected 5y ₁ of upper bump 5y, the higher the height of the columnar portion 5y _1, the resist layer 7 since even wider area of the side surface of the resist layer 7 and the surface in contact with the bump exposed portion 5y ₂ is embedded in, and thus be more relaxed local concentration of thermal stress. Therefore, the thickness of the flux 6 is preferably as thick as possible.

  When a sufficient thickness cannot be obtained by one application when forming the flux 6, a plurality of layers of the flux 6 may be formed by applying the flux 6 in a plurality of times. This can be easily achieved by repeatedly applying the first-layer flux 6, drying the flux 6, and then forming the second-layer flux 6.

  The flux 6 used here is, for example, a paste, and the viscosity is such that it does not flow out after being transferred onto the lower bump 5x, for example, about 0.5 Pa · S to 50 Pa · S. It is desirable that

  Further, in the step of forming the resist layer 7 to be described later, the resist material 7 ′ is heated and fluidized and further thermally cured, but at this time, it does not mix with the resist material 7 ′. It is required to have. As such a flux, a rosin type is used.

  (4) Subsequently, a resist material 7 'for forming a resist layer having a height lower than that of the upper surface of the flux is applied to a region other than the flux region (FIG. 2D).

  For the application of the resist material 7 ′, for example, a conventionally known screen printing method or dispenser method is employed. In this embodiment, a screen printing method is employed. That is, the print mask 8 used for screen printing is disposed on the substrate such that the opening is located in a region where the lower bump 5x does not exist and the non-opening is located on the lower bump 5x. 7 ′ is placed on the printing mask 8, and then the pressing means 9 such as a squeegee is moved to apply the resist material 7 ′ onto the semiconductor substrate 1 through the opening. In the present embodiment, an ultraviolet curable resin is used as the resist material 7 '.

  (5) Next, a resist material 7 ′ fluidized at room temperature is applied, and then cured at room temperature (about 25 ° C.) to form a resist layer 7 (FIG. 2 (e)).

  The fluidized resist material 7 'spreads on the semiconductor substrate 1 and covers the lower bumps 5x. At this time, if the height of the upper surface of the resist layer 7 is set lower than the height of the upper surface of the flux 6, the resist layer 7 does not cover the flux 6. As a result, the state in which the flux 6 is exposed on the upper surface can be maintained even after application of the resist layer 7, and the upper bump 5 y can be formed on the lower bump 5.

  (6) Subsequently, a solder paste 5 ″ is applied on the lower bump 5x (FIG. 2 (f)).

  For the application of the solder paste 5 ″, for example, a conventionally known screen printing method is employed. That is, a printing mask 8 having an opening corresponding to the base metal layer 3 is disposed on the semiconductor substrate 1 and the printing is performed. A solder paste 5 ″ placed on the mask 8 is applied onto the base metal layer 3 through the opening of the printing mask 8.

  (7) Finally, the upper layer bump 5y is formed by heating the solder paste 5 "applied in the step (5) at a temperature equal to or higher than the melting point of the solder paste 5" for 40 seconds to 60 seconds, thereby forming the lower layer bump 5x. A semiconductor element having the solder bumps 5 composed of the upper bumps 5y is completed (FIG. 2 (g)).

  Next, a semiconductor element mounting board on which the above-described semiconductor element is mounted will be described.

  As shown in FIG. 3, this semiconductor element mounting substrate is mainly composed of the above-described semiconductor element and circuit board K. The circuit board K has a circuit pattern s and a pad portion p provided in a predetermined area of the circuit pattern s on the upper surface thereof. The solder bump 5 of the semiconductor element is connected to the pad portion p. Further, after the semiconductor element is mounted, a sealing resin f is filled between the semiconductor element and the circuit board K.

  As the circuit board K of the semiconductor element mounting board, for example, a synthetic resin or ceramic board is used. A circuit pattern s is formed of a metal material such as aluminum, gold, or copper on the inside or the upper surface, and various electronic components and functional elements are mounted. The circuit pattern s formed on the circuit board K is formed by processing a metal wiring such as aluminum into a predetermined pattern.

  A pad portion p connected to the circuit pattern s is formed on the upper surface of the circuit board K.

  The pad portion p is for connection to the solder bump 5 of the semiconductor element, and basically a barrier metal layer made of nickel or the like similar to the base electrode layer 3 on the semiconductor element side is formed.

  In mounting the semiconductor element, first, the pad part p forming surface of the circuit board K and the solder bump 5 forming surface of the semiconductor element are opposed to each other, and the upper bump 5y of the solder bump 5 is positioned on the pad part p of the circuit board K. To be arranged. Thereafter, by reflowing the upper bumps 5y, the bump exposed portions of the upper bumps 5y are melted and connected to the pad portions p by connection. Thereafter, the solder joint is covered by filling a sealing resin f between the circuit board K and the semiconductor substrate 1.

  As the sealing resin f, for example, a conventionally known one such as an epoxy resin is used, but it is necessary to fill a narrow gap of about 10 μm to 100 μm formed by the circuit board K and the resist layer 7 of the semiconductor element. The viscosity is set low.

  By the way, since the sealing resin f is in contact with the resist layer 7, an interface with the resist layer 7 exists. When the environmental temperature of the semiconductor element mounting substrate changes between the resist layer 7 and the sealing resin f, shear stress is generated at the above-described contact interface due to the difference in volume expansion coefficient between the two.

  At this time, in the solder bump having the conventional structure, the joint portion between the lower layer bump 5x and the upper layer bump 5y is substantially in the same plane because it coincides with the contact interface in the height direction. The shear stress generated at the contact interface is directly applied to the joint, and a crack may occur in the joint.

  However, the joint between the lower bump 5x and the upper bump 5y is shifted in the height direction from the contact interface between the resist layer 7 and the sealing resin f described above. Accordingly, the shear stress generated at the contact interface between the resist layer 7 and the sealing resin f is not directly applied to the joint portion between the lower layer bump 5x and the upper layer bump 5y, thereby the lower layer bump 5x and the upper layer bump 5y. It can suppress that a crack enters into the joined part.

In this embodiment, the contact interface between the resist layer 7 and the sealing resin f is per middle of the upper bump 5y in the height direction, specifically, between the columnar portion 5y ₁ and the bump exposed portion 5y ₂ positioned.

  In addition, this invention is not limited to the above-mentioned embodiment, A various change and improvement are possible in the range which does not deviate from the summary of this invention.

  For example, in the above-described embodiment, the case where the resist layer 7 and the sealing resin f have different volume expansion coefficients has been described. Instead, the volume expansion coefficients of the resist layer 7 and the sealing resin f are substantially the same. Accordingly, the shear stress generated at the contact interface between the two can be reduced.

  Furthermore, in the present invention, solder bumps or solder plating layers may be formed in advance on the pad portion p of the circuit board. Thereby, the height of the entire solder connection portion can be increased, and various thermal stresses generated between the semiconductor substrate and the circuit substrate can be satisfactorily relaxed.

It is sectional drawing of the semiconductor element manufactured by the manufacturing method which concerns on one Embodiment of this invention. (A)-(g) is sectional drawing of each process for demonstrating the manufacturing method of the semiconductor element of FIG. It is sectional drawing of the semiconductor element mounting board | substrate which mounts the semiconductor element of this invention. It is sectional drawing of the conventional semiconductor element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Circuit wiring 3 ... Base metal layer 4 ... Passivation layer 5 ... Solder bump 5x ... Lower layer bump 5y ... Upper layer bump 5y ₁ ... Upper layer bump Columnar portion 5y ₂ ... bump exposed portion 5 ', 5 "of upper layer bump ... solder paste 6 ... resist layer 6' ... resist material 7 ... flux 8 ... printing mask 9 ..Pressing means (squeegee)
K ... Circuit board f ... Sealing resin p ... Pad part s ... Circuit pattern

Claims (3)

A semiconductor element comprising a base metal layer formed on a semiconductor substrate, a lower bump formed on the lower metal layer, and an upper bump formed on the lower bump,
The lower bump is coated with a resist layer on the surface other than the joint with the base metal layer and the joint with the upper bump,
The upper bump is composed of a columnar portion formed at a junction with the lower bump, and a bump exposed portion formed on the columnar portion, and the columnar portion is substantially embedded in the resist layer. The semiconductor element characterized by the above-mentioned. A pad part for mounting the semiconductor element according to claim 1 is provided on the circuit board, and the semiconductor element is mounted on the circuit board by bonding the pad part and an upper bump of the semiconductor element. A semiconductor device mounting board characterized by that. The semiconductor element mounting board according to claim 2, wherein a sealing resin is filled in a gap between the circuit board and the semiconductor element.

Images