JP2006048378A - Memory controller and electronic device therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller 1 that, even if a read start address from a memory 2 is not a word address, can transfer data in a short period of time same as in the case of a word address. <P>SOLUTION: The memory controller 1 comprises a buffer 17 intervening between two memories 2, 3 for temporarily storing the data read from one memory 2; a DMA control circuit 13 that, from the read start address included in a data transfer command from the outside, derives the word address of a word including the data stored in the read start address of the one memory 2; a selection circuit 18a that stores the data read from the word address of the one memory 2 into the buffer 17; and another selection circuit 19a that from the buffer 17 reads the data stored beyond the read start address of the one memory 2 and writes the data into the other memory 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a memory control device that intervenes between two memories and transfers data between the two memories, and an electronic apparatus including the memory control device.

In recent years, digital cameras that record images captured by an imaging optical system such as a CCD (solid-state imaging device) as digital data on a recording medium such as a memory card have become widespread.
In a digital camera, when an image recording operation is performed by a user, an image signal obtained from an imaging optical system is converted into digital image data, and then compressed by a well-known compression method. The compressed image data obtained thereby Is once stored in the SDRAM and then recorded on the recording medium.
In addition, when an image reproduction operation is performed by the user, the compressed image data recorded on the recording medium is read out and once stored in the SDRAM, and thereafter, the data includes image expansion processing and analog conversion processing. Known signal processing is performed, and an image signal obtained thereby is supplied to an image display device such as an LCD (liquid crystal display). As a result, the image recorded on the recording medium is displayed on the image display device.

FIG. 8 shows the configuration of a conventional digital camera. In FIG. 8, the imaging optical system and the image display device are not shown.
The digital camera includes a CPU (6) for controlling various operations such as an imaging operation, an SDRAM (2) for temporarily storing image data, and a recording medium (3) for recording image data. A DMA (Direct Memory Access) controller (5) for transferring data between the SDRAM (2) and the recording medium (3). The thin lines in the figure represent data buses, and the numbers written in the vicinity of each bus represent the bus width. The SDRAM (2) has a 32-bit bus width, while the recording medium (3) has a 16-bit bus width.

The DMA controller (5) includes an SDRAM control circuit (51) for controlling writing and reading with respect to the SDRAM (2), a recording medium control circuit (52) for controlling writing and reading with respect to the recording medium (3), Two access speed difference absorbing memories (54a) (54b) for temporarily storing data having a data capacity and read from the SDRAM (2) and the recording medium (3), and these two memories (54a ) (54b), a first memory selection circuit (55a) for selecting one memory and writing data to the memory, and a second memory for selecting one memory and reading data from the memory And a selection circuit (55b).
The DMA controller (5) selects either the upper 16-bit data or the lower 16-bit data from the 32-bit data read from the access speed difference absorbing memories (54a) (54b). The first data selection circuit (56a) to be supplied to the recording medium control circuit (52) and 16-bit data sequentially read out from the recording medium (3) are used to create 32-bit data. A second data selection circuit (56b) for supplying access speed difference absorption memory (54a) (54b) is provided.

The SDRAM control circuit 51, the recording medium control circuit 52, the first and second memory selection circuits 55a and 55b, and the first and second data selection circuits 56a and 56b are controlled by A DMA control circuit (53) for controlling the operation of these circuits is connected via a bus (50).
The CPU (6) is connected to the DMA control circuit (53), and the DMA control circuit (53) receives the data transfer command from the CPU (6) and executes the control operation.

In the SDRAM (2), an address (hereinafter referred to as a byte address) is assigned for each byte. For example, “SA0” in the first byte, “SA1” in the second byte, and 3 bytes as the byte address. "SA2" ... is given to the eye.
The CPU (6) performs data processing with one word as 32 bits (= 4 bytes), and the DMA controller (5) accesses the SDRAM (2) in units of words. Is possible. Since one word is 4 bytes, the first address of each word (hereinafter referred to as a word address) is “SA0”, “SA4”, “SA8”,.

9A shows data stored in the SDRAM (2) in units of words, while FIG. 9B shows data stored in the SDRAM (2) in units of bytes. (C) to (e) of FIG. 5 show access speed difference absorbing memories (54a) (54b) and (4) when data stored in the SDRAM (2) is transferred to the recording medium (3). The timing at which data is stored in the recording medium (3) is shown.
As shown in FIG. 9A, data “D0” is stored in word address “SA0”, data “D1” is stored in word address “SA4”, data “D2” is stored in word address “SA8”, and the like. Has been. Further, as shown in FIG. 4B, for example, the data “D0” stored in the word address “SA0” is composed of four data “D0a” to “D0d”, and the data is stored in the byte address “SA0”. Data “D0b” is stored in “D0a”, byte address “SA1”, data “D0c” is stored in byte address “SA2”, and data “D0d” is stored in byte address “SA3”.

For example, from the CPU (6) shown in FIG. 8 to the DMA control circuit (53) of the DMA controller (5), the word address “SA0” is used as the read start address from the SDRAM (2), and data for 8 words is SDRAM. When a data transfer command is issued to transfer data from (2) to the recording medium (3), the DMA control circuit (53) outputs a data processing command including the word address to the SDRAM control circuit (51). . Upon receiving the command, the SDRAM control circuit (51) reads data from the word address of the SDRAM (2) 32 bits at a time and bursts the data for 4 words as a block to the first memory selection circuit (55a). The operation to start is started.
The first memory selection circuit (55a) starts the operation of storing the data from the SDRAM control circuit (51) in one access speed difference absorption memory (54a) as shown in FIG. When the first 32-bit data “D0a” to “D0d” are stored in (54a) and data can be read from the memory (54a), the second memory selection circuit (55b) The operation of reading data from the memory (54a) 32 bits at a time and supplying it to the first data selection circuit (56a) is started.

As described above, the first four words of data “D0a” to “D3d” are read from the one access speed difference absorbing memory (54a) and supplied to the first data selection circuit (56). In the meantime, the first memory selection circuit (55a) stores the data "D4a" to "D7d" for the next four words in the other access speed difference absorbing memory (54b) as shown in FIG. When the last data “D3d” of the data for the first four words is supplied to the first data selection circuit (56a), the second memory selection circuit (55b) The operation of reading the data from the access speed difference absorbing memory (54a) 32 bits at a time and supplying it to the first data selection circuit (56a) is started.
As described above, the first data selection circuit (56a) is a recording medium control circuit that alternately converts the lower 16-bit data and the upper 16-bit data among the 32-bit data supplied from the second memory selection circuit (55b). The operation for supplying to (52) is executed, and the recording medium control circuit (52) writes the supplied data to the recording medium (3) as shown in FIG.
In this way, data “D0a” to “D7d” for 8 words stored after the word address “SA0” is transferred from the SDRAM (2) to the recording medium (3) and recorded. .

  In the DMA controller (5), as described above, the data read from the SDRAM (2) is temporarily stored in the access speed difference absorbing memory (54a) (54b) and then written to the recording medium (3). The difference between the access speed for the SDRAM (2) and the access speed for the recording medium (3) can be reduced. Also, as shown in FIGS. 9C to 9E, a process of reading data from one access speed difference absorbing memory (54a) and writing it to the recording medium (3), and reading data from the SDRAM (2). By executing the process of writing to the other access speed difference absorbing memory (54b) in parallel, writing to the recording medium (3) can be performed continuously, and the overall data transfer time can be shortened. I can do it.

FIG. 10A shows data recorded in the recording medium (3) in units of bytes, and FIGS. 10B to 10E show data recorded in the recording medium (3). When data is transferred to the SDRAM (2), the timing at which data is stored in the access speed difference absorbing memories (54a) (54b), the timing at which data is stored in the SDRAM (2) in units of words, and the SDRAM (2) Represents the timing at which data is stored in byte units.
For example, data for 8 words is recorded from the CPU (6) shown in FIG. 8 to the DMA control circuit (53) of the DMA controller (5) using the word address “SA0” as the write start address to the SDRAM (2). When a data transfer command for transferring data from the medium (3) to the SDRAM (2) is issued, the DMA control circuit (53) outputs a data processing command to the recording medium control circuit (52). In response to the command, the recording medium control circuit (52) reads the data recorded on the recording medium (3) 16 bits at a time as shown in FIG. 10 (a) and transfers it to the second data selection circuit (56b). Start operation. The second data selection circuit (56b) creates 32-bit data by alternately using the supplied 16-bit data as lower data or upper data, and supplies it to the first memory selection circuit (55a).

  The first memory selection circuit (55a) starts the operation of storing the data from the second data selection circuit (56b) in one access speed difference absorption memory (54a) as shown in FIG. When the data “D0a” to “D3d” for four words are stored in the memory (54a) and the memory (54a) becomes full, the second memory selection circuit (55b) ) Is started to read out the data from (1) and supply it to the SDRAM control circuit (51).

Further, as described above, when the first four words of data “D0a” to “D3d” are stored in one access speed difference absorbing memory (54a) and the memory (54a) becomes full, The one memory selection circuit (55a) stores the data "D4a" to "D7d" for the next four words in the other access speed difference absorbing memory (54b) by 32 bits as shown in FIG. To start. Thereafter, when the data “D4a” to “D7d” are stored in the memory for absorbing the access speed difference (54b) and the memory (54b) becomes full, the second memory selection circuit (55b) The operation of reading the data from the memory (54b) and supplying it to the SDRAM control circuit (51) is started.
The SDRAM control circuit (51) stores the data supplied from the second memory selection circuit (55b) in the SDRAM (2) 32 bits at a time, as shown in FIGS.
In this way, data for 8 words recorded on the recording medium (3) is transferred to the SDRAM (2) and stored after the word address "SA0".

  In the DMA controller (5), as described above, the data read from the recording medium (3) is temporarily stored in the access speed difference absorbing memory (54a) (54b) and then written in the SDRAM (2). The difference between the access speed for the SDRAM (2) and the access speed for the recording medium (3) can be reduced. Further, as shown in FIGS. 10B to 10E, the data is read from one access speed difference absorbing memory (54a) and stored in the SDRAM (2), and the data is read from the recording medium (3). By executing in parallel the process of storing in the other access speed difference absorbing memory (54b), the process of storing the data for 4 words in the SDRAM (2) is completed and the next 4 words are stored. The time until the process of storing the data in the SDRAM (2) is started can be shortened, and the entire data transfer time can be shortened.

The applicant of the present application has proposed a data processing apparatus that includes three memories including an SDRAM and can perform high-speed transfer processing between these memories (see Patent Documents 1 and 2).
The applicant of the present application has proposed various memory control circuits for accessing the memory in response to an access request from the CPU (see Patent Documents 3 and 4).
Furthermore, a high performance high bandwidth RAM bus architecture has been proposed that can reduce latency using SDRAM chips (see Patent Document 5).
JP 2001-243171 A JP 2004-030602 A JP 2000-187635 A JP 11-259358 A Japanese Patent Laid-Open No. 10-340224

  However, in the conventional digital camera, when the read start address from the SDRAM (2) is the word address “SA0”, “SA4”, “SA8”,..., The DMA controller (5) as described above. However, when the read start address of the SDRAM (2) is not a word address, for example, the byte address “SA2”, the data transfer process is performed only by the DMA controller (5). The data transfer process is performed by the CPU (6) and the DMA controller (5) as described later.

For example, when transferring the data “D0c” to “D2d” for three words to the recording medium (3) using the read start address from the SDRAM (2) as the byte address “SA2”, the CPU (6) As shown in FIG. 11A, a program for reading the word data “D0” stored in the word address “SA0” of the SDRAM (2) from the program storage memory (hereinafter referred to as a data reading program) is fetched and executed. As a result, the data “D0” stored in the word address “SA0” of the SDRAM (2) as shown in FIG. 8B, that is, the data “D0a” to “D0d” for 32 bits shown in FIG. Is read into the register of the CPU (6). Subsequently, the CPU (6) shifts the data read into the register from the program storage memory by 16 bits to the lower and then writes the lower 16 bits to the recording medium (3) (hereinafter referred to as data). Fetch and execute a shift / write program). As a result, the data “D0c” and “D0d” respectively stored in the byte addresses “SA2” and “SA3” of the SDRAM (2) are recorded on the recording medium (3) as shown in FIG. Thereafter, the CPU (6) fetches and executes a program for starting the DMA controller (5) (hereinafter referred to as a DMA start program) from the program storage memory. As a result, data transfer to the DMA controller (5) from the CPU (6) indicating that two words of data should be transferred from the SDRAM (2) to the recording medium (3) using the word address “SA4” as the read start address. When a command is issued, data “D1a” to “D2d” for two words stored after the word address “SA4” of the SDRAM (2) are recorded on the recording medium (3) as shown in FIG. The In this way, the data “D0c” to “D2d” stored after the byte address “SA2” of the SDRAM (2) is transferred to the recording medium (3) and recorded.

In the conventional digital camera, as described above, when the read start address from the SDRAM (2) is not a word address, the CPU (6) fetches not only the DMA start program but also the data read program. And the process of fetching the data shift / write program must be performed, and there is a problem that the entire data transfer time becomes longer than when the read start address is a word address.
An object of the present invention is to provide a memory control device capable of transferring data in a time as short as when the read start address is a word address even when the read start address from the memory is not a word address. It is to provide an electronic device having this.

The memory control device according to the present invention interposes between two memories, receives a data transfer command from the outside, and transfers data between the two memories. For each word consisting of a plurality of bytes of data One memory can be accessed using the assigned word address. The memory control device
Data organization buffer means for temporarily storing data read from said one memory;
When a data transfer command including a read start address from the one memory is received from the outside, a word address of a word including data stored in the read start address of the one memory is derived from the read start address. Address deriving means to perform,
First data processing means for starting reading data from the word address of the one memory and storing the read data in the data organization buffer means;
Second data processing means for reading data stored after the read start address of the one memory from the data organization buffer means and writing it to the other memory.

The memory control device is connected to an information processing device that issues a data transfer command including a read start address from one memory to the memory control device.
In the memory control device according to the present invention, the word address of the word including the data stored in the read start address of the one memory is derived from the read start address included in the data transfer command from the information processing device. After that, data reading is started from the derived word address of one memory, and the read data is stored in the data organization buffer means. Then, data stored after the read start address of the one memory is read from the data organization buffer means and written to the other memory. In this way, data stored after the read start address of one memory is transferred to the other memory and recorded.
According to the memory control device of the present invention, even if the read start address included in the data transfer command from the information processing device is not a word address, it is stored after the read start address of one memory as described above. Since the stored data can be recorded in the other memory, the information processing apparatus only needs to fetch and execute the program for starting the memory control apparatus, and the process for fetching the data read program and the data shift / write program The process of fetching is unnecessary. Therefore, data can be transferred in a time as short as when the read start address is a word address.

  Specifically, the address deriving unit performs a word address deriving operation when the read start address included in the data transfer command is not a word address, and the first data processing unit performs the operation when the read start address is not a word address. On the other hand, data reading is started from the derived word address, and when the read start address is a word address, data reading is started from the read start address.

Specifically, in response to a data transfer command including a write start address to the one memory from the outside, data is transferred from the other memory to the one memory.
Third data processing means for reading data from the other memory and storing it in the data organization buffer means;
Fourth data processing means for reading out data of the number of bytes corresponding to the write start address included in the data transfer command from the data organization buffer means and writing the data after the write start address of the one memory. Yes.

  In the specific configuration described above, even if the write start address included in the data transfer command from the information processing device is not a word address, the data written in the other memory is stored after the write start address in one memory. Therefore, the information processing device only needs to fetch and execute a program for starting the memory control device, and transfers data in a time as short as when the write start address is a word address. I can do it.

  More specifically, it comprises two access speed difference absorbing memory means for temporarily storing data read from the data organization buffer means, and the second data processing means comprises the data organization buffer means. Are alternately written to the two access speed difference absorbing memory means, and are alternately read from the two access speed difference absorbing memory means and written to the other memory. The operation of reading data from the access speed difference absorbing memory means and writing it to the other memory and the operation of reading data from the data organization buffer means and writing to the other access speed difference absorbing memory means are executed simultaneously.

  In the above specific configuration, the data read from one memory is temporarily written in the data organization buffer means and the access speed difference absorbing memory means and then written in the other memory, thereby accessing between the two memories. The speed difference can be reduced. The operation of reading data from one access speed difference absorbing memory means and writing it to the other memory and the operation of reading data from the data organization buffer means and writing to the other access speed difference absorbing memory means simultaneously. By executing, writing to the other memory can be performed continuously, and the entire data transfer time can be shortened.

  More specifically, the third data processing means alternately writes the data read from the other memory into the two access speed difference absorbing memory means, and the two access speed difference absorbing memories. Alternately reading data from the means and storing it in the data organization buffer means, wherein the data is read from one access speed difference absorbing memory means and stored in the data organization buffer means, and the other The operation of reading the data from the other memory and writing it into the other access speed difference absorbing memory means is executed simultaneously.

  In the above specific configuration, the data read from the other memory is temporarily written in one memory after being written in the access speed difference absorbing memory means and the data organization buffer means, thereby accessing between the two memories. The speed difference can be reduced. An operation of reading data from one access speed difference absorbing memory means and storing it in the data organization buffer means; and an operation of writing data read from the other memory into the other access speed difference absorbing memory means; Are simultaneously executed, the storage process for the data organization buffer means can be continuously performed, and the entire data transfer time can be shortened.

  According to the memory control device and the electronic apparatus including the memory control device according to the present invention, even when the read start address from the memory is not a word address, the time is as short as when the read start address is a word address. Data transfer can be performed.

Hereinafter, the embodiment in which the present invention is applied to the digital camera shown in FIG. 1 will be described in detail with reference to the drawings. In FIG. 1, the imaging optical system and the image display apparatus are not shown.
As shown in the figure, a digital camera according to the present invention includes a CPU (4) for controlling various operations such as an imaging operation, an SDRAM (2) for temporarily storing image data, and an image data recording unit. Recording medium (3), and a DMA controller (1) for transferring data between the SDRAM (2) and the recording medium (3). The thin lines in the figure represent data buses, and the numbers written in the vicinity of each bus represent the bus width. The SDRAM (2) has a 32-bit bus width, while the recording medium (3) has a 16-bit bus width.

The DMA controller (1) includes an SDRAM control circuit (11) for controlling writing and reading to the SDRAM (2), a recording medium control circuit (12) for controlling writing and reading to the recording medium (3), and a 16-byte memory. Two access speed difference absorbing memories (14a) and (14b) for temporarily storing data read from the SDRAM (2) and the recording medium (3) having a data capacity, and these two memories (14a ) (14b), the first memory selection circuit (15a) for selecting any one of the memories to be data written and writing the data to the memory, and any one of the objects to be read. A second memory selection circuit (15b) for selecting a memory and reading data from the memory is provided.
The DMA controller (1) selects either the upper 16-bit data or the lower 16-bit data from the 32-bit data read from the access speed difference absorbing memory (14a) (14b). The first data selection circuit (16a) to be supplied to the recording medium control circuit (12) and 16-bit data sequentially read out from the recording medium (3) are used to create 32-bit data. And a second data selection circuit (16b) for supplying access speed difference absorption memories (14a) and (14b).

  Further, the DMA controller (1) has a data organization buffer having a 64-bit bus width for temporarily storing data read from the SDRAM (2) and the recording medium (3) in a characteristic configuration. (17), a first buffer write area selection circuit (18a) and a second buffer write area selection circuit (18b) for selecting an area in which data is to be written from the buffer (17) and writing data to the area; A first buffer read area selection circuit (19a) and a second buffer read area selection circuit (19b) for selecting an area from which data is to be read from the buffer (17) and reading data from the area. .

  The SDRAM control circuit (11), the recording medium control circuit (12), the first and second memory selection circuits (15a) (15b), the first and second data selection circuits (16a) (16b), the first and second The second buffer write area selection circuits (18a) and (18b) and the first and second buffer read area selection circuits (19a) and (19b) control the operation of these circuits via the control bus (10). A DMA control circuit (13) is connected, and the CPU (4) is connected to the control circuit (13).

When the CPU (4) tries to execute data transfer from the SDRAM (2) to the recording medium (3) to the DMA controller (1), the read start address from the SDRAM (2) is a word address. Regardless of whether or not there is, a program for starting the DMA controller (1) is fetched from a program storage memory (not shown) and executed. As a result, a data transfer command including a read start address, transfer capacity, and transfer direction from the SDRAM (2) is issued from the CPU (4) to the DMA control circuit (13) of the DMA controller (1).
On the other hand, when the DMA controller (1) is to execute data transfer from the recording medium (3) to the SDRAM (2), whether or not the write start address to the SDRAM (2) is a word address. Regardless, the program for starting the DMA controller (1) is fetched from the program storage memory and executed. As a result, a data transfer command including a write start address, transfer capacity, and transfer direction to the SDRAM (2) is issued from the CPU (4) to the DMA control circuit (13) of the DMA controller (1).
When receiving the data transfer command from the CPU (4), the DMA control circuit (13) determines whether or not the read start address or the write start address included in the command is a word address. The control operation is executed according to the result.

FIG. 2 shows a data transfer path for transferring data stored in the SDRAM (2) to the recording medium (3). 4A shows the data stored in the SDRAM (2) in units of words, whereas FIG. 4B shows the data stored in the SDRAM (2) in units of bytes. (C) to (f) in FIG. 6 respectively show a data organization buffer (17) and an access speed difference absorbing memory (14a) when the read start address from the SDRAM (2) is a word address. ) (14b) and the recording medium (3) represent the timing at which data is stored.
As shown in FIG. 4A, the data “D0” is stored in the word address “SA0”, the data “D1” is stored in the word address “SA4”, the data “D2” is stored in the word address “SA8”. Has been. Further, as shown in FIG. 4B, for example, the data “D0” stored in the word address “SA0” is composed of four data “D0a” to “D0d”, and the data is stored in the byte address “SA0”. Data “D0b” is stored in “D0a”, byte address “SA1”, data “D0c” is stored in byte address “SA2”, and data “D0d” is stored in byte address “SA3”.

  For example, the CPU (4) shown in FIG. 2 transfers data for 8 words from the SDRAM (2) to the recording medium (3) using the word address “SA0” as a read start address to the DMA control circuit (13). When a data transfer command indicating power is issued, the DMA control circuit (13) outputs a data processing command including the word address to the SDRAM control circuit (11). In response to the command, the SDRAM control circuit (11) reads data from the word address of the SDRAM (2) 32 bits at a time and sets the data for 4 words as one block to the first buffer write area selection circuit (18a). Starts burst transfer operation.

  As shown in FIG. 4 (c), the first buffer write area selection circuit (18a) has a lower side write area BD [31: 0] having a lower 32-bit width from the data organization buffer (17) and the upper side The upper side write area BD [63:32] having a 32-bit width is alternately selected, and the operation of writing 32-bit data supplied from the SDRAM control circuit (11) to the selected area is started. At the time when the first 64-bit data “D0a” to “D1d” are written to the buffer (17), the first buffer read area selection circuit (19a) sets the lower side write area and the upper side of the buffer (17). The operation of alternately reading 32-bit data from the side write area and supplying it to the first memory selection circuit (15a) is started. As shown in FIG. 4 (e), the first memory selection circuit (15a) starts the operation of storing the supplied 32-bit data in one access speed difference absorbing memory (14a), and then the memory ( When the first 32-bit data “D0a” to “D0d” are stored in 14a) and the data can be read from the memory (14a), the second memory selection circuit (15b) An operation of reading data from the memory (14a) 32 bits at a time and supplying it to the first data selection circuit (16a) is started.

As described above, the first four words of data “D0a” to “D3d” are read from the one access speed difference absorbing memory (14a) and supplied to the first data selection circuit (16a). In the meantime, the first memory selection circuit (15a) stores the next four words of data “D4a” to “D7d” in the other access speed difference absorbing memory (14b) as shown in FIG. After the operation starts, when the last data “D3d” of the data of the first four words is supplied to the first data selection circuit (16a), the second memory selection circuit (15b) An operation of reading data from the access speed difference absorbing memory (14a) 32 bits at a time and supplying it to the first data selection circuit (16a) is started.
As described above, the first data selection circuit (16a) is a recording medium control circuit that alternately converts the lower 16-bit data and the upper 16-bit data among the 32-bit data supplied from the second memory selection circuit (15b). The operation of supplying to (12) is executed, and the recording medium control circuit (12) writes the supplied data to the recording medium (3) as shown in FIG. 4 (f).
In this way, data “D0a” to “D7d” for 8 words stored after the word address “SA0” is transferred from the SDRAM (2) to the recording medium (3) and recorded. .

5 (c) to 5 (f) respectively show the data organization buffer (17), the access speed difference absorbing memories (14a) (14b), and the recording when the read start address from the SDRAM (2) is not a word address. The timing at which data is stored in each medium (3) is shown. FIGS. 5A and 5B are the same as FIGS. 4A and 4B, respectively. FIG. 5A shows the data stored in the SDRAM 2 in word units. FIG. 4B shows the data stored in the SDRAM (2) in units of bytes.
For example, from the CPU (4) shown in FIG. 2 to the DMA control circuit (13), 8-byte data is read from the SDRAM (2) to the recording medium (3) using the byte address “SA1” which is not a word address as the read start address. When a data transfer instruction is issued to transfer to the DMA controller circuit 13, the DMA control circuit 13 starts from the byte address “SA1” to the word data “D0” including the data “D0b” stored at the address. The word address “SA0” is derived, and a data processing command including the word address is output to the SDRAM control circuit (11). In response to the command, the SDRAM control circuit (11) reads data from the word address “SA0” of the SDRAM (2) 32 bits at a time and sets the data for 4 words as one block to the first buffer write area selection circuit ( The operation of burst transfer is started at 18a).

  As shown in FIG. 5C, the first buffer write area selection circuit (18a) selects the lower write area BD [31: 0] and the upper write area BD [63:32] from the data organization buffer (17). By alternately selecting, the operation of writing the 32-bit data supplied from the SDRAM control circuit (11) to the selected area is started, and then the first 64-bit data “D0a” to the buffer (17) are started. When "D1d" is written, the first buffer read area selection circuit (19a) starts an operation of reading data from the buffer (17) 32 bits at a time and supplying it to the first memory selection circuit (15a). . At this time, the write area of the data organization buffer (17) has a 32-bit width from the position where the data “D0b” stored in the read start address “SA1” of the SDRAM (2) is stored to the upper side. The first write area BD [39: 8] having the remaining 32-bit width and the second write area BD [7: 0] BD [63:40] having the remaining 32-bit width are divided into the first and second write areas BD [39: 8]. Data is alternately read from the write area and supplied to the first memory selection circuit (15a). As a result, the data after the data “D0b” stored in the read start address “SA1” is supplied to the first memory selection circuit 15a.

  As shown in FIG. 5E, the first memory selection circuit (15a) starts the operation of storing the supplied 32-bit data in one access speed difference absorbing memory (14a), and then the memory ( When the first 32-bit data “D0b” to “D1a” are stored in 14a) and the data can be read from the memory (14a), the second memory selection circuit (15b) An operation of reading data from the memory (14a) 32 bits at a time and supplying it to the first data selection circuit (16a) is started.

As described above, the first four words of data “D0b” to “D4a” are read from the one access speed difference absorbing memory (14a) and supplied to the first data selection circuit (16a). In the meantime, the first memory selection circuit (15a) stores the next four words of data “D4b” to “D8a” in the other access speed difference absorbing memory (14b) as shown in FIG. After the operation starts, when the last data “D4a” of the data for the first four words is supplied to the first data selection circuit (16a), the second memory selection circuit (15b) An operation of reading data from the access speed difference absorbing memory (14a) 32 bits at a time and supplying it to the first data selection circuit (16a) is started.
As described above, the first data selection circuit (16a) is a recording medium control circuit that alternately converts the lower 16-bit data and the upper 16-bit data among the 32-bit data supplied from the second memory selection circuit (15b). The operation supplied to (12) is executed, and the recording medium control circuit (12) writes the supplied data to the recording medium (3) as shown in FIG. 5 (f).
In this way, data “D0b” to “D8a” for 8 words stored after the byte address “SA1” is transferred from the SDRAM (2) to the recording medium (3) and recorded. .

  At the time of data transfer from the SDRAM (2) to the recording medium (3), as described above, the data read from the SDRAM (2) is temporarily stored in the data organization buffer (17) and the access speed difference absorbing memory (14a) (14b). ) And then writing to the recording medium (3), the difference between the access speed to the SDRAM (2) and the access speed to the recording medium (3) can be reduced. Also, as shown in FIGS. 4 (d) to (f), a process of reading data from one access speed difference absorbing memory (14a) and writing it to the recording medium (3) and a data organization buffer (17) , And writing to the other access speed difference absorbing memory (14b) in parallel, the writing to the recording medium (3) can be performed continuously.

  FIG. 3 shows a data transfer path for transferring data recorded on the recording medium (3) to the SDRAM (2). FIG. 6 (a) shows data stored in the recording medium (3) in units of bytes. FIGS. 6 (b) to (f) show the write start addresses for the SDRAM (2). When it is a word address, the timing at which data is stored in the access speed difference absorbing memory (14a) (14b), the timing at which data is stored in the data organization buffer (17), and the SDRAM (2) in word units The timing at which data is stored and the timing at which data is stored in the SDRAM (2) in byte units are shown.

  For example, from the CPU (4) shown in FIG. 3 to the DMA control circuit (13), the word address “SA0” is used as a write start address to the SDRAM (2), and data for 8 words is transferred from the recording medium (3) to the SDRAM. When a data transfer command for transferring to (2) is issued, the DMA control circuit (13) outputs a data processing command to the recording medium control circuit (12). Upon receiving the command, the recording medium control circuit (12) reads out the data recorded on the recording medium (3) as shown in FIG. 6 (a) 16 bits at a time and transfers it to the second data selection circuit (16b). Start operation. The second data selection circuit (16b) creates 32-bit data by alternately using the supplied 16-bit data as lower data or higher data, and supplies it to the first memory selection circuit (15a).

  The first memory selection circuit (15a) starts the operation of storing the data from the second data selection circuit (16b) in one access speed difference absorption memory (14a) as shown in FIG. When the data “D0a” to “D3d” for four words are stored in the memory (14a) and the memory (14a) becomes full, the second memory selection circuit (15b) ) To read the data and supply it to the second buffer write area selection circuit (18b).

  As described above, when the first four words of data “D0a” to “D3d” are stored in one access speed difference absorbing memory (14a) and the memory (14a) becomes full, the first The memory selection circuit (15a) operates to store the next four words of data "D4a" to "D7d" in the other access speed difference absorbing memory (14b) by 32 bits as shown in FIG. Start. Thereafter, when the data “D0a” to “D3d” for the first four words are read from the one access speed difference absorbing memory (54a) and supplied to the second buffer write area selection circuit (18b). The second memory selection circuit (15b) starts the operation of reading data from the other access speed difference absorbing memory (14b) by 32 bits and supplying the data to the second buffer write area selection circuit (18b).

As shown in FIG. 6C, the second buffer write area selection circuit (18b) assigns the lower side write area BD [31: 0] and the upper side write area BD [63:32] from the data organization buffer (17). By alternately selecting and executing the operation of writing the 32-bit data supplied from the second memory selection circuit (15b) to the selected area, the first 64-bit data “D0a” ˜ At the time when “D1d” is written, the second buffer read area selection circuit (19b) alternately reads 32-bit data from the lower write area and the upper write area of the buffer (17) to read out the SDRAM control circuit. The operation to supply to (11) is started. The SDRAM control circuit (11) stores the supplied data in the SDRAM (2) 32 bits at a time, as shown in FIGS.
In this way, data for 8 words recorded in the recording medium (3) is transferred to the SDRAM (2) and stored from the word address “SA0”.

  FIGS. 7B to 7F respectively show the timing at which data is stored in the data organization buffer 17 when the write start address to the SDRAM 2 is not a word address, and an access speed difference absorbing memory ( 14a) and 14b show the timing at which data is stored, the timing at which data is stored in SDRAM (2) in units of words, and the timing at which data is stored in units of bytes in SDRAM (2). FIG. 6A is the same as FIG. 6A and shows data recorded on the recording medium (3) in units of bytes.

  For example, from the CPU (4) shown in FIG. 3 to the DMA control circuit (13), data of 8 words is stored on the recording medium (3) using the byte address “SA1” which is not a word address as the write start address to the SDRAM (2). ) Is issued to the SDRAM (2), the DMA control circuit (13) outputs a data processing command to the recording medium control circuit (12). In response to the command, the recording medium control circuit (12) reads the data recorded on the recording medium (3) as shown in FIG. 7 (a) 16 bits at a time and transfers it to the second data selection circuit (16b). Start operation. The second data selection circuit (16b) creates 32-bit data by alternately using the supplied 16-bit data as lower data or higher data, and supplies it to the first memory selection circuit (15a).

  The first memory selection circuit (15a) starts the operation of storing the data from the second data selection circuit (16b) in one access speed difference absorption memory (14a) as shown in FIG. When the data “D0a” to “D3d” for four words are stored in the memory (14a) and the memory (14a) becomes full, the second memory selection circuit (15b) The operation of reading the data from the second buffer write area selection circuit (18b) is started.

  As described above, when the first four words of data “D0a” to “D3d” are stored in one access speed difference absorbing memory (14a) and the memory (14a) becomes full, the first The memory selection circuit (15a) operates to store the next four words of data "D4a" to "D7d" in the other access speed difference absorbing memory (14b) by 32 bits as shown in FIG. Start. Thereafter, when the data “D0a” to “D3d” for the first four words are read from the one access speed difference absorbing memory (54a) and supplied to the second buffer write area selection circuit (18b). The second memory selection circuit (15b) starts the operation of reading data from the other access speed difference absorbing memory (14b) by 32 bits and supplying the data to the second buffer write area selection circuit (18b).

The second buffer write area selection circuit (18b), as shown in (d) of FIG. 5, selects the lower side write area BD [31: 0] and the upper side write area BD [63:32] from the data organization buffer (17). By alternately selecting and executing the operation of writing the 32-bit data supplied from the second memory selection circuit (15b) to the selected area, the first 64-bit data “D0a” ˜ When "D1d" is written, the second buffer read area selection circuit (19b) starts an operation of reading data from the buffer (17) 32 bits at a time and supplying it to the SDRAM control circuit (11). At this time, the write area of the data organization buffer (17) is the first write area BD [23: 0] BD [63:56] having a 32-bit width in accordance with the write start address “SA1” to the SDRAM (2). And the second write area BD [55:24], and data are alternately read from the first write area and the second write area and supplied to the SDRAM control circuit (11). As a result, the 24-bit data “D0a” to “D0c” are supplied to the SDRAM control circuit (11) as the first data block, and then the data after the data “D0d” is supplied 32 bits at a time. Will be. The SDRAM control circuit (11) stores the supplied data in the SDRAM (2) as shown in FIGS.
In this way, data for 8 words recorded on the recording medium (3) is transferred to the SDRAM (2) and stored from the byte address “SA1”.

  As described above, when data is transferred from the recording medium (3) to the SDRAM (2), the data read from the recording medium (3) is temporarily stored in the access speed difference absorbing memories (14a) (14b) and the data organization buffer ( By writing to the SDRAM (2) after storing in 17), the difference between the access speed to the SDRAM (2) and the access speed to the recording medium (3) can be reduced. Further, as shown in FIGS. 6B to 6D, a process of reading data from one access speed difference absorbing memory (14a) and storing it in the data organization buffer (17), and a recording medium (3) By executing the process of reading data and writing to the other access speed difference absorbing memory (14b) in parallel, the storage process to the data organization buffer (17) can be performed continuously.

In the digital camera according to the present invention, the DMA controller (1) starts the reading of the SDRAM (2) even when the reading start address included in the data transfer command from the CPU (4) is not a word address. Since data written after the address can be transferred and recorded on the recording medium (3), the CPU (4) may fetch and execute the DMA start program as described above, and the data read program can be executed. The process of fetching and the process of fetching the data shift / write program are unnecessary. Therefore, data transfer from the SDRAM (2) to the recording medium (3) can be performed in a time as short as when the read start address is a word address.
Further, the DMA controller (1) transfers the data recorded on the recording medium (3) to the SDRAM (2) even when the write start address included in the data transfer command from the CPU (4) is not a word address. Therefore, the CPU (4) only needs to fetch and execute the DMA start program, and the recording medium (in the same time as the case where the write start address is a word address) can be stored. Data transfer from 3) to SDRAM (2) can be performed.

In addition, each part structure of this invention is not restricted to the said embodiment, A various deformation | transformation is possible within the technical scope as described in a claim.
For example, it is possible to employ not only SDRAM but also various other memories.
The present invention is not limited to a digital camera and can be implemented in various other electronic devices.

It is a block diagram showing the structure of the digital camera which implemented this invention. It is a block diagram showing the data transfer path | route at the time of transferring the data stored in SDRAM to a recording medium. It is a block diagram showing the data transfer path | route at the time of transferring the data currently recorded on the recording medium to SDRAM. It is a figure showing the timing of data reading and writing when the read start address from the SDRAM is a word address. It is a figure showing the timing of data reading and writing when the read start address from the SDRAM is not a word address. It is a figure showing the timing of data reading and writing when the write start address to SDRAM is a word address. It is a figure showing the timing of data reading and writing when the write start address to SDRAM is not a word address. It is a block diagram showing the structure of the conventional digital camera. It is a figure showing the timing of the data reading and writing at the time of transferring the data stored in SDRAM to a recording medium. It is a figure showing the timing of the data reading and writing at the time of transferring the data currently recorded on the recording medium to SDRAM. It is a figure showing the timing which CPU starts various programs, and the data stored in SDRAM and memory.

Explanation of symbols

(1) DMA controller
(11) SDRAM control circuit
(12) Recording medium control circuit
(13) DMA control circuit
(17) Data organization buffer
(18a) First buffer write area selection circuit
(18b) Second buffer write area selection circuit
(19a) First buffer read area selection circuit
(19b) Second buffer read area selection circuit
(2) SDRAM
(3) Recording medium
(4) CPU

Claims (6)

Intervening between two memories and receiving data transfer commands from the outside to transfer data between both memories, using a word address assigned to each word consisting of a plurality of bytes of data In a memory control device capable of accessing one memory,
Data organization buffer means for temporarily storing data read from said one memory;
When a data transfer command including a read start address from the one memory is received from the outside, a word address of a word including data stored in the read start address of the one memory is derived from the read start address. Address deriving means to perform,
First data processing means for starting reading data from the word address of the one memory and storing the read data in the data organization buffer means;
A memory control device comprising: second data processing means for reading data stored after the read start address of the one memory from the data organization buffer means and writing the data to the other memory .   The address deriving means performs a word address deriving operation when the read start address included in the data transfer command is not a word address, and the first data processing means is derived when the read start address is not a word address. The memory control device according to claim 1, wherein reading of data starts from a word address while reading of data starts from the reading start address when the reading start address is a word address. Receiving a data transfer command including a write start address to the one memory from the outside, and transferring data from the other memory to the one memory,
Third data processing means for reading data from the other memory and storing it in the data organization buffer means;
Fourth data processing means for reading out data of the number of bytes corresponding to the write start address included in the data transfer command from the data organization buffer means and writing the data after the write start address of the one memory. The memory control device according to claim 1 or 2.   Two access speed difference absorbing memory means for temporarily storing the data read from the data organization buffer means are provided, and the second data processing means stores the data read from the data organization buffer means as 2 Alternately writing to one access speed difference absorbing memory means, and alternately reading data from the two access speed difference absorbing memory means and writing to the other memory, one access speed difference absorbing memory 4. An operation of reading data from the means and writing it to the other memory and an operation of reading data from the data organization buffer means and writing to the other access speed difference absorbing memory means are simultaneously executed. The memory control device according to any one of the above.   The third data processing means alternately writes the data read from the other memory to the two access speed difference absorbing memory means, and alternately reads the data from the two access speed difference absorbing memory means. Storing data in the data organization buffer means, reading data from one access speed difference absorbing memory means and storing it in the data organization buffer means, and reading data from the other memory and the other 5. The memory control device according to claim 4, wherein the write operation to the access speed difference absorbing memory means is simultaneously executed. Two memories, a memory control device that is interposed between the two memories and receives a data transfer command from the outside and transfers data between the two memories, and an information processing device that issues a data transfer command to the memory control device In the electronic apparatus comprising:
Means for outputting a data transfer command including a read start address from one memory to the memory control device, wherein the memory control device uses a word address assigned to each word consisting of a plurality of bytes of data. It is possible to access said one memory,
Data organization buffer means for temporarily storing data read from said one memory;
Address deriving means for deriving a word address of a word including data stored in the read start address of the one memory from a read start address included in the command when receiving a data transfer command from the information processing apparatus When,
First data processing means for starting reading data from the word address of the one memory and storing the read data in the data organization buffer means;
Electronic equipment comprising: second data processing means for reading data stored after the read start address of the one memory from the data organization buffer means and writing it to the other memory.

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