JP2005332964A - Fuse element circuit of semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain without an error an output corresponding to the non-disconnection and disconnection states of a fuse element F1 in the fuse element circuit of a semiconductor integrated circuit device. <P>SOLUTION: A serial circuit formed of a transistor Q1 and a fuse element F1, and a serial circuit formed of a transistor Q2 and a resistor R1, are respectively connected to drains of transistors Q3, Q4 forming a current mirror circuit, and a base bias circuit which is formed in common for transistors Q1, Q2 is formed with transistors Q5, Q6. Consequently, an output is obtained from a node 6 via an inverter X1. Even if the fuse element is disconnected imperfectly, an output (L level) corresponding to the disconnecting state can surely be obtained from an output terminal 4 by setting a resistance value of the resistor R1 to the value sufficiently larger than the resistance value of fuse element F1 in the non-disconnecting state, and smaller than the minimum resistance value of the fuse element F1 which is assumed when the fuse element is set to imperfect disconnecting state. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a fuse element circuit of a semiconductor integrated circuit device, and more particularly to a circuit configuration for adjusting circuit characteristics and switching circuit operation using a fuse element.

In recent years, semiconductor integrated circuit devices are prone to errors in component characteristics due to miniaturization of the manufacturing process, and the operating speed has been increased due to dramatic improvements in system clocks. It has become difficult to optimize.
Therefore, by providing a fuse element circuit in the semiconductor integrated circuit device and performing various settings of circuit characteristics and operation by cutting / not cutting the fuse element, circuit operation is optimized and yield is improved.

A conventional fuse element circuit generally has a method of fusing a polysilicon fuse element with a laser beam, but recently, a method of blowing a large current through the fuse element is frequently used.
FIG. 5 is an electric circuit diagram of the fuse element circuit in the case of adopting a fusing method by applying a large current.
In the figure, 1 is a power supply terminal, 2 is a write terminal, 3 is a GND terminal, 4 is an output terminal, and a pull-up Pch transistor Q10 is connected between the power supply terminal 1 and the write terminal 2. The fuse element F1 is connected between the write terminal 2 and the GND terminal 3.
A signal is output from the drain of the Pch transistor Q10 to the output terminal 4 via the inverter X1, and is output from the output terminal 4 to the circuit to be set.

  When the fuse element F1 is cut in the circuit configuration, a voltage equivalent to the power supply voltage applied to the power supply terminal 1 is applied to the write terminal 2, and a large current is passed through the fuse element F1 to blow it. That is, in general, the on-resistance of the Pch transistor Q10 is designed to have a high resistance value, and the input impedance of the inverter X1 is sufficiently high. Therefore, when a voltage is applied to the write terminal 2, almost all current is a low resistance fuse. It can be melted by flowing to the element F1.

More specifically, the resistance value of the fuse element F1 is designed to be about 200Ω, and the Pch transistor Q10 is provided to pull up the input of the inverter X1 when the fuse element F1 is disconnected. The on-resistance value is set to a value of several tens of KΩ or more.
Here, when the fuse element F1 is in an uncut state, assuming that the power supply voltage is Vc, the on-resistance of the Pch transistor Q10 is r10, and the resistance value of the fuse element F1 is rf, the voltage at the write terminal 2 is Vc * [rf / ( rf + r10)]. Since rf << r10, the voltage is almost at the GND level (L level), the voltage at the write terminal 2 is inverted by the inverter X1, and the output terminal 4 is at the H level. Will be output.
On the other hand, when the fuse element F1 is blown and disconnected, the voltage at the write terminal 2 is pulled up by the Pch transistor Q10 to the Vc level (H level) of the power supply voltage, which is inverted by the inverter X1. The L level is output from the output terminal 4.
Therefore, according to the fuse element circuit of FIG. 5, the H level information can be obtained from the output terminal 4 if the fuse element F1 is not cut, and the L level information can be obtained if the fuse element F1 is cut.

By the way, the characteristics of the fuse element F1 in the fuse element circuit are required to be about 200Ω when not cut and several hundred KΩ or more when cut.
In particular, in order to bring the voltage of the write terminal 2 to the H level in the disconnected state, it is necessary to have a sufficiently large value with respect to the on-resistance r10 of the Pch transistor Q10. Although it is ideal that the resistance value is large, even if the voltage dividing circuit is configured by incomplete cutting, the voltage dividing result does not become H level unless it is several hundred KΩ or more. The voltage of the write terminal 2 cannot be set correctly.
This means that completeness is required for the cutting of the fuse element F1, and the range of the resistance value for setting the cut state or the non-cut state is strictly limited.

And the following proposal content is disclosed by the following patent documents 1-3 regarding the problem.
First, as shown in FIG. 6, in the fuse element circuit of Patent Document 1, the write terminal 2 is connected to a power supply terminal (VDD terminal) 1 via a depletion type Pch MIS transistor Q11 having a large on-resistance value. The circuit configuration is connected to the GND terminal (VSS terminal) 3 through a series circuit including a fuse element F1, a diode element D11, and a depletion type Nch MIS transistor Q12. However, the on-resistance value of the transistor Q12 is set to be smaller than that of the transistor Q11, and the write terminal 2 is set to L level when the fuse element F1 is not cut, and is set to H level by the transistor Q11 when cut.
In this fuse element circuit, the fuse cutting terminal 5 is connected to the power supply terminal 1 and an H level or an L level is applied to the write terminal 2 from the outside to set the state of the write terminal 2. That is, when adjusting the characteristics of the semiconductor circuit connected to the output terminal 4 via the inverter X1, the characteristic value is measured with the write terminal 2 at the H level or the L level so that it is within the specification standard. The cutting / non-cutting of the fuse element F1 is determined.
In this case, since the fuse cutting power supply terminal 5 is connected to the power supply terminal 1, the current does not flow into the fuse element F1 even if the write terminal 2 is set to the H level. In addition, even when the L level is set, since the diode element D11 is in the reverse voltage application state, only a small current flows from the transistor Q11 side.
That is, according to the fuse element circuit of Patent Document 1, it is possible to determine whether the fuse element F1 is cut or not cut in advance without flowing a large current through the fuse element F1.

As shown in FIG. 7, the fuse element circuit in Patent Document 2 discloses a circuit in which a positive feedback circuit including two inverters X1 and X2 is provided on the output terminal 4 side of the circuit of FIG.
According to this fuse element circuit, even when the fuse element F1 is not completely cut and its resistance value is not slightly different from the on-resistance value of the pull-up transistor Q10, the action of the positive feedback circuit is achieved. Thus, the output from the output terminal 4 can be settled to the H level or the L level. For example, when the resistance value of the fuse element F1 after cutting becomes higher than the on-resistance value of the transistor Q10, the output of the inverter X1 slightly swings to the L side, and the output of the inverter X2 swings further to the H side. Then, the positive feedback is repeated to completely settle at the L level.
That is, according to the fuse element circuit of Patent Document 2, the output of the output terminal 4 can be set to a complete H level or L level even if the fuse element F1 is in an incompletely cut state.

The fuse element circuit of Patent Document 3 also has a positive feedback circuit on the output terminal 4 side as shown in FIG.
However, in this case, the output of the inverter X3 in the series circuit of the inverters X1 and X3 on the output terminal 4 side is connected to the gate of the Pch transistor Q13, and the transistor Q13 is used as an inverter.
According to this fuse element circuit, positive feedback is applied so as to optimize the on-resistance value of the transistor Q13 according to the state of the resistance value of the fuse element F1, for example, when the resistance value of the fuse element F1 is high. The output of the inverter X3 swings to the L side, the on-resistance value of the transistor Q13 decreases, the input voltage to the inverter X3 is increased, and the output is further increased.

Japanese Patent Application Laid-Open No. 10-189741 (page 3, FIG. 1) Japanese Unexamined Patent Publication No. 07-264221 (7th page, FIG. 1 (A)) Japanese Unexamined Patent Publication No. 2002-042482 (FIGS. 2, 5, 6, and 8)

As described above, the fuse element cutting method includes a method of fusing with a laser beam using a laser trimming device. However, when finely adjusting the characteristics of a semiconductor integrated circuit, it is based on an inspection result of an LSI tester. In many cases, the fuse element is cut by supplying a constant current to the fuse element circuit.
However, in the case of the energization cutting method, the current value is limited even though it is a large current, and the energization time is also limited due to the inspection time limitation, so that the fuse element is always in an ideal cutting state. Not limited to this, the resistance value may be in an intermediate state of about several KΩ to several tens of KΩ.

Here, regarding the disclosed technology of each of the above patent documents, in the fuse element circuit of Patent Document 1 (FIG. 6), it is possible to determine whether to disconnect / not disconnect before energization. The forward voltage Veb between the emitters is about 0.7 V. In order to set the output of the inverter X1 to H level when the fuse element F1 is cut, the resistance value after cutting is equal to the on-resistance value of the transistor Q11. It must be the above value, and it is required to have a resistance value of 100 KΩ or more.
Further, in the fuse element circuits of Patent Documents 2 and 3 (FIGS. 7 and 8), even if the cut state of the fuse element F1 is in an intermediate state of about several KΩ to several tens KΩ in resistance value, the output terminal 4 Can be set to either the H level or the L level. However, in order for the output of the output terminal 4 to become the H level corresponding to the cut state of the fuse element F1, the resistance value after the cut is also turned on for the transistors Q10 and Q13. Must be equal to or greater than the resistance value.
That is, the disclosed technologies of the above-mentioned patent documents are based on the premise that the fuse element F1 is in a completely cut state (resistance value is infinite) or a complete non-cut state (resistance value is 0). Does not assume the existence of intermediate states that occur over a fairly wide range of resistance values.
Therefore, even if it is thought that the fuse element F1 is cut by supplying a large current, there is a case where the semiconductor integrated circuit is not properly adjusted because the semiconductor integrated circuit is actually in the intermediate state. The entire semiconductor integrated circuit becomes a defective product only by the state, and the inspection result is not reflected in the adjustment, resulting in a great waste of inspection cost.
Further, a semiconductor integrated circuit is often adjusted by combining a plurality of fuse element circuits, and the probability of the disadvantage increases in proportion to the number of combinations.

  Accordingly, the present invention provides a fuse element circuit of a semiconductor integrated circuit device, in which a fuse element cutting process and an output state of an output terminal even if an incomplete cutting state occurs when the fuse element is cut. Was created for the purpose of providing a circuit configuration improved so as to correspond without error.

  The present invention relates to a fuse element circuit of a semiconductor integrated circuit device, wherein a series circuit including a first transistor and a fuse element is provided between a current output terminal of one transistor of a current mirror circuit and a ground circuit. A series circuit composed of a second transistor and a resistor is connected between the current output terminal of the other transistor and the ground circuit, and the current control terminals of the first transistor and the second transistor are the same. And a voltage level corresponding to a non-cut state and a cut state of the fuse element is output from any one of the current output terminals, and the resistance value of the resistor is It is assumed that the resistance value of the fuse element in a non-cut state is sufficiently larger than the resistance value of the fuse element, resulting in an incomplete cut state. Serial according to fuse element circuit of the semiconductor integrated circuit device being characterized in that set to be smaller than the minimum resistance value of the fuse element.

The fuse element circuit according to the present invention operates as follows.
First, the current mirror circuit has a function of outputting a current of the same magnitude from the current output terminal of each transistor constituting the circuit.
On the other hand, when the fuse element is not cut, a large current flows on the first transistor side. Conversely, when the fuse element is cut, a large current flows on the second transistor side.
Therefore, in any state, an imbalance occurs with respect to the function of the current mirror circuit. In order to compensate for this and output the same current, the transistor on the current mirror circuit side or the first or The voltage between the input and output terminals of the second transistor changes.
In the fuse element circuit of the present invention, the change in the voltage level is an output corresponding to non-cut / non-cut of the fuse element of the fuse element circuit.
By the way, in the present invention, an imbalance of the currents flowing through the first transistor and the second transistor is caused by the relationship between the resistance and each resistance value of the fuse element, but the resistance value of the resistor is in an uncut state. It is set on the condition that it is sufficiently larger than the resistance value of the fuse element and smaller than the minimum resistance value of the fuse element that is assumed in the case of an incompletely cut state.
According to the conditions regarding the resistance, even if the fuse element is in an incompletely cut state and exhibits a low resistance value, the current flowing to the second transistor side is always larger than that on the first transistor side. Thus, an output corresponding to the cutting of the fuse element is obtained based on the compensation action.
Although the present invention is effective for a method of cutting a fuse element by energizing a large current, it is natural that it can be applied to a fusing method using a laser beam.

In the above invention, the circuit for obtaining the output corresponding to the cutting / non-cutting of the fuse element is configured on the current output side of the current mirror circuit, but may be configured on the current input side of the current mirror circuit. Has the following structure, and the same operation and effect can be obtained.
In a fuse element circuit of a semiconductor integrated circuit device, a series circuit including a first transistor and a fuse element is provided between a current input terminal of one transistor of a current mirror circuit and a power supply circuit, and the other transistor of the current mirror circuit is provided. A series circuit composed of a second transistor and a resistor is connected between the current input terminal and the power supply circuit, and the same bias voltage is applied to each current control terminal of the first transistor and the second transistor. And having a circuit configuration that outputs a voltage level corresponding to a non-cut state and a cut state of the fuse element from any one of the current input terminals, and the resistance value of the resistor is set to a non-cut state. The fuse element is sufficiently larger than the resistance value of the fuse element in the above, and the fuse assumed in the case of an incompletely cut state is obtained. Fuse element circuit of the semiconductor integrated circuit device being characterized in that set to be smaller than the minimum resistance value of the element.

According to the present invention, in the fuse element circuit of the semiconductor integrated circuit device, even when the fuse element is cut, even if it is in an incompletely cut state showing a resistance value of about several KΩ to several tens KΩ, the output level Can be made to correspond to the cutting process.
Thereby, the inspection result of the semiconductor integrated circuit is correctly reflected in the adjustment, and it is prevented that the semiconductor integrated circuit is determined to be defective due to the incompatibility between the cutting process of the fuse element and the output level.

Hereinafter, embodiments of a fuse element circuit of a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the drawings.
Even if the fuse element circuit of each embodiment does not become a complete cut state when the fuse element is cut, but is in an intermediate state that shows a resistance value of about several KΩ to several tens KΩ, the output of the fuse element circuit Indicates a unique state (H level or L level) associated with the cutting of the fuse element.

First, FIG. 1 is an electric circuit diagram of a fuse element circuit according to this embodiment.
This fuse element circuit uses a current mirror circuit composed of two Pch transistors Q3 and Q4.
Then, the drains of two Nch transistors Q1 and Q2 whose gates are commonly connected are connected to the drains of the transistors Q3 and Q4 of the current mirror circuit, respectively, and the fuse element F1 is connected to the source of the transistor Q1 and the transistor A resistor R1 is connected to the source of Q2.
The Pch transistor Q5 and the Nch transistor Q6 constitute a constant voltage circuit for applying a common bias voltage to the gates of the transistors Q1 and Q2.
The output of the fuse element circuit is taken out from the node 6 at the connection point of the transistors Q2 and Q4 to the output terminal 4 via the inverter X1.

For simplicity of explanation, the transistors Q1 and Q2 and the transistors Q3 and Q4 have the same characteristics, the gate threshold voltage and the like are the same, and the gate-source voltage and the source-drain voltage are the same. If the voltage between them is the same, the same current flows through the drain.
This identity of characteristics can be easily obtained by making the transistors have the same structure and dimensions in the same chip of the semiconductor integrated circuit and arranging them closely.

In the fuse element circuit of this embodiment, the resistance value rf when the fuse element F1 is not cut is assumed to be about 200Ω, and the minimum resistance value when the fuse element F1 is cut incompletely is assumed to be about 3KΩ. The resistance value r1 of the resistor R1 is set to 2 KΩ. That is, the resistance value r1 of the resistor R1 is sufficiently larger than the resistance value rf when the fuse element F1 is not cut.
Now, when the fuse element F1 is a non-cutting state, the gate voltage of the transistors Q1, Q2 are identical on the gate bias voltage from the transistor Q6, since it is Rf«r1, the drain current I ₁ of transistor Q1 The drain current I ₂ of the transistor Q2 has a relationship of I ₁ > I ₂ .
However, the drain currents I ₃ and I ₄ of the transistors Q 3 and Q ₄ constituting the current mirror circuit must be equal, and the drain current I ₃ of the transistor Q ₃ is the drain current I ₁ of the transistor Q ₁ . The drain current I ₄ of the transistor Q4 is output as I ₄ ≈I ₁ .
That is, a current relationship of I ₄ > I ₂ occurs at the node 6.

By the way, the input impedance of the inverter X1 composed of CMOS is extremely large, and the input current from the node 6 (in particular, the DC current as in this case) can be regarded as zero.
Under the conditions, the relationship of I ₄ > I ₂ must be set to the relationship of I ₄ = I ₂ , and for this reason, the voltage between the source and the drain of the transistor Q ₄ decreases, and thereby the magnitude of the current I ₄ As I becomes smaller, the relationship of I ₄ = I ₂ is established.
As a result, the voltage of the node 6 rises to the power supply voltage side, and the output of the output terminal 4 obtained through the inverter X1 becomes L level.

Next, when the fuse element F1 is cut by supplying a large current from the write terminal 2, the resistance value is infinite or several MΩ or more if it is in an ideal cut state.
In this state, the gate voltage of the as well as the transistors Q1, Q2 is is the same, because it is Rf»r1, the drain current I ₂ of the drain current I ₁ and the transistor Q2 of the transistor Q1 is opposite to the said The relationship is I ₁ <I ₂ .
On the other hand, based on the configuration of the current mirror circuit, I ₃ = I ₄ must be satisfied, and I ₃ = I ₁ is the same as described above, and the drain current I ₄ of the transistor Q ₄ is I ₄ ≈I _1. Is output as
In other words, the current relationship of I ₄ <I ₂ occurs at the node 6 in the opposite manner.

The current cannot flow from the inverter X1 side to the node 6, and the relationship of I ₄ <I ₂ must be set to the relationship of I ₄ = I ₂ under the conditions. In this case, the source of the transistor Q2 The voltage between the drains is lowered, and the magnitude of the current I ₂ is thereby reduced, thereby establishing the relationship of I ₄ = I ₂ .
As a result, the voltage at the node 6 decreases to the GND voltage side, and the output of the output terminal 4 obtained through the inverter X1 becomes H level.
From the above, in the fuse element circuit of this embodiment, similarly to the fuse element circuit of FIG. 5, the output of the output terminal 4 is set to L level when the fuse element F1 is not cut and the output terminal 4 of the fuse element F1 is cut. The output is set to H level.

By the way, in the above description, it is assumed that the fuse element F1 is ideally disconnected and its resistance value is infinite or several MΩ or more, but incomplete disconnection is made to be several KΩ to several tens KΩ. Let us consider the case of an intermediate state showing a relatively low resistance value.
In the fuse element circuit of this embodiment, when the fuse element F1 is cut, the drain current I ₁ of the transistor Q1 and the drain current I _{2 of the} transistor Q2 have a relationship of I ₁ <I _2. Is reduced to the GND voltage side, and the output of the output terminal 4 is set to the H level. The condition for satisfying the relationship of I ₁ <I ₂ is rf (resistance value of the fuse element F 1)> r 1 (resistance value of the resistor R 1 ).
In this embodiment, r1 is set to 2 KΩ, and if the resistance value rf at the time of incomplete cutting of the fuse element F1 is about several KΩ to several tens KΩ as described above, then rf> r1 is established. When the element F1 is cut, the relationship of I ₁ <I ₂ is always established.
In order to invert the output of the inverter X1 by lowering the voltage at the node 6, a difference greater than a predetermined value is required between I ₂ and I ₁ , but a very large current difference is not required.

FIG. 2 is a graph in the case of simulating the voltage change of the node 6 when rf is changed with r1 = 2 KΩ.
In the figure, the voltage of the node 6 swings to the power supply voltage side when the fuse element F1 is not cut (in this example, the resistance value is 1 KΩ or less) and is 4 V or more. In a state where the value is 3 KΩ or more), it swings to the GND side and is 0.5 V or less.
When rf is in the range of 1 to 3 KΩ and is close to r1 in an incompletely cut state, the voltage at node 6 indicates an intermediate level. Even in this state, the fuse element If the resistance value of F1: rf changes to 3 KΩ or more, the output of the inverter X1 clearly shows the H level.
When this is compared with the prior arts (Patent Documents 1 to 3), in those prior arts, when the fuse element F1 is in an incompletely cut state, the resistance value rf is the on-resistance value of the transistor Q10 or the like. However, according to this embodiment, the fuse element F1 is in an incompletely disconnected state. However, according to this embodiment, the fuse element F1 is in an incompletely cut state. Even in this case, the cutting process of the fuse element F1 and the L level setting of the output terminal 4 can be made to correspond to each other under the extremely relaxed condition that rf is 3 KΩ or more.

The condition relating to the resistance value in the incompletely cut state of the fuse element F1 can be changed depending on how the resistance value r1 of the resistor R1 is set.
Further, in this embodiment, the inverter X1 is used. However, if a comparator is used, the range in which the resistance value: rf is in an intermediate state (corresponding to the range of 1 to 3 KΩ in FIG. 2) depending on how the threshold value is set. ) Can be narrowed.

FIG. 3 is an electric circuit diagram of the fuse element circuit according to this embodiment.
As is clear from comparison between FIG. 1 and FIG. 1, the fuse element circuit of this embodiment differs from that of Embodiment 1 in that the insertion positions of the fuse element F1 and the resistor R1 with respect to the current mirror circuit are reversed. It ’s just that.
That is, in this embodiment, the resistor R1 is connected between the control side transistor Q1 and the GND node in the current mirror circuit, and the fuse element F1 is connected between the controlled side transistor Q2 and the GND node. The write terminal 2 is connected to the connection point of the element F1.

The circuit operation is basically the same as that in the first embodiment, and the voltage level of the node 6 corresponding to the cut / non-cut state of the fuse element F1 is reversed from that in the first embodiment. Accordingly, the level of the output terminal 4 is only reversed.
Therefore, only the operation will be briefly described here.
First, in the uncut state of the fuse element F1, since rf << r1, the current relationship is I2> I1, but the current mirror circuit functions so that I4≈I1. Therefore, although I2> I4, there is no current flowing from the inverter X1 side to the node 6, so that the voltage between the source and drain of the transistor Q4 increases in order to reduce the unbalance. As a result, the node 6 becomes L level, and the output terminal 4 via the inverter X1 becomes H level.
On the other hand, in the state where the fuse element F1 is cut, since rf> r1, the current relationship is I2 <I1, but the current mirror circuit functions so that I4≈I1 as described above. Therefore, contrary to the above, I2 <I4, but since no current flows from the node 6 to the inverter X1 side, the voltage between the source and drain of the transistor Q2 is lowered to reduce the unbalance. As a result, the node 6 becomes H level, and the output terminal 4 via the inverter X1 becomes L level.

  In this embodiment, only the setting level of the output terminal corresponding to the cutting / non-cutting of the fuse element F1 is opposite to that in the first embodiment, and the fuse element F1 is in an incompletely cut state. Even in this case, the basic effect that the cutting process of the fuse element F1 and the L level setting of the output terminal 4 can be made to correspond with each other under the condition that allows the cutting state to have a relatively low resistance value. Same as the case.

FIG. 4 is an electric circuit diagram of the fuse element circuit according to this embodiment.
As is clear from comparison between FIG. 1 and FIG. 1, the fuse element circuit of this embodiment is different from that of the first embodiment only in that a resistor R2 is connected in parallel to the non-fuse element F1. .
The resistor R2 is provided to prevent the circuit operation from becoming unstable due to the source of the transistor Q1 being opened when the fuse element F1 is cut, and the resistance value r2 is the resistance value r2. It is set to a value that is at least 10 times the resistance value r1.

The basic operation and effect of the fuse element circuit itself of this embodiment are the same as those of the first embodiment. Here, the function performed by the resistor R2 and the influence on the basic operation will be described.
First, in the uncut state of the fuse element F1, of course, rf (resistance value of the fuse element F1) << r2 (resistance value of the resistance R2), so that the resistance R2 has little influence on the circuit operation of the fuse element circuit. .
On the other hand, the fuse element F1 is cut, the size of the drain current I ₁ of transistor Q1 is determined by the resistance value r2 of the resistor R2, because it is set as the as r2 ≧ 10 * r1 I1 < The current relationship of I2 is sufficiently established, and in this case, there is no problem with respect to the circuit operation of the fuse element circuit.
However, when the fuse element F1 is cut incompletely and exhibits a relatively low resistance value rf, the resistance R2 causes an increase in the current I1 as a parallel resistance. In this case also, for example, the resistance value rf Only the resistance value r2 = 20 KΩ is connected in parallel to = 3 KΩ, and the resistance value is about 2.6 KΩ, so the operation range does not change much.
That is, according to this embodiment, a stable circuit operation when the fuse element F1 is cut is realized without affecting the basic circuit operation.

Although the embodiments of the fuse element circuit of the present invention have been described above, the following modifications are also conceivable.
(1) The same effect can be obtained by reversing the channel characteristics of each transistor by reversing the power supply side and the GND side. Specifically, the transistors Q3 and Q4 are connected to the GND side as Nch transistors, and the transistors Q1 and Q2 are connected as Pch transistors to the power supply side through the fuse element F1 and the resistor R1, respectively. In addition, the bias circuits of the transistors Q5 and Q6 are similarly replaced.
That is, in each of the above embodiments, the circuit for obtaining the output level corresponding to the cutting / non-cutting of the fuse element is configured on the current output side of the current mirror circuit, but is configured on the current input side of the current mirror circuit. Of course, the same effect can be obtained.
(2) In each of the above embodiments, each transistor is configured as a MOS type, but all or a part of them may be replaced with a bipolar type.
(3) Although the basic form of the Wilson type current mirror circuit is used in each of the above-described embodiments, a circuit with improved characteristics as shown in, for example, JP-A-6-104762 may be applied.

  The present invention is applied to a fuse element circuit incorporated for characteristic adjustment, operation switching, and the like of a semiconductor integrated circuit.

1 is an electric circuit diagram of a fuse element circuit of a semiconductor integrated circuit device according to Example 1 of the present invention. In the electric circuit of FIG. 1, a graph simulating a change in voltage at the node 6 when the resistance value r1 of the resistor R1 is 2 KΩ and the resistance value rf of the fuse element F1 is changed. 6 is an electric circuit diagram of a fuse element circuit according to Embodiment 2. FIG. 6 is an electric circuit diagram of a fuse element circuit according to Example 3. FIG. It is an electric circuit diagram of a conventional general fuse element circuit. 2 is an electric circuit diagram of a fuse element circuit disclosed in Patent Document 1. FIG. 10 is an electric circuit diagram of a fuse element circuit disclosed in Patent Document 2. FIG. FIG. 6 is an electric circuit diagram of a fuse element circuit disclosed in Patent Document 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Power supply terminal, 2 ... Write terminal, 3 ... GND terminal, 4 ... Output terminal, 5 ... Terminal for fuse cutting, 6 ... Node, D11 ... Diode element, F1 ... Fuse element, I1, I2, I4 ... Current, Q1 , Q2, Q6, Q12 ... Nch transistors, Q3, Q4, Q5, Q11 ... Pch transistors, R1, R2 ... resistors, X1, X2, X3 ... inverters.

Claims (2)

In a fuse element circuit of a semiconductor integrated circuit device,
A series circuit composed of a first transistor and a fuse element is provided between the current output terminal of one transistor of the current mirror circuit and the ground circuit, and the current output terminal of the other transistor of the current mirror circuit is connected to the ground circuit. A series circuit composed of a second transistor and a resistor is connected between them, and the same bias voltage is applied to each current control terminal of the first transistor and the second transistor, and each current output is applied. It has a circuit configuration for outputting a voltage level corresponding to the non-cut state and the cut state of the fuse element from any one of the terminals, and the resistance value of the resistor is set to the resistance value of the fuse element in the non-cut state Is set to be sufficiently smaller than the minimum resistance value of the fuse element assumed in the case of an incompletely cut state. A fuse element circuit of a semiconductor integrated circuit device. In a fuse element circuit of a semiconductor integrated circuit device,
A series circuit composed of a first transistor and a fuse element is provided between the current input terminal of one transistor of the current mirror circuit and the power supply circuit, and between the current input terminal of the other transistor of the current mirror circuit and the power supply circuit. Are connected to a series circuit composed of a second transistor and a resistor, respectively, and the same bias voltage is applied to each current control terminal of the first transistor and the second transistor. It has a circuit configuration for outputting a voltage level corresponding to a non-cut state and a cut state of the fuse element from any one, and the resistance value of the resistor is set to be higher than the resistance value of the fuse element in the non-cut state. It is set to be smaller than the minimum resistance value of the fuse element that is assumed to be sufficiently large and incompletely cut. A fuse element circuit of a semiconductor integrated circuit device.

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