JP2005303764A - Electronic tuner, integrated circuit used therefor, and high-frequency signal receiver using the electronic tuner - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a compact electronic tuner by closely arranging inductors for antenna tuning at a plurality of reception circuit sections or inductors for inter-stage tuning without mutually using any partition boards for high-frequency shield. <P>SOLUTION: In each turning circuit for composing the plurality of reception circuit sections, at least one damping circuit is provided and the inductor for turning at the reception circuit section that is set to be inoperative is damped by the damping circuit, thus damping the inductor for antenna tuning provided at the inoperative reception circuit section or that for inter-stage tuning by each damping circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic tuner or the like having a plurality of reception bands.

  Hereinafter, the conventional electronic tuner has the configuration shown in FIG. That is, in FIG. 13, the high-frequency input signal input from the input terminal 1 is divided into a high frequency and a low frequency by the duplexer 2 and input to the receiving circuit units 3 and 4, respectively. The outputs of the receiving circuit units 3 and 4 are connected to the input terminals 5a and 5b of the mixing circuit unit 5, respectively.

  The receiving circuit unit 3 includes an antenna tuning circuit 6 composed of a parallel connection body of a tuning capacitor 6a and a tuning inductor 6b connected between the input and the ground, an amplifier 7 to which an output of the antenna tuning circuit 6 is connected, An interstage tuning circuit 8 composed of a parallel connection body of a tuning capacitor 8a and a tuning inductor 8b connected between the output of the amplifier 7 and the ground, and a tuning inductor 9a inductively coupled to the tuning inductor 8b are tuned. The interstage tuning circuit 9 is composed of a parallel connection body composed of a capacitor 9b, and an output terminal 3b to which the output of the interstage tuning circuit 9 is connected.

  The receiving circuit unit 4 includes an antenna tuning circuit 10 including a parallel connection body of a tuning capacitor 10a and a tuning inductor 10b connected between an input and the ground, and an amplifier 11 to which an output of the antenna tuning circuit 10 is connected. An interstage tuning circuit 12 comprising a parallel connection body of a tuning capacitor 12a and a tuning inductor 12b connected between the output of the amplifier 11 and the ground, a tuning inductor 13a inductively coupled to the tuning inductor 12b, and a tuning The interstage tuning circuit 13 composed of a parallel contact made of a capacitor 13b and an output terminal 4b to which the output of the interstage tuning circuit 13 is connected are configured.

  The mixing circuit unit 5 includes an electronic switch 14 having one input terminal 14a to which the input terminal 5a is connected and an input terminal 14b to which the input terminal 5b is connected, and the common terminal 14c of the electronic switch 14 has one input. A mixer 15 connected to the oscillator 15, an oscillator 17 having an oscillation tuning circuit 16 connected to the other input of the mixer 15 and composed of a parallel connection body of a tuning inductor 16a and a tuning capacitor 16b, and a mixer 15 And an amplifier 19 connected between the output terminal 18 and the output terminal 18.

  The operation of the electronic tuner configured as described above will be described below. PLL control data from the control unit is input to the PLL control unit 20 via the PLL control terminal 20A. Based on the PLL control data, one of the receiving circuit units 3 and 4 is selected, and the electronic switch 14 is controlled so that the output signal of the selected receiving circuit unit is output from the common terminal 14c.

  Further, the tuning capacitors 6a, 8a, 9b, 10a, 12a, and 13b are set to predetermined capacitance values by the tuning voltage from the output 20b of the PLL controller 20, so that the antenna tuning circuits 6 and 10 and the stage The inter-tuning circuits 8, 9, 12, and 13 can select a desired signal.

  As described above, the high frequency input signal input to the input terminal 1 is selected by the tuning circuit 3 or 4 and then the signal converted to the intermediate frequency by the mixer 15 is output from the output terminal 18. It was.

As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
JP-A-4-379918

  However, in such a conventional electronic tuner, when the size is simply reduced, the coils 6b and 10b, the coils 8b and 9a, and the coils 12b and 13a are close to each other. High frequency coupling occurred.

  As a result, when the receiving circuit unit 4 receives, for example, an input signal having a low frequency, the selection characteristic in the high frequency region deteriorates, and thus interference due to the high frequency signal occurs. Similarly, when a high frequency signal is received by the receiving circuit unit 3, for example, the selection characteristic in a higher frequency range is deteriorated, and interference due to a higher frequency signal occurs.

  Therefore, the antenna tuning coils and the interstage tuning coils are spaced apart from each other, or a shielding metal plate is inserted. Therefore, there is a problem that a small high-frequency receiving device cannot be realized.

  Therefore, the present invention solves this problem and aims to realize a small-sized electronic tuner.

  In order to achieve this object, an electronic tuner of the present invention is provided with at least one damping circuit for each tuning circuit constituting a plurality of receiving circuit units, and for tuning a receiving circuit unit which is inactive. The inductor is damped by the damping circuit. Thereby, a small-sized electronic tuner can be realized.

  As described above, according to the present invention, the antenna tuning inductor or the interstage tuning inductor provided in the non-operating receiving circuit unit is damped by the respective damping circuits. Therefore, the antenna tuning inductor or the interstage tuning inductor of the selected receiving circuit unit is not affected by the high frequency coupling with the antenna tuning inductor or the interstage tuning inductor of the receiving circuit unit which is not operated. That is, there is no deterioration of the selection characteristics in the selected receiving circuit unit.

  In addition, the antenna tuning inductors or the interstage tuning inductors of a plurality of receiving circuit units can be arranged close to each other without using a partition plate for high-frequency shielding, so that the small size. Can be realized.

(Embodiment 1)
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an electronic tuner according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 21 denotes an input terminal to which a high frequency input signal is input. The input terminal 21 is connected to the common terminal 22 a of the duplexer 22. The output terminals 22b and 22c of the duplexer 22 are connected to the inputs 23a and 24a of the receiving circuit units 23 and 24, respectively.

  Here, it is assumed that the receiving circuit unit 23 receives a high frequency in the input signal, and the receiving circuit unit 24 receives a low frequency in the input signal.

  Outputs 23b and 24b of the receiving circuit units 23 and 24 are connected to input terminals 26a and 26b of the mixing circuit unit 26, respectively. The output of the mixing circuit unit 26 is connected to the output terminal 27.

  The receiving circuit unit 23 is connected to an input 23a, and a tuning circuit 28 in which a tuning capacitor 28a and a tuning inductor 28b are connected in parallel, an amplifier 29 connected to the output of the tuning circuit 28, and the amplifier And a tuning circuit 30 composed of a tuning capacitor 30a and a tuning inductor 30b, and a tuning circuit 31 composed of a tuning capacitor 31b and a tuning inductor 31a. The output of the tuning circuit 30 is connected to the input terminal 26a of the mixing circuit unit 26 via the output terminal 23b.

  The inductor 30b of the tuning circuit 30 and the inductor 31a of the tuning circuit 31 are configured as inductive coupling, and the tuning circuits 30 and 31 form a double tuning circuit.

  Further, a damping circuit 32 is connected in parallel between the tuning circuit 28 and the ground. Damping circuits 33 and 34 are connected between the input of the tuning circuit 30 and the ground and between the output of the tuning circuit 31 and the ground, respectively.

  Similarly, the receiving circuit unit 24 includes a tuning circuit 35 connected to the input 24a and connected in parallel with a tuning capacitor 35a and a tuning inductor 35b, and an amplifier 36 connected to the output of the tuning circuit 35. The tuning circuit 37 is connected to the output of the amplifier 36 and is composed of a tuning capacitor 37a and a tuning inductor 37b. The tuning circuit 38 is composed of a tuning capacitor 38b and a tuning inductor 38a. The output of the tuning circuit 38 is connected to the input terminal 26b of the mixing circuit unit 26 via the output terminal 24b.

  The inductor 37b of the tuning circuit 37 and the inductor 38a of the tuning circuit 38 are configured as inductive coupling, and the tuning circuits 37 and 38 form a double tuning circuit.

  Further, a damping circuit 39 is connected between the output of the tuning circuit 35 and the ground. Damping circuits 40 and 41 are connected between the input of the tuning circuit 37 and the ground and between the output of the tuning circuit 38 and the ground, respectively.

  The mixing circuit unit 26 includes a changeover switch 51 in which the input terminals 26a and 26b are connected to the input terminals 51a and 51b, and a mixer 52 in which the common terminal 51c of the changeover switch 51 is connected to one input. An oscillator 53 connected to the other input of the mixer 52, an oscillation tuning circuit 54 connected to the oscillator 53 and composed of a parallel connection circuit in which a capacitor 54a and an inductor 54b are connected in parallel, and the mixer And an amplifier 55 connected between the output 52 and the output terminal 27.

  Further, the output signal from the oscillator 53 is connected to the input 60 a of the PLL controller 60. A tuning voltage is output from the output 60 b of the PLL controller 60. When this tuning voltage is applied to the capacitor 54a, the oscillator 53 has a predetermined oscillation frequency. At the same time, the tuning voltage from the output 60b is supplied to the capacitors 28a, 30a, 31b, 35a, 37a, and 38b.

  The output 60c of the PLL control unit 60 is connected to the damping circuits 32, 33, 34, 39, 40, and 41, and each damping circuit can be independently controlled on and off by the output voltage from the output 60c. A PLL control terminal 61 is connected to the input 60d of the PLL control unit 60, and PLL control data from the control unit is input.

  The operation of the electronic tuner configured as described above will be described with reference to FIG. A data signal for PLL control is input to the input 60 d of the PLL control unit 60. Depending on the output voltage from the output 60 c of the PLL control unit 60, power is supplied to either the receiving circuit unit 23 or 24. Thus, for example, when receiving a high frequency, the receiving circuit unit 23 is in an operating state, and when receiving a low frequency, the receiving circuit unit 24 is in an operating state.

  At the same time, the changeover switch 51 of the mixing circuit unit 26 is switched by the output 60c from the PLL control unit 60 so that the output from the receiving circuit unit in the operating state is selected.

  Further, the oscillation signal of the oscillator 53 is input to the input 60 a of the PLL control unit 60. The oscillation frequency of this oscillation signal is compared with a reference frequency in the PLL control unit 60. Further, the tuning voltage from the output 60 b of the PLL controller 60 is applied to the tuning capacitor 54 a of the oscillation tuning circuit 54 of the oscillator 53. In this way, the oscillator 53 is PLL-controlled and can have a predetermined oscillation frequency.

  The tuning voltage from the output 60b is also supplied to the tuning capacitors 28a, 30a, 31b, 35a, 37a, and 38b constituting the tuning circuits 28, 30, 31, 35, 37, 38, and 54, respectively. Thereby, the tuning frequency of the tuning circuits 28, 30, 31, 35, 37, 38, 54 becomes a predetermined frequency. In this way, either the receiving circuit unit 23 or 24 is selected based on the PLL control data input to the PLL control terminal 61.

  First, the receiving circuit unit 23 will be described. The high frequency input signal input to the input terminal 21 is input to the common terminal 22 a of the duplexer 22. A high frequency input signal is output from the output 22 b of the duplexer 22. This high frequency input signal is supplied to the input 23 a of the receiving circuit unit 23. The high frequency input signal input to the input 23 a is amplified by the amplifier 29 after the desired signal is selected by the antenna tuning circuit 28. The output signal from the amplifier 29 is further selected by the interstage tuning circuits 30 and 31. This desired signal is output from the output 23b. This desired signal is output from the output 23 b and supplied to the input terminal 26 a of the mixing circuit unit 26.

  Next, the receiving circuit unit 24 will be described. A low frequency input signal is output from the output 22 c of the duplexer 22. This low frequency input signal is supplied to the input 24 a of the receiving circuit unit 24. The low frequency input signal input to the input 24 a is amplified by the amplifier 36 after the desired signal is selected by the antenna tuning circuit 35. The output signal from the amplifier 36 is further selected by the interstage tuning circuits 37 and 38 as desired signals. This desired signal is output from the output 24 b and supplied to the input terminal 26 b of the mixing circuit unit 26.

  Further, the mixing circuit unit 26 will be described. Outputs from the input terminals 26a and 26b are connected to the input terminals 51a and 51b of the changeover switch 51, respectively. In the changeover switch 51, the input terminals 51a and 51b are selected so that the output of the selected receiving circuit unit is selected.

  An output signal from the output 51 c of the changeover switch 51 is supplied to one input of the mixer 52. An output signal from the oscillator 53 is supplied to the other input of the mixer 52, so that an intermediate frequency signal is output from the output of the mixer 52. The intermediate frequency signal is amplified by the amplifier 55 and then output from the output terminal 27.

  Next, the damping circuits 32, 33, 34, 39, 40, and 41 will be described. These damping circuits 32, 33, 34, 39, 40, and 41 are composed of electronic switches. By connecting both ends of these electronic switches, they are short-circuited in high frequency. The damping circuits 32, 33, 34, 39, 40, and 41 are controlled to be shorted or opened by a damping control voltage from the output 60 c of the PLL control unit 60.

  For example, a case where the receiving circuit unit 23 is selected and the receiving circuit unit 24 is not operated will be described. In the receiving circuit unit 23, the damping circuits 32, 33, and 34 are opened, and only the desired signal is selected. On the other hand, in the reception circuit unit 24, the antenna tuning circuit 35 and the interstage tuning circuits 37, 38 are damped with the damping circuits 39, 40, 41 short-circuited.

  FIG. 2 is a component arrangement diagram of the electronic tuner according to the first embodiment. FIG. 1 shows a case where there are two receiving circuit units, but FIG. 2 shows three receiving circuit units. In addition, the parts used in FIG. 1 are the same as those in FIG.

  In FIG. 2, 21 is an input terminal. Reference numeral 70 denotes a metal case in which the receiving circuit units 23 and 24, the mixing circuit unit 26, and the PLL control unit 60 are housed. Reference numeral 70a denotes a metal partition plate for preventing the antenna tuning circuits 28, 35 and the interstage tuning circuits 30, 31, 37, 38 from being coupled at a high frequency. Similarly, reference numeral 70b denotes a metal partition plate for preventing the interstage tuning circuits 30, 31, 37, and 38 and the mixing circuit unit 26 including the oscillator 53 from being coupled at a high frequency.

  Reference numeral 71 denotes an antenna tuning inductor of the third receiving circuit unit. Reference numeral 72 denotes an interstage tuning inductor located near the input terminal 21 of the third receiving circuit unit. 73 is an interstage tuning inductor located near the output terminal 27 of the third receiving circuit section. Reference numeral 54b denotes an oscillation tuning inductor of the oscillation tuning circuit 54, which is composed of three oscillation tuning inductors corresponding to the three receiving circuit units.

  As described above, in the small-sized electronic tuner, the antenna tuning inductors 28b, 35b, 71 are close to each other, the interstage tuning inductors 30b, 37b, 72 are close to each other, and the interstage tuning inductors 31a, 38a, 73 are close to each other. They will be close to each other. As a result, the coils are inductively coupled to each other, and a high frequency effect is generated.

  FIG. 14A is a diagram of the interstage tuning circuits 9 and 13 of the electronic tuner in the conventional example. 14A, the same components as those in FIG. 13 are denoted by the same reference numerals, and the description thereof is simplified.

  In FIG. 14A, interstage tuning inductors 9a and 13a and interstage tuning capacitors 9b and 13b are shown as components of the interstage tuning circuits 9 and 13, respectively. When the interstage tuning inductors 9a and 13a come close to each other, inductive coupling occurs.

  FIG. 14B is an equivalent circuit diagram of the interstage tuning circuit of the electronic tuner in the conventional example. In FIG. 14B, the coupling inductance by inductive coupling by the interstage tuning inductors 9a and 13a is 81. As a result of the coupling inductance 81, the interstage tuning inductors 9a and 13a have inductance values 82 and 83, respectively, with the inductance value decreasing by the amount of the coupling inductance.

  FIG. 15 shows impedance characteristics of the interstage tuning circuit 9 of the electronic tuner in the conventional example. In FIG. 15, (A) represents the frequency, (B) represents the impedance, and 87 represents the characteristic impedance of the conventional example.

  In FIG. 15, 88 is a series resonance frequency by the series circuit 84 of the interstage tuning capacitor 13 b and the inductor 83. Furthermore, 89 is a parallel resonance frequency by the parallel circuit 85 of the series circuit 84 and the coupled inductor 81. Reference numeral 90 denotes a series resonance frequency by a series circuit of the parallel circuit 85 and the inductor 82. Further, 91 is a parallel resonance frequency mainly due to a parallel circuit of the interstage tuning capacitor 9b and the inductances 81 and 82. FIG. 16 shows the selection characteristic with respect to the frequency of the interstage tuning circuit 9 of the electronic tuner in the conventional example. In addition, about the frequency used in FIG. 16, the same number is attached about the same thing as FIG. 15, and description is simplified. Further, (A) represents the frequency, (C) represents the attenuation amount, and 93 represents the selection characteristic of the interstage tuning circuit 9.

  In FIG. 16, the selection characteristic of the interstage tuning circuit 9 is a blocking region at the series resonance frequencies 88 and 90, as is clear from the impedance characteristic of FIG. 15. The parallel resonance frequency 91 is a pass band through which a desired signal passes. In addition, the parallel resonance frequency 89 is deteriorated in selection characteristics at a frequency higher than the parallel resonance frequency 91. Due to the deterioration of the selection characteristics, the interference signal cannot be eliminated and the reception performance is deteriorated.

  FIG. 3A is a circuit diagram of the interstage tuning circuits 31 and 38 in the first embodiment. 3A, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is simplified.

  In FIG. 3A, interstage tuning inductors 31a and 38a and interstage tuning capacitors 31b and 38b, which are components of the interstage tuning circuits 31 and 38, are shown. When the interstage tuning inductors 31a and 38a are close to each other, inductive coupling occurs.

  FIG. 3B is an equivalent circuit diagram of the interstage tuning circuit 31 according to the first embodiment. In FIG. 3B, the coupling inductance by inductive coupling by the interstage tuning inductors 31a and 38a is 96. As a result of this coupling inductance 96, the interstage tuning inductors 31a and 38a have inductance values 97 and 98, respectively, with their inductance values decreasing by the amount of the coupling inductance. Reference numeral 99 denotes a short-circuit inductance when the electronic switch 41 is short-circuited.

  FIG. 4 is an impedance characteristic diagram of the interstage tuning circuit 31 of the electronic tuner according to the first embodiment. Further, (A) represents the frequency and (B) represents the impedance, and the impedance characteristic of the interstage tuning circuit 31 is 108.

  In FIG. 4, 104 is a series resonance frequency by the series circuit 101 of the parallel circuit 100 and the inductor 98. Reference numeral 105 denotes a parallel resonance frequency by the parallel circuit 101 of the parallel circuit 100 and the coupled inductor 96. Reference numeral 106 denotes a series resonance frequency by the parallel circuit 101 and the inductor 97. Further, the frequency 107 is a parallel resonance frequency mainly due to a parallel circuit of the interstage tuning capacitor 31b and the inductances 96 and 97. The parallel resonance frequency of the interstage tuning capacitor 38b and the short-circuit inductor 99 by the parallel circuit 100 is higher than UHF because the short-circuit inductor is as small as several nH. This parallel resonance frequency is not shown.

  FIG. 5 shows the selection characteristics of the interstage tuning circuit 31 according to the first embodiment. In addition, about the frequency used in FIG. 5, about the same thing as FIG. 4, the same number is attached | subjected and description is simplified. Also. (A) represents the frequency, (C) represents the attenuation, and 113 represents the selection characteristic of the interstage tuning circuit 31.

  In FIG. 5, the selection characteristic of the interstage tuning circuit 31 is a blocking region at the series resonance frequencies 104 and 106, as is clear from the impedance characteristic of FIG. 4. The parallel resonance frequency 107 is a pass band through which a desired signal passes.

  At this time, the parallel resonance frequency 105 is sufficiently higher than the parallel resonance frequency 107 that is the reception frequency. Further, the attenuation amount of the parallel resonance frequency 105 is sufficiently suppressed by the series resonance frequencies 104 and 106. Therefore, even if an interference signal is present at the parallel resonance frequency 105, the reception performance is not deteriorated.

  On the other hand, in the conventional example, the parallel resonance frequency 89 is in the UHF band in the vicinity of the parallel resonance frequency 91 that is the reception frequency. The reception performance deteriorated due to the interference signal in the UHF band.

  The foregoing has described the deterioration of the selection characteristics due to the inductive coupling between the interstage tuning inductors 31a and 38a. However, the inductive coupling also applies to the interstage tuning inductors 30b and 37b or the antenna tuning inductors 28b and 35b. The influence of the selection characteristics by is the same.

  Accordingly, between the antenna tuning inductors 28b and 35b or between the interstage tuning inductors 30b, 37b, 31a and 38a, only air is used without using a metal case or partition plate for high frequency shielding. Therefore, a small-sized electronic tuner can be realized.

  At this time, a metal partition plate is often used as the partition plate for the high-frequency shield, but a partition plate obtained by performing metal plating on the insulating material may be used.

  In the electronic tuner of the first embodiment, the effect of the damping circuit with respect to the two receiving circuit units has been described. However, the effect of the damping circuit is the same even in the case of having a plurality of receiving circuit units, and the non-operating state What is necessary is just to dampen at least any one of the tuning inductors provided in the receiving circuit unit.

(Embodiment 2)
Hereinafter, Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 6 is a damping circuit diagram according to the second embodiment of the present invention. 6 differs from the damping circuit described in FIG. 3 in that a resistor is added in series. Further, in FIG. 6, the same components as those in FIG.

  In FIG. 5, the selection characteristic 114 of the interstage tuning circuit 31 in the second embodiment is indicated by a dotted line. At this time, the resistors 120 and 121 are resistors having a resistance value of several Ω to 100 Ω, for example, and are connected in series to the damping circuits 34 and 41, respectively. The interstage circuit section 38 of the non-operating receiving circuit section 24 is damped at high frequency by the series connection body of the damping circuit 41 and the resistor 121.

  With the resistor having a resistance value of several Ω to 100Ω, the selection characteristic 114 of the interstage tuning circuit 31 is damped in series at the high frequency of the series resonance frequencies 104 and 106 and the parallel resonance frequency 105. Become. That is, the attenuation amounts at the series resonance frequencies 104 and 106 and the parallel resonance frequency 105 are averaged, and suppression against interference is increased on average.

(Embodiment 3)
Hereinafter, Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 7 is a circuit diagram of the electronic tuner according to the third embodiment of the present invention. 1 has a common mixer 52 and a common oscillator 53 in the mixing circuit unit 26, whereas in FIG. 7, each of the two receiving circuit units has a mixer and an oscillator individually. Is different.

  In FIG. 7, reference numeral 131 denotes an input terminal to which a high frequency input signal is input. The input terminal 131 is connected to the common terminal 132 a of the duplexer 132. The output terminals 132b and 132c of the duplexer 132 are connected to the inputs 133a and 134a of the receiving circuit sections 133 and 134, respectively.

  Here, it is assumed that the reception circuit unit 133 receives a high frequency in the input signal, and the reception circuit unit 134 receives a low frequency in the input signal.

  Outputs 133b and 134b of the receiving circuit units 133 and 134 are connected to input terminals 136a and 136b of the IF amplifier circuit unit 136, respectively. The output of the IF amplifier circuit unit 136 is connected to the output terminal 137.

  The receiving circuit unit 133 is connected to the input 133a and has an antenna tuning circuit 138 in which a tuning capacitor 138a and a tuning inductor 138b are connected in parallel, an amplifier 139 connected to the output of the antenna tuning circuit 138, An interstage tuning circuit 140 which is connected to the output of the amplifier 139 and is composed of a tuning capacitor 140a and a tuning inductor 140b, and an interstage which is composed of a tuning capacitor 141b and a tuning inductor 141a. Tuning circuit 141, mixer 142 whose output from interstage tuning circuit 141 is connected to one input, oscillator 143 connected to the other input of mixer 142, and connected to this oscillator 143 It consists of a parallel circuit of an oscillation tuning capacitor 144a and an oscillation tuning inductor 144b. And oscillation tuning circuit 144, the output of the mixer 142 is from the output terminal connected 133b, the output terminal 133b is connected to the input terminal 136a of the IF amplifier circuit 136.

  The inductor 140b of the interstage tuning circuit 140 and the inductor 141a of the interstage tuning circuit 141 are configured as inductive coupling, and the interstage tuning circuits 140 and 141 form a double tuning circuit.

  Further, a damping circuit 149 is connected in parallel between the antenna tuning circuit 138 and the ground. Damping circuits 150, 151, and 152 are connected between the input and ground of the interstage tuning circuit 140, between the output and ground of the interstage tuning circuit 141, and between the oscillation tuning circuit 144 and ground, respectively.

  Similarly, the receiving circuit unit 134 includes an antenna tuning circuit 153 connected to the input 134a and connected in parallel with the antenna tuning capacitor 153a and the antenna tuning inductor 153b, and an amplifier connected to the output of the antenna tuning circuit 153. 154, an interstage tuning circuit 155 which is connected to the output of the amplifier 154 and includes an interstage tuning capacitor 155a and an interstage tuning inductor 155b, and an interstage tuning capacitor 156b and an interstage tuning inductor. An interstage tuning circuit 156 constituted by 156a, a mixer 157 to which the output of the interstage tuning circuit 156 is connected to one input, an oscillator 158 connected to the other input of the mixer 157, and The oscillation tuning capacitor 159a and the oscillation tuning impedance are connected to the oscillator 158. And oscillation tuning circuit 159 consisting of a parallel circuit of inductor 159b, the output of the mixer 157 is comprised of the connected output terminal 134b, the output terminal 134b is connected to the input terminal 136b of the IF amplifier circuit 136.

  The inductor 155b of the interstage tuning circuit 155 and the inductor 156a of the interstage tuning circuit 156 are configured as inductive coupling, and the interstage tuning circuits 155 and 156 form a double tuning circuit.

  Further, a damping circuit 162 is connected in parallel between the antenna tuning circuit 153 and the ground. Damping circuits 163, 164, and 165 are connected between the input and ground of the interstage tuning circuit 155, between the output and ground of the interstage tuning circuit 156, and between the oscillation tuning circuit 159 and the ground, respectively.

  Further, the outputs from the oscillators 143 and 158 are connected to the input 170 a of the PLL controller 170. A tuning voltage is output from the output 170b of the PLL controller 170. By applying this tuning voltage to the oscillation tuning capacitor 144a or 159a, the oscillator 143 or 158 can be set to a predetermined oscillation frequency. At the same time, the tuning voltage from the output 170b of the PLL controller 170 is supplied to the capacitors 138a, 140a, 141b, 153a, 155a, and 156b.

  The output 170c of the PLL controller 170 is connected to the damping circuits 149, 150, 151, 152, 162, 163, 164, and 165, and each damping circuit is independently controlled to be turned on and off by the output voltage from the output 170c. it can. A PLL control terminal 171 to which PLL control data from the control unit is input is connected to the input 170d of the PLL control unit 170.

  The operation of the electronic tuner configured as described above will be described with reference to FIG. The PLL control data from the control unit is input to the input 170 d of the PLL control unit 170 via the PLL control terminal 171. Based on the PLL control data, power is supplied to either the receiving circuit unit 133 or 134 by the output 170c of the PLL control unit 170. Thereby, for example, when receiving a high frequency, the receiving circuit unit 133 is in an operating state, and when receiving a low frequency, for example, the receiving circuit unit 134 is in an operating state.

  At the same time, the changeover switch 172 of the IF amplification circuit unit 136 is switched by the output 170c from the PLL control unit 170 so that the output from the reception circuit unit in the operating state is selected.

  Further, the oscillation signal of the oscillator 143 or 158 is input to the input 170 a of the PLL control unit 170. The oscillation frequency of this oscillation signal is compared with a reference frequency in the PLL control unit 170. Further, the tuning voltage from the output 170 b of the PLL controller 170 is applied to the tuning capacitor 144 a of the oscillation tuning circuit 144 of the oscillator 143 or applied to the tuning capacitor 159 a of the oscillation tuning circuit 159 of the oscillator 158. In this way, the oscillator 143 or 158 is PLL-controlled, and can have a predetermined oscillation frequency.

  The tuning voltage from the output 170b is also supplied to the tuning capacitors 138a, 140a, 141b, 153a, 155a, and 156b constituting the antenna tuning circuit 138 and the interstage tuning circuits 140, 141, 153, 155, and 156. Is done. Thereby, the tuning frequency of the antenna tuning circuit 138 and the interstage tuning circuits 140, 141, 153, 155, and 156 becomes a predetermined frequency. In this way, either the receiving circuit unit 133 or 134 is selected based on the PLL control data input to the PLL control terminal 171.

  First, the receiving circuit unit 133 will be described. The high frequency input signal input to the input terminal 131 is input to the common terminal 132 a of the duplexer 132. A high-frequency input signal is output from the output 132b of the duplexer 132. This high frequency input signal is supplied to the input 133 a of the receiving circuit unit 133. The high frequency input signal input to the input 133 a is amplified by the amplifier 139 after the desired signal is selected by the antenna tuning circuit 138. The output signal from the amplifier 139 is further selected by the interstage tuning circuits 140 and 141. This desired signal is supplied to one input of the mixer 142. An output signal from the oscillator 143 is supplied to the other input of the mixer 142, whereby an intermediate frequency signal is output from the output of the mixer 142. This intermediate frequency signal is output from the output 133b. The intermediate frequency signal is output from the output 133b and supplied to the input terminal 136a of the IF amplifier circuit unit 136.

  Next, the receiving circuit unit 134 will be described. A low frequency input signal is output from the output 132 c of the duplexer 132. This low frequency input signal is supplied to the input 134 a of the receiving circuit unit 134. The low-frequency input signal input to the input 134 a is amplified by the amplifier 154 after the desired signal is selected by the antenna tuning circuit 153. The output signal from the amplifier 154 is further selected by the interstage tuning circuits 155 and 156. This desired signal is supplied to one input of the mixer 157. An output signal from the oscillator 158 is supplied to the other input of the mixer 157, whereby an intermediate frequency signal is output from the output of the mixer 157. The intermediate frequency signal is output from the output 134b and supplied to the input terminal 136b of the IF amplifier circuit unit 136.

  Further, the IF amplifier circuit unit 136 will be described. The intermediate frequency signal output from the input terminals 136 a and 136 b is connected to the changeover switch 172. In the changeover switch 172, the output of the selected receiving circuit unit is selected.

  The intermediate frequency signal selected by the changeover switch 172 is amplified by the amplifier 166 and then output from the output terminal 137.

  Next, the damping circuits 149, 150, 151, 152, 162, 163, 164, and 165 will be described. These damping circuits 149, 150, 151, 152, 162, 163, 164, and 165 are composed of electronic switches. By connecting both ends of these electronic switches, they are short-circuited in high frequency. Further, the damping circuits 149, 150, 151, 152, 162, 163, 164, 165 are controlled to be short-circuited or opened by a damping control voltage from the output 170 c of the PLL controller 170.

  For example, a case where the receiving circuit unit 133 is in an operating state and the receiving circuit unit 134 is in a non-operating state will be described. In the receiving circuit unit 133, the damping circuits 149, 150, 151, and 152 are opened, and only the desired signal is selected. On the other hand, in the receiving circuit unit 134, the damping circuits 162, 163, 164, and 165 are short-circuited, and the antenna tuning circuit 153, the interstage tuning circuits 155 and 156, and the oscillation tuning circuit 159 are dumped.

  FIG. 8 is a component layout diagram of the electronic tuner according to the third embodiment. 7 shows the case where there are two reception circuit units, but in FIG. 8, there are three reception circuit units. In addition, the parts used in FIG. 8 are the same as those in FIG.

  In FIG. 8, 131 is an input terminal. Reference numeral 180 denotes a metal case in which the reception circuit units 133 and 134, the IF amplification circuit unit 136, and the PLL control unit 170 are housed. Reference numeral 180a denotes a metal partition plate for preventing the antenna tuning circuits 138 and 153 and the interstage tuning circuits 140, 141, 155 and 156 from being coupled at a high frequency. At the same time, 180b is a metal partition plate for preventing the interstage tuning circuits 140, 141, 155, and 156, the oscillators 143 and 158, and the mixers 142 and 157 from being coupled at a high frequency.

  Reference numeral 181 denotes an antenna tuning inductor of the third receiving circuit unit. Reference numeral 182 denotes an interstage tuning inductor located near the input terminal 131 of the third receiving circuit unit. Reference numeral 183 denotes an interstage tuning inductor located near the output terminal 137 of the third receiving circuit unit. Reference numeral 184 denotes an oscillation tuning inductor of the third receiving circuit unit.

  As described above, in the small-sized electronic tuner, the antenna tuning inductors 138b, 153b, and 181 are close to each other, the interstage tuning inductors 140b, 155b, and 182 are close to each other, and the interstage tuning inductors 141a, 156a, and 183 are close to each other. The oscillation tuning inductors 144b, 159b, and 184 are close to each other. As a result, the inductors are inductively coupled to each other, and a high frequency effect is generated.

  FIG. 9A is a circuit diagram of interstage tuning circuits 141 and 156 according to the third embodiment. 9A, the same components as those in FIG. 7 are denoted by the same reference numerals, and the description thereof is simplified.

  FIG. 9A shows interstage tuning inductors 141a and 156a and interstage tuning capacitors 141b and 156b, which are components of the interstage tuning circuits 141 and 156. The interstage tuning inductors 141a and 156a come close to each other. Inductive coupling occurs with each other.

  FIG. 9B is an equivalent circuit diagram of the interstage tuning circuit 141 according to the third embodiment. In FIG. 9B, the coupling inductance due to inductive coupling by the interstage tuning inductors 141a and 156a is 196. As a result of the coupling inductance 196, the interstage tuning inductors 141 a and 156 a have inductance values 197 and 198, respectively, with the inductance value decreased by the coupling inductance. Reference numeral 199 denotes a short-circuit inductance when the electronic switch 164 is short-circuited.

  FIG. 10 is an impedance characteristic diagram of the interstage tuning circuit 141 of the electronic tuner according to the third embodiment. Further, (A) represents frequency, (B) represents impedance, and the impedance characteristic of the interstage tuning circuit 141 is 208.

  In FIG. 10, 204 is a series resonance frequency by the series circuit 201 of the parallel circuit 200 and the inductor 198. Reference numeral 205 denotes a parallel resonance frequency by the parallel circuit 201 of the parallel circuit 200 and the coupled inductor 196. Reference numeral 206 denotes a series resonance frequency by the parallel circuit 201 and the inductor 197. Further, the frequency 207 is a parallel resonance frequency mainly by a parallel circuit of the interstage tuning capacitor 141b and the inductances 196 and 197. The parallel resonance frequency of the interstage tuning capacitor 156b and the short-circuit inductor 199 by the parallel circuit 200 is higher than UHF because the short-circuit inductor is as small as several nH. This parallel resonance frequency is not shown.

  FIG. 11 shows the selection characteristics of the interstage tuning circuit 141 according to the third embodiment. In addition, about the frequency used in FIG. 11, about the same thing as FIG. 10, the same number is attached | subjected and description is simplified. Further, (A) represents frequency, (C) represents attenuation, and 213 represents selection characteristics of the interstage tuning circuit 141.

  In FIG. 11, the selection characteristic of the interstage tuning circuit 141 is a blocking region at the series resonance frequencies 204 and 206, as is clear from the impedance characteristic of FIG. 10. The parallel resonance frequency 207 is a pass band through which a desired signal passes.

  At this time, the parallel resonance frequency 205 is sufficiently higher than the parallel resonance frequency 207 that is the reception frequency, and the attenuation amount of the parallel resonance frequency 205 is sufficiently suppressed by the series resonance frequencies 204 and 206. Therefore, even if an interference signal exists at the parallel resonance frequency 205, the reception performance is not deteriorated.

  On the other hand, in the conventional example, the parallel resonance frequency 89 is close to the parallel resonance frequency 91 that is the reception frequency and exists in the UHF band. The reception performance deteriorated due to the interference signal in the UHF band.

  The foregoing has described the deterioration of the selection characteristics due to inductive coupling between the interstage tuning inductors 141a and 156a. However, the interstage tuning inductors 140b and 155b, the antenna tuning inductors 138b and 153b, or the oscillation The tuning inductors 144b and 159b have the same influence on the selection characteristics due to inductive coupling.

  Therefore, between the antenna tuning inductors 138b and 153b, between the interstage tuning inductors 140b and 155b, or between the interstage tuning inductors 141a and 156a, a metal case or partition plate for mutual high frequency shielding. Therefore, the small-sized electronic tuner can be realized.

  At this time, a metal partition plate is often used as the partition plate for the high-frequency shield, but a partition plate obtained by performing metal plating on the insulating material may be used.

  In the electronic tuner of the third embodiment, the effect of the damping circuit for the two receiving circuit units has been described. However, the effect of the damping circuit is the same even in the case of having a plurality of receiving circuit units, and the non-operating state What is necessary is just to dampen at least any one of the tuning inductors provided in the receiving circuit unit.

(Embodiment 4)
Embodiment 4 of the present invention will be described below with reference to the drawings. FIG. 12 is a damping circuit diagram according to the fourth embodiment of the present invention. 12 differs from the damping circuit described in FIG. 9 in that a resistor is added in series. Further, in FIG. 12, the same components as those in FIG.

  In FIG. 11, the selection characteristic 214 of the interstage tuning circuit 141 in the fourth embodiment is indicated by a dotted line. At this time, the resistors 122 and 123 have a small resistance value of 10Ω, for example, and are connected in series to the damping circuits 151 and 164, respectively. The interstage circuit unit 156 of the non-operating receiving circuit unit 134 is damped at a high frequency by the series connection body of the damping circuit 164 and the resistor 123.

  As a result, the selection characteristic 214 of the interstage tuning circuit 141 is indicated by a dotted line because the series resonance frequencies 204 and 206 and the parallel resonance frequency 205 are damped in high frequency. That is, the attenuation amounts at the series resonance frequencies 204 and 206 and the parallel resonance frequency 205 are averaged. Increased suppression of interference.

  The high-frequency receiver according to the present invention has an effect that a small-sized electronic tuner can be realized, and is particularly useful when used for a mobile phone or a mobile terminal.

Circuit diagram of electronic tuner in Embodiment 1 of the present invention Same as above, parts layout of electronic tuner Same as above, electronic tuner interstage tuning circuit diagram Same as above, impedance diagram of interstage tuning circuit of electronic tuner Same as above, selection characteristics diagram of interstage tuning circuit of electronic tuner Interstage tuning circuit diagram of electronic tuner in Embodiment 2 of the present invention Circuit diagram of electronic tuner in Embodiment 3 of the present invention Same as above, parts layout of electronic tuner Same as above, electronic tuner interstage tuning circuit diagram Same as above, impedance diagram of interstage tuning circuit of electronic tuner Same as above, selection characteristics diagram of interstage tuning circuit of electronic tuner Circuit diagram for interstage tuning of electronic tuner in embodiment 4 of the present invention Circuit diagram of electronic tuner in conventional example Same as above, electronic tuner interstage tuning circuit diagram Same as above, impedance diagram of interstage tuning circuit of electronic tuner Same as above, selection characteristics diagram of interstage tuning circuit of electronic tuner

Explanation of symbols

23 receiving circuit unit 23a input terminal 23b output terminal 24 receiving circuit unit 24a input terminal 24b output terminal 26 mixing circuit unit 27 output terminal 28 antenna tuning circuit 29 amplifier 30 interstage tuning circuit 31 interstage tuning circuit 32 damping circuit 33 damping circuit 34 Damping circuit 35 Antenna tuning circuit 36 Amplifier 37 Interstage tuning circuit 38 Interstage tuning circuit 39 Damping circuit 40 Damping circuit 41 Damping circuit 51 Changeover switch 52 Mixer 53 Oscillator 54 Oscillation tuning circuit

Claims (16)

An input terminal to which a high frequency signal is input, first and second receiving circuit units connected in parallel via a duplexer connected to the input terminal, and outputs of the first and second receiving circuit units A changeover switch having a side connected to each terminal, a first mixing circuit unit in which a signal of a common terminal of the changeover switch is input to one side and an output of the first oscillator is input to the other, and the first In the electronic tuner comprising the IF output terminal to which the output of the mixing circuit section is supplied, the first and second receiving circuit sections each have at least a tuning inductor and a tuning capacitor, respectively. And at least one of the tuning inductors is provided with a damping circuit connected in parallel, and the receiving circuit is configured so that one of the first and second receiving circuit units is inactive. Electronic tuner in which the tuning inductor is damping by the damping circuit parts. The electronic tuner according to claim 1, wherein the damping circuit includes a series connection body of a switch circuit and a resistor. The electronic tuner according to claim 1, wherein the damping circuit is disposed in proximity to the tuning capacitor. 2. The electronic tuner according to claim 1, wherein only air is interposed between the tuning inductors forming the first and second tuning circuits. The distance between the tuning inductors forming the first and second tuning circuits is based on the distance between the tuning inductor and a metal case or partition plate in which the first and second receiving circuit units are housed. The electronic tuner according to claim 4, wherein the electronic tuner is reduced. 2. The integrated circuit according to claim 1, wherein at least a changeover switch, a damping circuit provided in the vicinity of the changeover switch, and a first mixing circuit unit are integrated in the same package. The electronic tuner according to claim 1, wherein a PLL control unit is loop-connected to the first oscillator, a control data input terminal for supplying control data to the PLL control unit is provided, and a damping circuit is controlled by the control data. A high-frequency signal receiver having a control unit for sending control data to a control data input terminal of the electronic tuner according to claim 7. An input terminal to which a high-frequency signal is input, third and fourth receiving circuit units connected in parallel via a duplexer connected to the input terminal, and outputs of the third and fourth receiving circuit units In an electronic tuner comprising a changeover switch whose side is connected to each terminal and an IF output terminal to which a signal of a common terminal of the changeover switch is supplied, the third and fourth receiving circuit units are at least for tuning Second and third mixers formed by third and fourth tuning circuits, respectively, having an inductor and a tuning capacitor, and the outputs of the third and fourth tuning circuits are input to one side, respectively. Second and third oscillators respectively input to the other of the second and third mixers, and fifth and sixth oscillators comprising tuning inductors and tuning capacitors respectively connected to the second and third oscillators Tuning circuit and And at least one of the tuning inductors forming the third and fourth receiving circuit sections and the fifth and sixth tuning circuits are provided with a damping circuit connected in parallel, 3. An electronic tuner in which the tuning inductor provided in the receiving circuit unit and the tuning circuit which are not operated among the third and fourth receiving circuit units and the fifth and sixth tuning circuits is damped by the damping circuit. The electronic tuner according to claim 9, wherein the damping circuit includes a series connection body of a switch circuit and a resistor. The electronic tuner according to claim 9, wherein the damping circuit is disposed in proximity to the tuning capacitor. 10. Only air is interposed between the tuning inductors forming the third and fourth tuning circuits, or between the tuning inductors forming the fifth and sixth tuning circuits. Electronic tuner. At least the distance between the tuning inductors that form the third and fourth tuning circuits, or the distance between the tuning inductors that form the fifth and sixth tuning circuits, is determined by these tuning inductors, The electronic tuner according to claim 12, wherein the electronic tuner is smaller than a distance from a metal case or a partition plate in which the fourth receiving circuit unit and the fifth and sixth tuning circuits are housed. 10. The electronic tuner according to claim 9, wherein at least the second and third mixers and the respective damping circuits provided in the vicinity of the second and third mixers are integrated in the same package. circuit. The PLL control unit is connected in a loop to the second and third oscillators, a control data input terminal for supplying control data to the PLL control unit is provided, and a damping circuit is controlled by the control data. Electronic tuner. The high frequency signal receiver which has a control part which sends out control data toward the control data input terminal of the electronic tuner of Claim 15.

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