JP2005302871A - Multilayer semiconductor device and manufacturing method thereof. - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a stacked semiconductor device capable of improving a non-defective product rate after being stacked, and a manufacturing method thereof, while reducing the mounting area per function or memory capacity.
SOLUTION: A first bonding pad 13 provided along an end of a first main surface and a second bonding surface provided opposite to the first main surface and electrically connected to the first bonding pad 13 are provided. A first substrate 11 having a connected external connection terminal 17, a second bonding pad 22 provided along the end of the main surface, and a second substrate 21 fixed on the first substrate 11. And a semiconductor device 6 having a semiconductor chip 23 mounted face down so as to expose the second bonding pad 22 on the second substrate 21 and electrically connected to the second bonding pad 22; A bonding wire 31 for electrically connecting the first bonding pad 13 and the second bonding pad 22 is provided.
[Selection] Figure 1

Description

The present invention relates to a stacked semiconductor device in which one or more semiconductor devices are stacked to improve the mounting density as a three-dimensional structure, and a method for manufacturing the same.

In recent years, with the advancement of functions, miniaturization, and portability of electronic devices, high-density mounting of semiconductor devices on a mounting substrate is required. To meet such market demands, high integration,
A so-called stack MCP (multi-chip) in which a plurality of semiconductor chips composed of a memory LSI, a logic LSI, or an LSI in which these functions are increased and a large memory capacity are stacked on a package substrate A semiconductor device (hereinafter referred to as a stacked semiconductor device) in which a chip-package type package structure is employed has been proposed (for example,
See Patent Document 1. ).

For example, in Patent Document 1, as shown in the schematic cross-sectional view of FIG. 8, on the substrate 111 of the package, the semiconductor chip 123 that is relatively large on the side close to the substrate 111 (lower side), A relatively small semiconductor chip 124 is bonded to the upper side with an adhesive 127, and a bonding pad 122 exposed on the upper side of each semiconductor chip 123 and 124 and a bonding pad 113 on the substrate 111 are formed. They are connected by bonding wires 131. The bonding pad 113 is connected to the land 112 on the opposite side via a substrate wiring 118 and a side conductor 115 disposed in an opening 114 penetrating the substrate 111.
The land 112 is further connected to a solder ball 117. Substrate 111
The semiconductor chips 123 and 124 are covered with a mold resin 136.

By adopting such a stacked semiconductor device 101 structure, a single semiconductor chip 123 is obtained.
, 124 can be reduced compared with a semiconductor device (not shown) mounted with a function or memory capacity. In addition, since the semiconductor chips 123 and 124 are stacked in a chip state, the burn-in test is not executed, and the burn-in test is performed at the stage of becoming a stacked semiconductor device, and the quality is determined.

However, in such a stacked semiconductor device, the mounted semiconductor chip normally finishes the die sort, but since the burn-in test is not completed, the semiconductor chip that causes the burn-in test failure is included in the stacked semiconductor device. It may be installed. In fact, when a burn-in test of a stacked semiconductor device is performed, the non-defective product rate of the stacked semiconductor device is a result of multiplying the non-defective product rate of each stacked semiconductor chip, and there is a problem in that the non-defective product rate of the stacked semiconductor device, that is, the yield greatly decreases. Occur.
JP 2000-150699 A (page 4, FIG. 1)

The present invention provides a stacked semiconductor device capable of improving the yield rate after being stacked while reducing the mounting area per function or memory capacity, and a method for manufacturing the same.

In order to achieve the above object, a stacked semiconductor device of one embodiment of the present invention includes a first bonding pad provided along an end portion of a first main surface, and a second facing the first main surface. A first substrate having an external connection terminal provided on a main surface and electrically connected to the first bonding pad; a second bonding pad provided along an end of the main surface; and the first substrate A second substrate fixed on the substrate, and placed face down so as to expose the second bonding pad on the second substrate and electrically connected to the second bonding pad. A semiconductor device having a semiconductor chip, and connection means for electrically connecting the first bonding pad and the second bonding pad are provided.

According to another aspect of the present invention, there is provided a method for manufacturing a stacked semiconductor device, wherein the second bonding pad is provided on the main surface of a second substrate provided with a second bonding pad along an end of the main surface. A semiconductor chip is mounted face-down so as to expose the semiconductor chip, and the semiconductor chip and the second bonding pad are electrically connected to produce a semiconductor device; and the second bonding of the semiconductor device Performing a burn-in test using a pad and selecting a non-defective product of the semiconductor device; a first bonding pad provided along an end of the first main surface;
And the first main surface of the first substrate having an external connection terminal provided on the second main surface opposite to the first main surface and electrically connected to the first bonding pad. Placing the second substrate of the semiconductor device such that the first bonding pad of the first substrate is exposed, and forming the second bonding pad of the semiconductor device and the first substrate. And a step of electrically connecting the first bonding pad.

According to the present invention, it is possible to provide a stacked semiconductor device capable of improving the yield rate after being stacked and the manufacturing method thereof, while reducing the mounting area per function or memory capacity.

Embodiments of the present invention will be described below with reference to the drawings. In the figure shown below, the same code | symbol is attached | subjected to the same component.

A stacked semiconductor device and a manufacturing method thereof according to Example 1 of the present invention will be described with reference to FIGS. FIG. 1 schematically shows the structure of a stacked semiconductor device. FIG. 1A is a plan view thereof, FIG. 1B is a cross-sectional view taken along line AA of FIG. 3 is a plan view schematically showing the structure of the first substrate of the stacked semiconductor device, FIG. 3 is a schematic view showing the structure of the semiconductor device that is a component of the stacked semiconductor device, and FIG. 3B is a cross-sectional view taken along the line BB in FIG. 3A, and FIG. 4 is a plan view schematically showing the structure of the second substrate of the semiconductor device.
FIG. 5 is a flowchart showing a process for manufacturing a laminated semiconductor device.

First, as shown in FIG. 1, in the stacked semiconductor device 1 of the present embodiment, a plurality of semiconductor devices 6 a, 6 b, 6 c, and 6 d are provided on one end of the first main surface (upper surface) of the first substrate 11. The portions are shifted in the left direction on the drawing and fixed in a staircase pattern. Also, each semiconductor device 6a, 6
b, 6c, 6d bonding pads (second or third bonding pads) 22a
, 22b, 22c, and 22d are electrically connected to bonding pads (first bonding pads) 13a, 13b, 13c, and 13d provided on the upper surface of the first substrate 11, respectively. The bonding pads 13a, 13b, 13c, and 13d are connected to the first substrate 11
The substrate wiring 18 on the upper surface is electrically connected to the lands 12 and the solder balls 17 serving as external connection terminals on the second main surface (lower surface). The semiconductor device 6, the bonding wire (connection means) 31, etc. are covered with a mold resin 36.

As shown in FIG. 2, the first substrate 11 is formed of, for example, a single layer substrate made of glass epoxy material, and is arranged in parallel with the right side at the end (peripheral part) on the right side of the upper surface. A plurality of rows of bonding pads 13 and substrate wirings 18 connected to the bonding pads 13 and extending in the left direction of the drawing are arranged. In this specification, “column” refers to a direction parallel to a side. Each row of the bonding pads 13a, 13b, 13c, and 13d is provided in parallel with the right side. The rows of bonding pads 13a, 13b, 13c, 13d are
As many as the number of semiconductor devices 6 to be stacked, here four semiconductor devices 6a, 6b, 6c, 6d
Are stacked in four rows, and the number of bonding pads in each row corresponds to the number of semiconductor devices 6a, 6
The same number of bonding pads 22 as b, 6c, and 6d are provided. The bonding pad 13 is secured with, for example, Ni / Au or SnAg plating on the underlying Cu.

On the other hand, a land 12 is provided on the lower surface of the first substrate 11, and this land 12 is electrically connected to the substrate wiring 18 through a side conductor 15 formed on the side surface of the opening 14 of the first substrate 11. ing. Solder balls 17 are fixed to the lands 12.

In the semiconductor device 6, as shown in FIG. 3A, the semiconductor chip 23 is placed face down on the second substrate 21, the space between the second substrate 21 and the semiconductor chip 23, and the semiconductor chip. The peripheral portion of 23 is filled with underfill 27 made of a resin having a high viscosity and hermetically sealed. As shown in FIG. 3B, the semiconductor chip 23 has a plurality of bump electrodes 24 formed on the main surface.

As shown in FIG. 4, the second substrate 21 is formed of polyimide, glass epoxy material, or the like, and bonding pads 22, bump connection pads 29, and substrate wirings 28 are formed on the upper surface thereof. The bonding pads 22 are arranged in a row parallel to the right side at one end peripheral portion of the second substrate 21, for example, the right peripheral portion of the drawing, with an arrangement interval corresponding to the interval between the bonding pads 13 of the first substrate 11. ing.

The bump connection pads 29 are arranged corresponding to the bump electrodes 24 of the semiconductor chip 23, and each bump connection pad 29 is connected to each bonding pad 22 through a substrate wiring 28. The bonding pad 22 and the bump connection pad 29 are, for example, the underlying Cu
Ni / Au or SnAg plating is applied on the surface to ensure bonding.

Further, as shown in FIG. 3, the semiconductor chip 23 is placed face down on the second substrate 21 so as to expose the bonding pads 22 of the second substrate 21.
SnAg plated on the bump electrode 24 and the bump connection pad 29 surface of the second substrate 21
It is fixed by thermocompression bonding (not shown).

As shown in FIG. 1, the lowermost semiconductor device (first semiconductor device) 6a is fixed to a predetermined position on the first substrate 11 with an adhesive with the second substrate 21a facing down. The bonding pad 22a is connected to the bonding pad 13a in the leftmost column of the first substrate 11. The second semiconductor device (second semiconductor device) 6b from the bottom has the second substrate 21b on the lowermost semiconductor device 6a, and one end of the second substrate 21b and the lower semiconductor. One end of the chip 23a is aligned and laminated and fixed via an adhesive, and the bonding pad 22b is the bonding pad 1 in the second row from the left side of the first substrate 11.
It is connected to 3b. Similarly, the third (fourth) and fourth (fourth) semiconductor devices 6 from the bottom
c, 6d are laminated and fixed, and bonding pads 22c of the semiconductor devices 6c, 6d,
22d is a bonding pad 13c, 1 in the third row and the rightmost row of the first substrate 11.
Each is connected to 3d.

Next, a manufacturing method of the laminated semiconductor device having the above structure will be described with reference to FIG. FIG. 5 shows steps from wafer die sort to burn-in test of the laminated semiconductor device. First, a plurality of semiconductor chips 23 that have been subjected to the wafer process are placed on a die sorter in a wafer state, and pass / fail judgment is performed mainly on DC characteristics, etc., and marking is performed on defective semiconductor chips (step S11).
. Next, the back surface of the wafer after the pass / fail judgment is ground to a certain thickness (step S12). Thereafter, the wafer is diced to separate (separate) the semiconductor chips 23 (step S13). Next, for example, a wire bonder is used for the electrode pads of the non-defective semiconductor chip 23 to
U stud bumps are formed to form bump electrodes 24 (step S14).

Thereafter, the semiconductor chip 23 is placed face down on a predetermined position of the second substrate 21, and the bump electrodes 24 of the semiconductor chip 23 and the bump connection pads 2 of the second substrate 21 are placed.
9 is subjected to bump bonding by thermocompression bonding, and the semiconductor chip 23 and the second substrate 21 are further bonded.
Underfill 27 is filled in the space between (step S15). At this stage, the semiconductor device 6 with the bonding pad 22 exposed at the peripheral portion of one end portion of the second substrate 21 as shown in FIG. 3 is completed.

One end portion of the semiconductor device 6 is inserted into, for example, a socket (not shown) of a burn-in test device (not shown), and the electrical connection between the bonding pad 22 and the socket terminal is ensured. To select non-defective products (step S16). The sorted first non-defective semiconductor device 6 and its second substrate 21 are arranged on the first substrate 11 side (lower side).
The first substrate 11 is placed at a predetermined position via an adhesive, and the second semiconductor device 6 is placed on the first semiconductor device 6 and the second substrate 21 is placed on the lower side. In the same manner, a predetermined number, for example, four non-defective semiconductor devices 6 are stacked (step S17).

Here, each semiconductor device 6 is mounted in a staggered manner parallel to the first substrate 11 so that the bonding pads 22 can be wire-bonded. A plurality of first substrates 11 are arranged in a sheet form.

The bonding pads 22 of the stacked semiconductor devices 6 and the bonding pads 13 of the first substrate 11 are connected by bonding wires 31 (step S18). The semiconductor device 6, the bonding wire 31 and the like on the first substrate 11 are covered with the mold resin 36 and sealed (step S19). The sheet-like assembly at this stage may be of a type in which the partition of the mold resin 36 is inserted at a position where the individual laminated semiconductors 1 are to be separated, or a type in which the partition of the mold resin 36 is not inserted.

Solder balls 17 are provided on the lands 12 on the first substrate 11 (step S20). Thereafter, the solder balls 17 are fixed to the lands 12 on the first substrate 11 by reflow (step S21).

The laminated semiconductor device 1 arranged in a plurality of sheets is cut or diced,
It is separated into individual stacked semiconductor devices 1 (step S22). A burn-in test is performed as a product of the stacked semiconductor device 1 to finally select a non-defective stacked semiconductor device 1 (step S23).

Note that the stacked semiconductor devices 6 may be the same type or a different type of LSI, such as a memory LSI, a logic LSI, or an LSI in which these are mixed.

According to the stacked semiconductor device of the embodiment described above, each semiconductor device 6 is placed face down on the second substrate 21 as shown in FIG. 3, and a peripheral portion of one end portion of the second substrate 21. The bonding pad 22 is exposed. Therefore, one end of the semiconductor device 6 is inserted into, for example, a socket of a burn-in test device, and a burn-in test is performed in a state where electrical connection between the bonding pad 22 and the socket terminal is ensured to select a good product. And the yield of the stacked semiconductor device can be improved. For example, assuming that the burn-in non-defective rate of each semiconductor chip is 90%, the final non-defective rate of a laminated semiconductor device having four layers is calculated as 0.9 × 0.9 × 0.9 × 0.9. = 0.66, that is, 66%. On the other hand, in this embodiment, since semiconductor chips having a burn-in non-defective product rate close to 100% are stacked, the non-defective product rate of the laminated semiconductor device is almost 100%.

Further, since the yield rate is improved, it is possible to eliminate waste of materials used or process time. For example, in the conventional stacked semiconductor device, about 1/3 is a defective product, whereas in this embodiment, about 1/10 of the defective product is required, which is about 24% of the conventional material or manufacturing time. It is possible to eliminate waste.

Further, in the conventional stacked semiconductor device, it is essential that the upper semiconductor chip is smaller than the semiconductor chip disposed in the lower layer, but in this embodiment, a semiconductor chip larger than the semiconductor chip of the semiconductor device stacked in the lower layer is used. It is possible to arrange in the upper layer.

Further, since the second substrate is disposed, the wiring between the electrode position of the semiconductor chip and the bonding pad can be easily changed. That is, even if the conventional bonding wires cross and cannot be electrically connected, or even when the connection to the preferred position of the bonding pad of the second substrate is impossible, the substrate wiring is changed. Thus, electrical connection can be established at a desired position.

A stacked semiconductor device according to Example 2 of the present invention will be described with reference to FIGS. FIG. 6 is a plan view schematically showing the structure of the stacked semiconductor device, and FIG. 7 is a perspective view schematically showing the structure of the semiconductor device that is a component of the stacked semiconductor device. The difference from the semiconductor device of the first embodiment is that the bonding pad of the second substrate of the semiconductor device is connected to the second continuous substrate of the second substrate.
They are arranged in parallel to the sides and at the peripheral edges. Then, the bonding pads of the first substrate that are wire-connected to the second substrate are arranged in parallel with the peripheral edges of the two continuous sides of the first substrate, corresponding to the bonding pads of the semiconductor device. is there. In addition, the same code | symbol is attached | subjected to the same component as the said Example 1. FIG.

First, as shown in FIG. 6, in the stacked semiconductor device 2 of the present embodiment, a plurality of semiconductor devices 7 a, 7 b, 7 c, and 7 d are continuously formed on the first main surface (upper surface) of the first substrate 41. The two end portions are shifted in the left and upper directions in the drawing and fixed in a stepped manner. Also,
Bonding pads 22a, 22b, 22c, 2 of each semiconductor device 7a, 7b, 7c, 7d
2d are bonding pads 13a, 13b, 13c provided on the upper surface of the first substrate 41;
13d is electrically connected to each other. Each of these bonding pads 13a, 13b,
Similarly to the first embodiment, 13c and 13d are electrically connected to lands (not shown) serving as external connection terminals on the second main surface (lower surface) by the substrate wiring 18 on the upper surface of the first substrate 41, respectively.

The first substrate 41 is formed of, for example, a single layer substrate made of glass epoxy material, and bonding pads 13 arranged in a lattice shape (matrix shape) on the right side and lower side of the upper surface thereof, and
A substrate wiring 18 connected to the bonding pad 13 and extending in the left or upper direction of the drawing is disposed. However, the bonding pad 13 at the intersection of the right side and the lower side in the drawing, that is, the bonding pad 13 at the lower right corner of the drawing is used by thinning out a part indicated by a broken line because the density of the substrate wiring 18 is increased. On the contrary, a part of the bonding pad 22 of the second substrate 51 of the semiconductor device 7 indicated by a broken line is thinned out. This bonding pad 13
Each column of a, 13b, 13c, and 13d is provided in parallel with the right side or the lower side. The number of bonding pads 13a, 13b, 13c, and 13d on each side is provided corresponding to the number of stacked semiconductor devices 7a, 7b, 7c, and 7d. Here, four semiconductor devices 7a,
In order to stack 7b, 7c, and 7d, four rows are provided on the right side and four rows on the lower side. The number of bonding pads in each column is at least the number of bonding of each semiconductor device 7a, 7b, 7c, 7d.

As shown in FIG. 7, in the semiconductor device 7, the semiconductor chip 53 is placed face down on the second substrate 51, the space between the second substrate 51 and the semiconductor chip 53, and the semiconductor chip 5.
3 is filled with an underfill 27 having a large viscosity and hermetically sealed.

The second substrate 51 is made of polyimide, glass epoxy material, or the like, and bonding pads 22, bump connection pads (not shown), and substrate wirings 28 are formed on the upper surface thereof. The bonding pads 22 are arranged on the periphery of two consecutive ends of the second substrate 51, for example, on the right side and the lower periphery of the drawing, with an arrangement interval corresponding to the interval between the bonding pads 13 of the first substrate 51. , Arranged in a line parallel to the right or bottom side.

Further, as shown in FIG. 7, the semiconductor chip 53 is placed face down on the second substrate 51 so as to expose the bonding pad 22 on the right side and the bonding pad 22 on the lower side of the second substrate 51. The bump electrodes (not shown) of the semiconductor chip 53 and the second substrate 51
It is fixed by thermocompression bonding SnAg (not shown) plated on the surface of the bump connection pad (not shown).

Then, as shown in FIG. 6, the lowermost semiconductor device (first semiconductor device) 7a has an adhesive at a predetermined position on the first substrate 41 with the second substrate 51a facing the first substrate 41. The bonding pad 22a at the right peripheral edge of the first substrate 41 is connected to the bonding pad 13a in the leftmost column of the right peripheral edge of the first substrate 41, and the bonding pad 22a at the lower peripheral edge is the first bonding pad 22a. Are connected to the bonding pads 13a in the uppermost row of the lower peripheral edge of the substrate 41.

The second semiconductor device (second semiconductor device) 7b from the first substrate 41 side has the second substrate 51b on the first substrate 41 side on the lowermost semiconductor device 7a, and the second substrate. The right and lower one ends of 51b and the same end of the lower semiconductor chip 53 are aligned and fixed via an adhesive, and the bonding pads 22b are bonded in the second row from the left or upper side. It is connected to the pad 13b. Similarly, the third (third) and uppermost (fourth) semiconductor devices 7c and 7d from the first substrate 41 side are stacked and fixed, and these semiconductor devices 7
The bonding pads 22c and 22d of c and 7d are connected to the bonding pads 13c and 13d of the third row and the outermost row from the left or upper side, respectively.

Next, the manufacturing process of the laminated semiconductor device 2 includes the left side of the drawing and the left side of the drawing so that the bonding pads 22 of the first substrate 41 and the second substrate 51 of the semiconductor device 7 can be wire-bonded in step S17 of FIG. The first embodiment is different from the first embodiment in that the first substrate 41 and the first substrate 41 are shifted in a stepped manner in the upward direction. In other processes, bonding pads 13 and 22 are used.
However, it is the same as the process of the first embodiment except that it is necessary to change in consideration that the first and second substrates 41 and 51 are arranged at the peripheral edge portions of the two continuous ends.

According to the laminated semiconductor device of the embodiment described above, each semiconductor device 7 is placed face down on the second substrate 51 as shown in FIG. The bonding pad 22 is exposed at the peripheral portion of the end portion. For this reason, these end portions of the semiconductor device 7 are inserted into, for example, a socket (not shown) of a burn-in test device (not shown), and electrical connection between the bonding pad 22 and the socket terminal is ensured.
A burn-in test can be performed to select non-defective products, and the non-defective product rate of the stacked semiconductor device can be maintained high.

Further, the bonding pads 13 and 22 are continuous on the first and second substrates 41 and 51 2.
By arranging in parallel to the peripheral part of the edge part of the side, more bonding pads 13, 2
2 can be formed, and as a result, it can be applied to a stacked semiconductor device that requires more external connection terminals.

As mentioned above, this invention is not limited to the said Example, In the range which does not deviate from the summary of this invention, it can change and implement variously.

For example, in the above-described embodiment, an example in which a plurality of semiconductor devices are stacked on the first substrate has been described. However, one semiconductor device may be stacked.

In the above embodiment, the bonding pad of the first substrate of the stacked semiconductor device is connected to the bonding pad of the second substrate of the semiconductor device so as to be connected. There is no need to stick to this example. For example, a plurality of bonding pads on the second substrate may be connected to one bonding pad on the first substrate. Also,
In both substrates, there may be bonding pads that are not used for connection.

In step S13, the semiconductor chips are separated into individual pieces, and in step S14, the stud bumps are formed on the separated semiconductor chips. However, the order of the steps is changed, and the stud bumps are formed on the semiconductor chips on the wafer. After forming, semiconductor chips may be separated.

In addition, the connection of the semiconductor chip to the second substrate has been described using an example of Au stud bumps, but other types of bumps, for example, Au bumps formed by plating, SnPb solder bumps, Pd-free Sn, are used. It is possible to connect using a system solder bump or the like. Also,
It is also possible to employ a connection method in which solder, conductive paste, anisotropic conductive resin, or the like is interposed between the bumps.

BRIEF DESCRIPTION OF THE DRAWINGS The top view and sectional drawing which show typically the structure of the laminated semiconductor device which concerns on Example 1 of this invention. 1 is a plan view schematically showing a structure of a first substrate of a stacked semiconductor device according to Example 1 of the invention. 1 is a perspective view and a cross-sectional view schematically showing the structure of a semiconductor device according to Embodiment 1 of the present invention. 1 is a plan view schematically showing the structure of a second substrate of a semiconductor device according to Example 1 of the present invention. 5 is a flowchart showing a process for manufacturing the stacked semiconductor device according to the first embodiment of the invention. The top view which shows typically the structure of the laminated semiconductor device which concerns on Example 2 of this invention. The perspective view which shows typically the structure of the semiconductor device which concerns on Example 2 of this invention. Sectional drawing which shows the structure of the conventional laminated semiconductor device typically.

Explanation of symbols

1, 2, 101 Multilayer semiconductor device 6, 6a, 6b, 6c, 6d, 7, 7a, 7b, 7c, 7d Semiconductor device 11, 41 First substrate 12, 112 Land 13, 13a, 13b, 13c, 13d, 22, 22a, 22b, 22c, 22d, 11
3, 122 Bonding pad 14, 114 Opening 15, 115 Side conductor 16, 116 Solder resist 17, 117 Solder ball 18, 28, 118 Substrate wiring 21, 21a, 21b, 21c, 21d, 51, 51a, 51b, 51c, 51d Second
Substrate 23, 23a, 23b, 23c, 23d, 53, 123, 124 Semiconductor chip 24 Bump electrode 27 Underfill 29 Bump connection pad 31, 131 Bonding wire 36, 136 Mold resin 127 Adhesive 111 Substrate

Claims (5)

A first bonding pad provided along an end portion of the first main surface, and an external provided on the second main surface opposite to the first main surface and electrically connected to the first bonding pad A first substrate having connection terminals;
A second bonding pad is provided along an end of the main surface, and the second substrate is fixed on the first substrate, and the second bonding pad is exposed on the second substrate. A semiconductor device having a semiconductor chip mounted face down and electrically connected to the second bonding pad,
Connection means for electrically connecting the first bonding pad and the second bonding pad;
A laminated semiconductor device comprising: Further, a plurality of the first bonding pad rows are provided on the first substrate, and a third chip is formed on the semiconductor chip of the first semiconductor device along the end of the main surface. A bonding pad is provided, and is mounted face down so that the third substrate fixed on the semiconductor chip of the first semiconductor device and the third bonding pad are exposed on the third substrate. A second semiconductor device having a semiconductor chip placed thereon, wherein the connection means includes one first bonding pad row of a plurality of rows and the second bonding pad of the first semiconductor device. 2. The electrical connection is provided, and the other first bonding row of the plurality of rows and the third bonding pad of the second semiconductor device are electrically connected. Placing the stacked semiconductor device. The stacked semiconductor device according to claim 1, wherein the bonding pad is provided along an adjacent end portion of the substrate. The number of bonding pads of the first bonding pad row of the first substrate has at least the number of bonding pads of the semiconductor device, and the first number of the first substrate.
The stacked semiconductor device according to claim 3, wherein the number of bonding pad rows includes at least the number of the semiconductor devices. The main surface of the second substrate provided with a second bonding pad along the end of the main surface,
Mounting a semiconductor chip face down so as to expose the second bonding pad, and electrically connecting the semiconductor chip and the second bonding pad to produce a semiconductor device;
Performing a burn-in test using the second bonding pads of the semiconductor device and selecting non-defective products of the semiconductor device;
A first bonding pad provided along an end portion of the first main surface, and an external provided on the second main surface opposite to the first main surface and electrically connected to the first bonding pad The second substrate of the selected semiconductor device is placed on the first main surface of the first substrate having a connection terminal so that the first bonding pad of the first substrate is exposed. Process,
Electrically connecting a second bonding pad of the semiconductor device and a first bonding pad of the first substrate;
A method for manufacturing a laminated semiconductor device, comprising:

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