JP2005236210A - Standard cell layout, standard cell library, semiconductor integrated circuit, and design method thereof - Google Patents

Abstract

Provided are a standard cell layout, a standard cell library, a semiconductor integrated circuit using the standard cell layout, and a design method thereof that can suppress leakage current without changing existing process steps.
In a standard cell layout which is included in a standard cell library and used to design a semiconductor integrated circuit and has one or a plurality of MOS transistors as a logic cell, a gate poly which constitutes a gate electrode of the MOS transistor. 11 and a region for arranging an extended poly between the adjacent contacts 12.
[Selection] Figure 2

Description

  The present invention relates to a standard cell layout, a standard cell library, a semiconductor integrated circuit, and a design method thereof.

  A standard cell layout having one or a plurality of MOS transistors as a logic cell is usually included in a standard cell library and used to design a semiconductor integrated circuit. Here, most of the standard cell layouts included in the standard cell library are created with priority given to the minimum rule defined by the design rule.

  In recent years, semiconductor integrated circuits tend to move to finer processes due to higher speed and higher integration. In semiconductor integrated circuit devices using standard cells, however, gate miniaturization is achieved by this miniaturization process. Leakage current due to increases. In particular, when the gate length is 100 nm or less, the influence tends to become obvious, and the power consumption of the entire chip, and hence the voltage drop due to the increase of the power consumption occurs, which causes the operation speed to decrease.

  In order to improve speed and power consumption, there is a method of selectively combining a plurality of different libraries to form an integrated circuit device according to performance. For example, a library using a device with a high gate leak conscious of high performance or a device using a device conscious of low leak is prepared, and the optimal library is selected in the process of logic synthesis and place and route, and the cell There is a control method using Multi Vth that is improved by replacing the level (for example, see Non-Patent Document 1). A plurality of different sets of implantation masks are provided for different libraries, and device performance such as Vt is controlled separately.

“90 nm technology”, [online], TSMC, [searched on August 29, 2003], Internet <URL: http: // www. tsmc. com / download / enliterature / 90_bro_2003. pdf>

  However, different cell libraries with different Vt have to create additional masks such as implantation, and the wafer fabrication process work also increases the additional implantation work, so when using a single library at its cycle time and cost There was a problem that was disadvantageous.

  The present invention has been made in view of the above problems in the prior art, and uses a standard cell layout, a standard cell library, and a standard cell layout that can suppress leakage current without changing existing process steps. An object of the present invention is to provide a semiconductor integrated circuit and a design method thereof.

  The present invention provided to solve the above-mentioned problems is used in designing a semiconductor integrated circuit included in a standard cell library, and in the standard cell layout having one or a plurality of MOS transistors as logic cells, A standard cell layout comprising a region for arranging an extended poly between a gate poly constituting a gate electrode of a MOS transistor and an adjacent contact (claim 1).

  Here, the width of the gate poly is a minimum width defined by a design rule, and it is preferable that an interval between the gate poly and an adjacent contact is larger than the minimum distance defined by the design rule and an extended poly arrangement region is provided. (Claim 2).

  Preferably, the extended poly arrangement region is provided on the source region side of the MOS transistor with respect to the gate poly.

  The present invention provided to solve the above-mentioned problems is used in designing a semiconductor integrated circuit included in a standard cell library, and in the standard cell layout having one or a plurality of MOS transistors as logic cells, A standard cell layout comprising a region for disposing an extended poly on a side opposite to an adjacent contact with respect to a gate poly constituting a gate electrode of a MOS transistor (claim 4).

  Here, the width of the gate poly is the minimum width specified by the design rule, and the distance between the source / drain extension with respect to the gate poly and / or the distance from the adjacent gate poly is set to be larger than the minimum distance specified by the design rule. It is suitable to provide the arrangement | positioning area | region (Claim 5).

  Further, in the invention according to any one of claims 1 to 5, when the MOS transistor is divided into a plurality at the same node, it is preferable that each gate electrode has a different gate length depending on the extension poly. 6).

  Furthermore, in the invention according to any one of claims 1 to 5, the MOS transistor is divided into a plurality at the same node, and one of the PMOS transistor and the NMOS transistor has a gate electrode whose gate electrode is different depending on the extended poly. It is preferable to have a length (Claim 7).

  The present invention provided to solve the above-described problems is a standard cell library having the standard cell layout according to any one of claims 1 to 7 (claim 8).

  The present invention provided to solve the problems is a semiconductor integrated circuit designed using the standard cell layout according to any one of claims 1 to 7 (claim 9). .

  The present invention provided to solve the above problems is designed using the standard cell layout according to any one of claims 1 to 5, wherein an extension poly is arranged in the standard cell layout and a gate length is extended. A semiconductor integrated circuit (claim 10).

  The present invention provided to solve the above-mentioned problems has a standard cell layout A having a standard gate length in which no extension poly is arranged, using the standard cell layout according to any one of claims 1 to 5. 1 standard cell library and a second standard cell library having a standard cell layout B in which an extended poly is arranged in the layout of the standard cell layout A and the gate length is extended, and the standard cell layout A is used. Then, after forming the semiconductor integrated circuit, the standard cell layout A is changed to the standard cell layout B (claim 11).

  The present invention provided to solve the above-mentioned problems is a semiconductor integrated circuit design method for designing a semiconductor integrated circuit using the standard cell layout according to any one of claims 1 to 7. (Claim 12).

  In order to solve the above problems, the present invention provides a semiconductor integrated circuit designed using the standard cell layout according to any one of claims 1 to 5, and then an extended poly is arranged in the standard cell layout. A method of designing a semiconductor integrated circuit, wherein the gate length is extended.

  The present invention provided to solve the above-mentioned problems has a standard cell layout A having a standard gate length in which no extension poly is arranged, using the standard cell layout according to any one of claims 1 to 5. 1 standard cell library and a second standard cell library having a standard cell layout B in which an extended poly is arranged in the layout of the standard cell layout A and the gate length is extended, and the standard cell layout A is used. Then, after the semiconductor integrated circuit is formed, the standard cell layout A is changed to the standard cell layout B (claim 14).

As an effect of the present invention, according to the first and second aspects of the present invention, it is possible to extend one or a plurality of gate lengths in a standard cell only by providing an extended poly, suppress a short channel effect, and suppress a gate leakage current. It becomes possible. Further, if the activation rate and delay of each gate of the standard cell are taken into consideration, it is possible to arrange an extended poly for a part of inputs.
According to the invention of claim 3, since the extended poly region is provided on the source side, the area on the drain side is not increased, so that the gate leakage current is suppressed without deteriorating the cell performance (propagation delay) at the minimum gate length. It becomes possible.
According to the fourth and fifth aspects of the present invention, the extended poly can be arranged using the bend gate, and the gate leakage current can be suppressed without increasing the cell width.
According to the sixth aspect of the present invention, it is possible to suppress the noise in the switching of the gate by delaying the simultaneous switching of the same node partially or stepwise by the extended poly.
According to the seventh aspect of the present invention, it is possible to suppress the noise by changing the threshold value by arranging the extended poly in the MOS transistor on one side with respect to the transition of the same node.
According to the invention of claim 8, the standard cell library having the effects of claims 1 to 7 can be obtained.
According to the ninth to eleventh aspects of the present invention, a semiconductor integrated circuit capable of suppressing the leakage current without changing the existing process steps can be obtained. In particular, according to the invention of claim 11, when a plurality of conventional implantation steps for controlling Vth are provided and a plurality of libraries are configured on one chip, the number of wafer manufacturing steps increases because of different Vth implantation steps. However, since the extended poly can be arranged by revising only the poly gate, no additional process is required in the process.
According to the invention of claims 12 to 14, it is possible to provide a method for designing a semiconductor integrated circuit capable of suppressing a leakage current without changing an existing process step.

The first embodiment of the present invention will be described below.
FIG. 1 shows a layout of a conventional standard cell which is a premise of the present invention. FIG. 1 shows an example of a two-input NAND cell. Reference numeral 71 denotes a gate poly constituting the gate electrode of the MOS transistor, 72 denotes a contact, and the contacts 72 are all arranged in the source / drain diffusion region 7b. Reference numeral 73 is a power supply line to which a power supply potential is supplied, 74 is a wiring, 75 and 76 are input terminals (1) and (2), 77 is an output wiring connected to the source / drain diffusion region 7b through the contact 72, Reference numeral 78 denotes a ground line, 79 denotes a cell frame, and 7a denotes an N well region. The power supply line 73, the wiring 74, the input terminals 75 and 76, the output wiring 77, and the ground line 78 are formed of the same wiring layer.

The size of the standard cell layout in FIG. 1 is as follows.
The distance between the gate poly 71 and the adjacent contact 72: Space-1
・ Width of gate poly 71: Width-2
Standard cell width: Cell-Width-1

  Here, the minimum rule of the designated process design rule is used for the distance (Space-1) between the gate poly 71 and the adjacent contact 72 in order to minimize the standard cell width (Cell-Width-1). For the width (Width-2) of the gate poly 71, the minimum rule of the process design rule is used in order to maximize the propagation delay.

Next, the standard cell layout of the present invention will be described.
FIG. 2 is a diagram showing a standard cell layout according to the first embodiment of the present invention.
In FIG. 2, the standard cell layout is different from the configuration of FIG. 1 in that the standard cell layout is provided with a region for arranging an extended poly between the gate poly 11 and the adjacent contact 12, and is otherwise the same as the configuration of FIG. A gate poly 11, a contact 12, a power supply line 13, a wiring 14, input terminals 15 and 16, an output wiring 17, a ground line 18, a cell frame 19, an N well region 1a, and a source / drain diffusion region 1b.

Here, the size of the standard cell layout in FIG. 2 is as follows.
The distance between the gate poly 11 and the adjacent contact 12: Space-2 (> Space-1)
-Width of gate poly 11: Width-2
Standard cell width: Cell-Width-3 (> Cell-Width-1)

  That is, the width of the gate poly 11 is the minimum width (Width-2) defined by the design rule, and the distance between the gate poly 11 and the adjacent contact 12 is larger than the minimum distance (Space-1) defined by the design rule. By doing so, an extended poly arrangement region is provided. As a result, the extended poly can be arranged without changing anything other than the gate poly 11 with respect to the width of the standard cell, and the gate length can be extended only by the revision of the gate poly, thereby suppressing the short channel effect. An example is shown in FIGS.

  FIG. 3 shows an example in which the extended poly 1c is arranged on all the gate polys 11, and FIG. 4 shows an example in which the extended poly is arranged only on the gate poly on the input terminal (1) 15 side.

  In FIG. 2, an extended poly arrangement region is provided on the source region side of the MOS transistor with respect to the gate poly. As a result, since the area on the drain region side is not increased, the gate leakage current can be suppressed without deteriorating the cell performance (propagation delay) at the minimum gate length.

Next, a second embodiment of the present invention will be described.
FIG. 5 shows a layout of a conventional standard cell which is a premise of the present invention. FIG. 5 is an example of a two-input NAND cell similar to FIG. 1, but differs from FIG. 1 in that the source / drain diffusion region is salicide and the minimum number of contacts is arranged. 1 and includes a gate poly 81a, a contact 82, a power supply line 83, wiring 84, input terminals 85 and 86, an output wiring 87, a ground line 88, a cell frame 89, an N well region 8a, and a source / drain diffusion region 8b.

Here, the size of the standard cell layout in FIG. 5 uses the minimum rule of the process design rule as in the case of FIG. 1, and is as follows.
-Distance between gate poly 81a and adjacent contact 82: Space-1
-Width of gate poly 81a: Width-2
Standard cell width: Cell-Width-1
Source / drain extension: Space-a
The source / drain extension is an overlap distance of the source / drain diffusion region 8b with respect to the gate poly 81a, and the minimum rule of the process design rule is applied thereto.

  As a reference example, FIG. 6 shows an example in which a gate poly bend (hereinafter referred to as a bend gate) is configured in a MOS transistor in the layout of FIG. The configuration is the same as that of FIG. 5 except that the linear gate poly 81a in FIG. 5 is replaced with a gate poly 81b of a bend gate.

Here, the size of the standard cell layout in FIG. 6 uses the minimum rule of the process design rule as in the case of FIG. 5, and is as follows.
The distance between the gate poly 81b and the adjacent contact 82: Space-1
-Width of gate poly 81a: Width-2
Standard cell width: Cell-Width-2 (<Cell-Width-1)
Source / drain extension: Space-a
-Spacing between adjacent gate polys 81b: Space-c

Next, the standard cell layout of the present invention will be described.
FIG. 7 is a diagram showing a standard cell layout according to the second embodiment of the present invention.
In FIG. 7, the standard cell layout is different from the configuration of FIG. 5 in that it has a region for arranging an extended poly on the side opposite to the adjacent contact 22 with respect to the gate poly 21, and the configuration of FIG. And includes a gate poly 21, a contact 22, a power supply line 23, a wiring 24, input terminals 25 and 26, an output wiring 27, a ground line 28, a cell frame 29, an N well region 2a, and a source / drain diffusion region 2b.

Here, the size of the standard cell layout in FIG. 7 is as follows.
The distance between the gate poly 21 and the adjacent contact 22: Space-1
・ Width of gate poly 21: Width-2
Standard cell width: Cell-Width-1
Source / drain extension: Space-b (> Space-a)
-Spacing between adjacent gate polys 21: Space-d (> Space-c)

  That is, the width of the gate poly 21 is the minimum width (Width-2) defined by the design rule, and the distance (Space-b) of the source / drain extension with respect to the gate poly 21 and the distance (Space-d) between the adjacent gate poly 21 are set. An extended poly arrangement area is provided as being larger than the minimum distances (Space-a and Space-c, respectively) defined by the design rule. Thus, by extending the extended poly so that it becomes a bend gate, without increasing the standard cell width (while maintaining Cell-Width-1), the gate length is extended only by the revision of this gate poly, and the short channel The effect can be suppressed. An example is shown in FIG.

  FIG. 8 shows an example in which the extended poly 2c is divided and arranged so as to avoid the contact 22 in the length direction of the gate poly 21, thereby forming a bend gate.

Next, a third embodiment of the present invention will be described.
FIG. 9 shows a layout of a conventional standard cell which is a premise of the present invention. FIG. 9 shows an example of a standard cell layout of an inverter that requires drive capability. In consideration of adjacent arrangement, MOS transistors are arranged in a divided manner in order to unify cell heights. Here, reference numeral 91 denotes a gate poly constituting the gate electrode of the MOS transistor, 92 denotes a contact, and all the contacts 92 are arranged in the source / drain diffusion region 9b. Reference numeral 93 denotes a power supply line to which a power supply potential is supplied, 94 is a wiring, 95 is an input terminal, 97 is an output wiring connected to the source / drain diffusion region 9b through the contact 92, 98 is a grounding line, and 99 is a cell frame. , 9a is an N well region. The power supply line 93, the wiring 94, the input terminal 95, the output wiring 97, and the ground line 98 are formed by the same wiring layer.

The standard cell layout size in FIG. 9 uses the minimum process design rule as in FIG. 1, and is as follows.
-Distance between gate poly 91 and adjacent contact 92: Space-1
・ Width of gate poly 91: Width-2
Standard cell width: Cell-Width-4

Next, the standard cell layout of the present invention will be described.
FIG. 10 is a diagram showing a standard cell layout according to the third embodiment of the present invention.
In FIG. 10, the standard cell layout is different from the configuration of FIG. 9 in that it has a region for arranging an extended poly between a part of the gate poly 31b and 31c and the contact 32 on the adjacent source region side. 9 is the same as the configuration of FIG. 9 except that the gate poly 31a, 31b, 31c, contact 32, power supply line 33, wiring 34, input terminal 35, output wiring 37, ground line 38, cell frame 39, N well region 3a, source A drain diffusion region 3b is provided.

Here, the size of the standard cell layout in FIG. 10 is as follows.
-Distance between gate poly 31a and adjacent contact 32: Space-1
The distance between the gate poly 31b and the adjacent contact 32: Space-2 (> Space-1)
The distance between the gate poly 31c and the adjacent contact 32: Space-3 (> Space-2)
-Width of gate poly 31: Width-2
Standard cell width: Cell-Width-5 (> Cell-Width-4)

  That is, the width of the gate poly 31a, 31b, 31c is the minimum width (Width-2) defined by the design rule, and the interval between the one part of the gate poly 31b, 31c and the adjacent source region side contact 32 is determined by the design rule. The extended poly arrangement area is provided by making the distance greater than the minimum distance (Space-1) defined. In addition, the width of the extension poly arrangement region (the distance between the gate poly and the source region side contact 32) is different for each gate poly. As a result, the extended poly can be arranged without changing anything other than the gate poly 31b and 31c with respect to the width of the standard cell, and the gate length can be expanded only by the revision of the gate poly, thereby suppressing the short channel effect. . An example is shown in FIG.

  In FIG. 11, for the divided MOS transistors of the same node, the extended poly 3c is arranged in the gate poly 31b, the extended poly 3d having a width different from that of the extended poly 3c is arranged in the gate poly 31c, and the devices having different gate lengths (Width). -2, Width-3, Width-4). Thereby, it is possible to suppress noise in the switching of the gate by delaying the switching at the same node partially or stepwise.

  Next, FIG. 12 shows a variation of the third embodiment. As a standard cell layout, a MOS transistor is divided into a plurality of parts at the same node, and either a PMOS transistor or an NMOS transistor (PMOS transistor in FIG. 12). 9 is different from the configuration of FIG. 9 in that an extension poly is provided between the gate poly 41 and the adjacent contact 42 on the source region side. 41, a contact 42, a power supply line 43, a wiring 44, an input terminal 45, an output wiring 47, a ground line 48, a cell frame 49, an N well region 4a, and a source / drain diffusion region 4b.

Here, the size of the standard cell layout in FIG. 12 is as follows.
The distance between the gate poly 41 and the adjacent contact 42 (PMOS transistor side): Space-2 (> Space-1)
-Width of gate poly 41: Width-2
Standard cell width: Cell-Width-5 (> Cell-Width-4)

  That is, the width of the gate poly 41 is the minimum width (Width-2) defined by the design rule, and the distance between the gate poly 41 on the PMOS transistor side and the contact 42 on the adjacent source region side is the minimum distance defined by the design rule. By setting it to be larger than (Space-1) (Space-2), an extended poly arrangement region is provided. As a result, the extended poly can be arranged without changing anything other than the gate poly 41 on the PMOS transistor side with respect to the width of the standard cell, and the gate length is expanded only by the revision of the gate poly, thereby suppressing the short channel effect. Can do. An example is shown in FIG.

  FIG. 13 shows a configuration example in which the extended poly 4c is arranged only on the PMOS transistor side with respect to the divided MOS transistors of the same node. Further, in FIG. 13, the width of the extended poly arrangement region on the PMOS transistor side may be changed for each gate poly to form a device having a different gate length as in FIG. This makes it possible to suppress noise by changing the threshold value for the transition of the same node.

Next, a method for designing a semiconductor integrated circuit using the standard cell layout of the present invention and a semiconductor integrated circuit based thereon will be described.
FIG. 14 shows an example of standard cell arrangement constituting a conventional semiconductor integrated circuit. In FIG. 14, each quadrangle surrounded by a solid line or a dotted line means one standard cell. In addition, reference signs A to E in the rectangle indicate standard cells having different functions such as an inverter and NAND, and reference sign (T1) indicates a standard cell library. For example, the standard cell indicated by the arrow a in the figure is arranged with the standard cell A included in the standard cell library (T1). In FIG. 14, all standard cells included in the standard cell library (T1) are arranged.

Next, FIG. 15 shows an example of the standard cell arrangement constituting the semiconductor integrated circuit according to the present invention.
Here, three standard cell libraries (T1), (T2), and (T3) are provided. For example, the standard cell library (T1) has extensions as shown in FIGS. 2, 7, 10, and 11. A standard cell layout having a poly layout area, which does not have an extended poly layout, that is, includes a standard cell layout with a standard gate length. In the standard cell libraries (T2) and (T3), the standard cell library (T1) Includes the standard cell layout in which the gate length is extended by arranging the extended poly as shown in FIGS. 3, 4, 8, 11, and 13. It is a waste.

Using these standard cell libraries (T1), (T2), and (T3), a semiconductor integrated circuit is designed as follows.
(S1) First, the standard cells are arranged and wired using the standard cell layout included in the standard cell library (T1) to design a semiconductor integrated circuit. This configuration is shown, for example, in FIG.
(S2) The semiconductor integrated circuit having the standard cell arrangement of FIG. 14 is verified.
(S3) Next, when it is necessary to change the standard cell, one standard cell in the arrangement of FIG. 14 is changed to the standard cell layout of the same logic included in the standard cell libraries (T2) and (T3). The standard cell arrangement shown in FIG. In FIG. 15, the standard cells with hatched lines are changed. For example, standard cells A (T2) and A (T3) have the same logic as standard cells A (T1) but different extension polys. The standard cell A (T1) indicated by the arrow a in FIG. 14 is changed to the standard cell A (T3) in FIG.

  Here, when the standard cell needs to be changed, for example, in the placement and routing of FIG. 14, there is a margin in gate delay and local concentration is observed in the estimation of power consumption, or there is concentration of simultaneous switching. Etc.

  As described above, the standard cell change in the semiconductor integrated circuit design method of the present invention is applicable to any step of the conventional standard cell automatic placement and routing flow because the cell size and the metal terminal position do not vary. Even after the circuit FIX, it is possible to revise by means such as exchanging the cells by manual correction work or manually placing the extension poly.

  Further, the gate length may be extended by designing a semiconductor integrated circuit using the standard cell layout of the present invention and then disposing an extended poly with respect to the standard cell layout.

  In the description of the above embodiment, an example in which the width of the standard cell is different with respect to the standard cell layout is shown, and an example in which the width becomes larger than the conventional one is disadvantageous. The ratio of the extended poly region inserted with respect to the gate length is at most about several percent. In the illustrated example, the ratio is exaggerated. However, in the case where the ratio is small, the cell width does not increase in the case of a cell having a sufficient transistor arrangement with respect to the gate length in general with respect to the wiring grid. Further, in the case of multi-Vth control by conventional injection, it is a change at the standard cell level, and the present invention can be controlled in units of MOS transistors, and more precise leak control is possible.

It is a figure which shows the structural example (1) of the conventional standard cell layout. It is a figure which shows the structure of the standard cell layout which concerns on the 1st Embodiment of this invention. It is the structural example (1) which has arrange | positioned the extension poly to the layout of FIG. It is the structural example (2) which has arrange | positioned the extension poly to the layout of FIG. It is a figure which shows the structural example (2) of the conventional standard cell layout. It is a figure which shows the structural example (3) of the conventional standard cell layout. It is a figure which shows the structure of the standard cell layout which concerns on the 2nd Embodiment of this invention. It is the structural example which has arrange | positioned the extension poly to the layout of FIG. It is a figure which shows the structural example (4) of the conventional standard cell layout. It is a figure which shows the structure (1) of the standard cell layout which concerns on the 3rd Embodiment of this invention. It is the structural example which has arrange | positioned the extension poly to the layout of FIG. It is a figure which shows the structure (2) of the standard cell layout which concerns on the 3rd Embodiment of this invention. 13 is a configuration example in which an extended poly is provided in the layout of FIG. It is a figure which shows the example of a standard cell arrangement | positioning which comprises the conventional semiconductor integrated circuit. It is a figure which shows the example of a standard cell arrangement | positioning which comprises the semiconductor integrated circuit in this invention.

Explanation of symbols

11, 21, 31a, 31b, 31c, 41, 71, 81a, 81b, 91 Gate poly 12, 22, 32, 42, 72, 82, 92 Contacts 13, 23, 33, 43, 73, 83, 93 Power line 14 24, 34, 44, 74, 84, 94 Wiring 15, 25, 35, 45, 75, 85, 95 Input terminal 1
16, 26, 76, 86 Input terminal 2
17, 27, 37, 47, 77, 87, 97 Output wiring 18, 28, 38, 48, 78, 88, 98 Ground line 19, 29, 39, 49, 79, 89, 99 Cell frame 1a, 2a, 3a , 4a, 7a, 8a, 9a N well 1b, 2b, 3b, 4b, 7b, 8b, 9b Source / drain diffusion region 1c, 2c, 3c, 3d, 4c

Claims (14)

In a standard cell layout which is included in a standard cell library and used to design a semiconductor integrated circuit and has one or a plurality of MOS transistors as logic cells,
A standard cell layout comprising a region for arranging an extended poly between a gate poly constituting a gate electrode of the MOS transistor and an adjacent contact.   The width of the gate poly is a minimum width defined by a design rule, and an extended poly arrangement area is provided with an interval between the gate poly and an adjacent contact being larger than a minimum distance defined by the design rule. Item 2. The standard cell layout according to item 1.   2. The standard cell layout according to claim 1, wherein the extended poly arrangement region is provided on the source region side of the MOS transistor with respect to the gate poly. In a standard cell layout which is included in a standard cell library and used to design a semiconductor integrated circuit and has one or a plurality of MOS transistors as logic cells,
A standard cell layout comprising a region for disposing an extended poly on a side opposite to an adjacent contact with respect to a gate poly constituting a gate electrode of the MOS transistor.   The width of the gate poly is the minimum width specified by the design rule, and the extension poly placement region is set such that the distance between the source drain and the gate poly and / or the distance to the adjacent gate poly is larger than the minimum distance specified by the design rule. The standard cell layout according to claim 4, comprising:   6. The standard cell layout according to claim 1, wherein when the MOS transistor is divided into a plurality at the same node, each gate electrode has a different gate length depending on the extended poly.   6. The MOS transistor according to claim 1, wherein the MOS transistor is divided into a plurality at the same node, and one of the PMOS transistor and the NMOS transistor has a different gate length depending on the extension poly. Standard cell layout described in 1.   A standard cell library comprising the standard cell layout according to claim 1.   A semiconductor integrated circuit designed using the standard cell layout according to any one of claims 1 to 7.   A semiconductor integrated circuit, which is designed using the standard cell layout according to any one of claims 1 to 5, wherein an extended poly is arranged in the standard cell layout and a gate length is extended.   Using the standard cell layout according to any one of claims 1 to 5, a first standard cell library having a standard cell layout A having a standard gate length in which no extension poly is arranged, and the standard cell layout A A second standard cell library having a standard cell layout B in which an extended poly is arranged in the layout and the gate length is extended, and after forming a semiconductor integrated circuit using the standard cell layout A, the standard cell layout A semiconductor integrated circuit characterized in that A is changed to a standard cell layout B.   A semiconductor integrated circuit design method, comprising: designing a semiconductor integrated circuit using the standard cell layout according to claim 1.   A semiconductor integrated circuit comprising: designing a semiconductor integrated circuit using the standard cell layout according to any one of claims 1 to 5; and extending a gate length by arranging an extension poly in the standard cell layout. Design method. Using the standard cell layout according to any one of claims 1 to 5, a first standard cell library having a standard cell layout A having a standard gate length in which no extension poly is arranged, and the standard cell layout A A second standard cell library having a standard cell layout B in which an extended poly is arranged in the layout and the gate length is extended;
A method of designing a semiconductor integrated circuit, comprising: forming a semiconductor integrated circuit using the standard cell layout A; and then changing the standard cell layout A to a standard cell layout B.

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