JP2005228760A - Charge storage memory and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of a memory cell and extend the data holding time.
A bottom barrier layer 4, a first charge storage layer 5, a second charge storage layer 6, a top barrier layer 7, and a gate electrode 8 are sequentially stacked on a semiconductor substrate 1 to form a second charge. The density of the localized levels of the storage layer 6 is set higher than the density of the localized levels of the first charge storage layer 5.
[Selection] Figure 1

Description

  The present invention relates to a charge storage type memory made of a MOS type or MIS type semiconductor device and having a memory function by storing electrons in a gate insulating film, and a method for manufacturing the same.

  The operation of a conventionally known charge storage type memory will be described. As a charge storage type memory, an EEPROM (flash memory) that stores electrons in a floating gate is well known. In this floating gate type flash memory, the thickness of the insulating film cannot be reduced in order to prevent electrons stored in the floating gate from passing through the insulating film. There was a limit to miniaturization.

SONOS (Semiconductor-Oxide-Nitride-Oxide-Semiconductor) memory using Si ₃ N ₄ as a charge storage layer has attracted attention as a next-generation memory that improves the drawbacks of the floating gate flash memory. SONOS is also called a trap memory because it uses a trap level spatially localized as a method of charge accumulation. As a charge storage layer of this trap memory, there is a recent research report that a structure using Al ₂ O _{3 in} addition to Si ₃ N ₄ has extremely good data retention characteristics as a memory (for example, non-patent literature) 1).

Here, the structure using Al ₂ O ₃ will be described in detail by taking an example. FIG. 11 is a cross-sectional view of an example of a trap memory that has attracted attention in recent years. The bottom barrier layer 14 of SiO ₂ is 1 nm in a position straddling the source 12 and the drain 13 of the p-type single crystal silicon substrate 11. The Al ₂ O ₃ charge storage layer 15 is successively deposited by 10 nm, the SiO ₂ top barrier layer 17 is successively deposited by 10 nm, and finally the gate electrode 18 of n-type polysilicon is deposited.

FIG. 12 shows the band structure of the trap memory of FIG. The charge storage layer 15 of Al ₂ O _3, trap level is, the conduction band of Al ₂ O _3, is present at the position below the 2.4 eV. Since electrons are trapped in this trap level, it is difficult for charges to escape through the bottom barrier layer 14. For this reason, the bottom barrier layer 14 can be made thin, and the voltage and miniaturization of writing and erasing can be reduced.

  Now, both the floating gate type flash memory and the trap memory (SONOS) change the threshold voltage of the transistor by injecting electrons into the charge storage layer. , “0” is determined.

  FIG. 13 shows a trap memory in which 20 V is applied to the p-type substrate 11, the gate electrode 18 is set to 0 V, the source 12 and the drain 13 are opened, and electrons are drawn from the charge storage layer 15 to the p-type substrate 11. The state of the movement of electrons when the threshold voltage is set to be negative is shown. This operation is called memory erasure.

  On the other hand, FIG. 14 shows a threshold value by injecting electrons from the p-type substrate 11 into the charge storage layer 15 by setting the p-type substrate 11, the source 12 and the drain 13 to 0 V, applying 20 V to the gate electrode 18. It shows how the electrons move when the voltage is set to positive. This operation is called memory writing.

  FIG. 15 shows a threshold distribution of a memory cell of a floating gate type memory or trap memory (SONOS) set by injecting electrons. If the voltage of the word line is 0V, current flows in the memory cell if it is “1”, and if it is “0”, no current flows. The state of “1” and “0” is distinguished depending on whether a current flows or not. Therefore, one memory cell can store 1-bit data.

  FIG. 16 shows a state having four types of groups as the threshold distribution of the memory cells. The threshold voltage has a state of “11” as an erase state and a state of “10”, “01”, and “00” as a write state. In this case, since there are four threshold states per cell, there are 2 bits per cell.

  Now, in the above trap memory, electrons are accumulated at the localized levels. A memory function is provided by using the fact that electrons are captured without causing a tunnel phenomenon from the localized level, that is, captured without leaking. In the case of a normal SONOS memory, it is known that the distance between the nearest local levels is about 5 nm. In this case, a data retention characteristic of about 10 years is obtained.

Next, a method for manufacturing a conventional SONOS memory using the ECR sputtering method will be described in detail. The ECR sputtering method uses plasma to grow a thin film, and it is known that a good quality thin film can be grown on Al ₂ O ₃ (see, for example, Non-Patent Document 2).

  FIG. 17 shows an ECR sputtering apparatus. 21 is a waveguide for introducing a microwave of 2.45 GHz, 22 is a coil for generating a magnetic field, 23 is a quartz window for transmitting microwaves, 24 is also a coil for generating a magnetic field, 25 is a chamber, and 26 is an axis 26a. A holder which can be rotated at the center, 27 is a semiconductor substrate held by the holder 26, 28 is a target, 29 is a 13.56 MHz high frequency oscillator for applying high frequency power to the target 28, and 30 and 31 are gas injection portions. is there. Here, in order to generate the electron cyclotron resonance plasma 32, a microwave of 2.45 GHz and 500 W and a magnetic flux of 875 gauss generated by the coils 22 and 24 are used. A film is grown on the semiconductor substrate 27 by causing the plasma 32 to have a kinetic energy of about 10 to 20 eV by a divergent magnetic field and extracting the plasma 32 in the vertical direction (in the direction of the semiconductor substrate 27). Since the ECR sputtering apparatus has a very low energy of 10 to 20 eV, it is possible to grow a high-quality thin film without defects in the film crystal.

FIG. 18 shows aluminum oxide on the semiconductor substrate 27 when argon (Ar) gas is injected from the gas injection section 30 and oxygen (O ₂ ) gas is injected from the gas injection section 31 and Al is used as the target 28. The growth rate and refractive index (measurement wavelength: 632.8 nm) are plotted against the flow rate of oxygen gas. The white circle is the refractive index, the black circle is the growth rate, and the horizontal axis is the oxygen gas flow rate.

Regarding the refractive index, a value of 1.6 to 1.7 was obtained at an oxygen gas flow rate of 4 to 9 sccm, which is a normal value of aluminum oxide having a stoichiometric composition (Al ₂ O ₃ ). is there. When the oxygen gas flow rate is 4 sccm or less, the refractive index gradually increases. From this, the composition Al _{2 + x} O ₃ (x> 0) state in which Al exists excessively from the ideal composition Al ₂ O ₃ state. It turns out that it changes to.

  Also in the growth rate, the growth rate varies greatly depending on the oxygen gas flow rate. In the region of 7-9 sccm, the growth rate is very slow at 1 nm / min. This is because the oxygen gas flow rate is large and the surface of the Al target is oxidized, making it difficult for Al atoms to jump out. In the ECR sputtering method, this region is called an oxide region (region (3)).

In the region of 4-7 sccm, the growth rate is very fast at 6.5 nm / min. This is because the Al target surface is not oxidized and Al atoms are likely to jump out because the oxygen gas flow rate is small. In the ECR sputtering method, this region is called a metal region (region (2)). In the metal region, it is known that when aluminum oxide is deposited, a film having a good composition Al ₂ O ₃ with very few localized levels can be deposited.

Here, the equivalent oxide thickness EOT (equivalent oxide thickness) is
When defined as EOT≡ [(dielectric constant of SiO ₂ ) / (dielectric constant of insulator)] × insulator film thickness, an Al ₂ O ₃ film having a dielectric constant larger than SiO ₂ is compared with the same EOT In addition, since the actual film thickness can be made larger than that of the SiO ₂ film, it is known that the leakage current flowing in the insulating film is reduced.

Next, a region where the oxygen gas flow rate is even smaller will be described. By reducing the oxygen gas flow rate as in the region of 0 to 4 sccm in FIG. 18, the growth rate gradually decreases again from 6.5 nm / min. This is because oxygen is insufficient and Al ₂ O ₃ is difficult to grow. Here, this region is referred to as a metal rich region (region (1)).

In such a metal rich region (1), it can be seen that a composition Al _{2 + x} O ₃ (x> 0) in which Al atoms are excessively supplied is grown by observing the change in refractive index. . A film of Al _{2 + x} O _{3 with} an excess of Al atoms is expected to generate a large number of localized levels due to Al atoms in the insulator and accumulate electrons there. In the ECR sputtering method, the formation of localized levels can be controlled by controlling the oxygen flow rate in the metal rich region (1). In the prior art, deposition of a film of Al _{2 + x} O _{3 with} an excess of Al atoms was realized by using the metal rich region (1) of the ECR sputtering method.

FIG. 19 shows a cross-sectional view of the entire structure of the charge storage type memory manufactured by the above method. On the p-type silicon substrate 41, as a bottom barrier layer 44, Al ₂ O ₃ is grown to 4.5 nm with an oxygen flow rate of 5.5 sccm, and then Al _{2 + x} O ₃ charges are charged with an oxygen flow rate of 0 to 4 sccm. The storage layer 45 was grown to 4.5 nm, and then the Al ₂ O ₃ top barrier layer 47 was grown to 9 nm with an oxygen flow rate of 5.5 sccm. The gate electrode 48 is formed by evaporating Al.

FIG. 20 shows a band structure in the case where the charge storage layer 45 of the charge storage memory shown in FIG. 19 has a localized level. FIG. 21 shows CV characteristics of an Al _{2 + x} O ₃ diode grown as the charge storage layer 45 under the condition of the metal region (2) with an oxygen flow rate of 4 sccm. Before forming the gate electrode 48, heat treatment is performed in a high vacuum at 600 ° C. for about 3 minutes. In this case, it is understood that the localized level is not generated so much in the charge storage layer 45, and hysteresis due to the charge storage effect does not occur in the CV characteristics.

FIG. 22 shows the CV characteristics of the Al _{2 + x} O ₃ diode grown as the charge storage layer 45 under the condition of the metal rich region (1) with an oxygen flow rate of 2 sccm. This sample was also subjected to heat treatment in a high vacuum at 600 ° C. for about 3 minutes before forming the gate electrode 48. In this case, many localized levels are generated in the charge storage layer 45, and hysteresis due to the charge storage effect occurs in the CV characteristics. Here, when the gate voltage is 1 V, a state with a large capacity is A, and a state with a small capacity is B.

FIG. 23 shows the time change of the capacitance value of the charge storage type alumina (Al _{2 + x} O ₃ ) diode when the gate voltage is 1 V (states A and B) in FIG. In state A, the value hardly changes even after 30 minutes. Next, when the change in the capacitance value is examined with the state as B, the value hardly changes even after 30 minutes. Next, when the capacity value was measured again with the state as A, it was found that the value hardly changed even after 2 hours. From this result, it is expected that there will be no significant change after 10 years (3 × 10 ⁸ seconds) and a sufficiently large margin will be taken. As described above, since the high-quality Al ₂ O ₃ film having few defects is used for the barrier layers 44 and 47, good charge retention characteristics can be obtained, and Al _{2 + x} O in which the oxygen flow rate is reduced and Al is increased. It has been clarified that the charge storage layer ₃ operates very well as a memory because it stores electrons in the trap.

  Now, the size of the current state-of-the-art memory cell is 90 nm square (90 nm × 90 nm), but in the future, the size of the memory cell will be further miniaturized to increase the capacity of the memory. It is considered that a memory cell of 20 nm × 20 nm or less is also realized. At this time, assuming that the height (thickness) of the charge storage layer is about 10 nm in a 20 nm square memory cell, the distance between the nearest localized levels is about 5 nm. In the layer region, the number of localized levels can be obtained by the following equation.

(20 nm / 5 nm) ² × (10 nm / 5 nm) = 32 (1)
This number of 32 is extremely small and is expected to vary considerably in each memory cell. Further, storing as many electrons as possible in the charge storage layer has the advantage that the threshold voltage changes greatly and the “1” and “0” states of the memory can be clearly distinguished.

From the above viewpoint, it is necessary to increase the number of localized levels of the charge storage layer in each memory cell as much as possible. Therefore, if the number of localized levels is 128, which is four times the 32, the distance between the nearest localized levels is about 5 nm / 4 ^1/3 = 3.15 nm. It becomes. However, if the distance between the localized levels is shortened in this way, electrons trapped in the localized level are likely to tunnel to the adjacent localized level. The tunnel probability can be expressed by the following formula in the general formula (see, for example, Non-Patent Document 3).

p = exp (−αφ ^1/2 d) (2)
Here, φ is the barrier height of the tunnel barrier, d is the thickness of the tunnel barrier, and α is a coefficient. Electrons in the charge storage layer are eventually lost by leaking from the bottom barrier layer to the semiconductor substrate due to a tunnel phenomenon, but the number of electrons lost is proportional to the tunnel probability. Therefore, it can be seen that the data retention time is longer when the tunnel probability is smaller.

From equation (2), the change in tunnel barrier thickness has an exponential effect on the tunnel probability. From simulations and experiments, it is known that when the thickness of the tunnel barrier layer is reduced by 1 nm, the tunnel current due to the tunnel increases about 100 times (for example, see Non-Patent Document 4). Therefore, when the distance between the localized levels is reduced from 5 nm to 3 nm, it is expected that the leakage current due to the tunnel is increased about 10,000 times. This means that the data retention performance of the trap memory deteriorates, for example, from 10 years (3 × 10 ⁸ seconds) to 8 hours (3 × 10 ⁴ seconds).

T. Sugizaki et al. “Novel Muli-bit SONOS Type Flash Memory Using a High-k Charge Trapping Layer” 2003 Symposium on VLSI Thechnology Digest of Technical Papers, Page 27. Y. Jin, K. Saito, M. Shimada and T. Ono, “Using electron cyclon resonance sputtering in the deposition of ultrathin Al2O3 gate dielectrics”, J. Vac. Sci. Technol. B21 (3), p.942-948 , (2003). S.M.Sze, "Physics of Semiconductor Devices" 2nd Edition, John Wiley & Sons.Inc., Page 541,1981. JJLee, X.Wang, W.Bai, N.Lu, J.Liu, and DLKwong, "Theoretical and experimental investigation of Si nanocrystal memory device with Hf02 high-k tunneling dielectic" 2003 Symposium on VLSI Technology Digest of Technical Papers , page 33.

  As described above, when attempting to reduce the size of the memory cell, if the number of localized levels in the charge storage layer is to be increased as much as possible, it is necessary to reduce the distance between the nearest localized levels. For this reason, there is a problem that the data retention performance deteriorates.

  An object of the present invention is to reduce the local level density on the bottom barrier layer side of the charge storage layer and increase the local level density on the top barrier layer side so that the tunnel from the charge storage layer via the bottom barrier layer It is an object of the present invention to provide a charge storage type memory and a method of manufacturing the same, which can satisfy both the miniaturization of the memory cell and the improvement of the data retention performance.

  The invention according to claim 1 is a semiconductor substrate, a bottom barrier layer deposited on the top surface of the semiconductor substrate, a charge storage layer deposited on the top surface of the bottom barrier layer, and deposited on the top surface of the charge storage layer. A charge storage type memory having a top barrier layer thicker than the barrier layer and a gate electrode formed on an upper surface of the top barrier layer, wherein the threshold value is changed depending on whether electrons are stored in the charge storage layer; The storage layer is composed of a first charge storage layer located on the bottom barrier layer side, a plurality of elements located on the top barrier layer side and the same as the first charge storage layer, A two-layer structure including a second charge accumulation layer having a higher localized level density than that of one charge accumulation layer is characterized.

  According to a second aspect of the present invention, in the charge storage type memory according to the first aspect, the bottom barrier layer and the top barrier layer are made of silicon oxide, and the charge storage layer is made of silicon nitride, aluminum oxide, or silicon oxide. It is characterized in that a local level is generated by excessively containing a metal atom or a semiconductor atom in any one of them.

  According to a third aspect of the present invention, in the charge storage type memory according to the first aspect, the charge storage layer and the top barrier layer are made of the same insulator, and the top barrier layer is an insulator having a stoichiometric composition. The first charge storage layer has a stoichiometric excess of metal atoms or semiconductor atoms that are elements constituting the insulator, and has a localized level of the metal atoms or the semiconductor atoms. Electrons are accumulated at the localized level, and the second charge accumulation layer has a stoichiometrically equivalent metal atom or semiconductor atom as an element constituting the insulator in the first charge accumulation layer. In addition, the present invention is characterized in that the metal atom or the semiconductor atom is present in an excessive amount, and electrons are accumulated in the localized level.

  According to a fourth aspect of the present invention, in the charge storage type memory according to the first aspect, the bottom barrier layer, the charge storage layer, and the top barrier layer are formed of the same insulator, and the bottom barrier layer and the top The barrier layer is made of an insulator having a stoichiometric composition, and the first charge storage layer has a stoichiometric excess of metal atoms or semiconductor atoms as elements constituting the insulator, and the metal atoms or The semiconductor atom has a localized level so that electrons are accumulated in the localized level, and the second charge storage layer has a stoichiometric amount of a metal atom or a semiconductor atom which is an element constituting an insulator. Theoretically, the metal charge is present in excess of the first charge storage layer, has a localized level of the metal atom or the semiconductor atom, and electrons are accumulated in the localized level. Features.

  The invention according to claim 5 is the charge storage type memory according to claim 3 or 4, wherein aluminum oxide is used as the insulator, and aluminum atoms are used as the metal atoms present in the charge storage layer. And

  The invention according to claim 6 is the charge storage type memory according to claim 3 or 4, wherein silicon nitride is used as the insulator and silicon atoms are used as the semiconductor atoms present in the charge storage layer. And

  The invention according to claim 7 is the charge storage type memory according to any one of claims 1 to 6, wherein the semiconductor substrate is a single crystal silicon substrate, a polycrystalline silicon substrate, or an amorphous silicon substrate. It is characterized by.

The invention according to claim 8 is a method for manufacturing the charge storage type memory according to claim 3, wherein the electron cyclotron resonance type plasma generating means and a gas for supplying a rare gas and an oxygen gas to the plasma generating means are provided. Use sputtering means having at least supply means, a target made of aluminum installed in the plasma generation means, a semiconductor substrate installed in the plasma generation means, and high-frequency power application means to the target, At the time of forming the first charge storage layer, the refractive index of Al ₂ O _{3 in which} the refractive index of aluminum oxide deposited on the semiconductor substrate by sputtering is the stoichiometric composition of the aluminum oxide is formed by using the oxygen gas. The first supply amount having a higher refractive index than that of the second charge storage layer is formed. When the top barrier layer is formed, the oxygen amount deposited on the semiconductor substrate by the sputtering is a second supply amount in which the refractive index of the aluminum oxide is higher than the refractive index of the first charge storage layer. The gas is used as a third supply amount in which the refractive index of aluminum oxide deposited on the semiconductor substrate by sputtering becomes the refractive index of Al ₂ O ₃ which is the stoichiometric composition of the aluminum oxide. And

The invention according to claim 9 is a method for manufacturing the charge storage type memory according to claim 4, wherein the electron cyclotron resonance type plasma generating means and a gas for supplying a rare gas and an oxygen gas to the plasma generating means are provided. Use sputtering means having at least supply means, a target made of aluminum installed in the plasma generation means, a semiconductor substrate installed in the plasma generation means, and high-frequency power application means to the target, At the time of forming the first charge storage layer, the refractive index of Al ₂ O _{3 in which} the refractive index of aluminum oxide deposited on the semiconductor substrate by sputtering is the stoichiometric composition of the aluminum oxide is formed by using the oxygen gas. The first supply amount having a higher refractive index than that of the second charge storage layer is formed. The second supply amount in which the refractive index of aluminum oxide deposited on the semiconductor substrate by the sputtering is higher than the refractive index of the first charge storage layer is used, and the bottom barrier layer and the top barrier layer At the time of formation, the oxygen gas is supplied with a third supply amount in which the refractive index of aluminum oxide deposited on the semiconductor substrate by sputtering becomes the refractive index of Al ₂ O ₃ which is the stoichiometric composition of the aluminum oxide; It is characterized by.

  According to the charge storage type memory of the present invention, the charge storage layer has a two-layer structure of a first charge storage layer having a low localized level density and a second charge storage layer having a high localized level density, The first charge storage layer is disposed on the bottom barrier layer side, the second charge storage layer is disposed on the top barrier layer side, and the second charge storage layer having a high localized level density is separated from the semiconductor substrate. Since it is arranged on the far side, it is possible to eliminate almost all electric charges leaked by the tunnel in the direction of the semiconductor substrate through the bottom barrier layer, and there is an advantage that both the miniaturization of the memory cell and the improvement of the data retention performance can be satisfied. is there.

  In the present invention, in a charge storage memory having a structure in which a bottom barrier layer, a charge storage layer, a top barrier layer, and a gate electrode are sequentially stacked on the surface of a semiconductor substrate, the charge storage layer is formed of the first low localized level density. As a two-layer structure comprising a charge storage layer and a second charge storage layer having a high localized level density, the second charge storage layer is arranged on the side of the top barrier layer farthest from the semiconductor substrate, and the localized level By lowering the tunnel probability of the charge accumulated in the memory cell, the data retention time can be extended while maintaining a sufficient charge accumulation amount even when the memory cell is downsized. This will be described in detail below.

FIG. 1 is a cross-sectional view showing the structure of the charge storage type memory according to the first embodiment. In the first embodiment, the bottom barrier layer 4 of SiO ₂ is 1 nm and the first Al _{2 + x1} O ₃ (x1> 0) is placed at a position straddling the source 2 and drain 3 of the p-type single crystal silicon substrate 1. The charge storage layer 5 (type 2) of 10 nm, the second charge storage layer 6 (type 3) of Al _{2 + x2} O ₃ (x2> x1) is 0.3 nm (about one atomic layer), and the top of SiO ₂ Barrier layers 7 are sequentially stacked by 10 nm, and finally an n-type polysilicon gate electrode 8 is stacked. In this way, the first charge storage layer 5 (type 2) of Al _{2 + x1} O ₃ having a predetermined localized level is stacked on the bottom barrier layer 4 and the localized level density is increased thereon. A second charge storage layer 6 (type 3) of higher Al _{2 + x2} O ₃ is laminated by about one atomic layer.

  FIG. 2 is a diagram showing a band structure of the charge storage type memory of FIG. Trap levels exist in the regions of the first and second charge storage layers 5 and 6, and electrons are stored therein. The current in these charge storage layers 5 and 6 is a current that flows through the trap level. Further, the bottom barrier layer 4 does not have a trap level, and is a Fowler-Nordheim (F-N) tunnel type. Further, in the top barrier layer 7, since the film thickness is thicker than that of the bottom barrier layer 4, almost no current flows.

Assume that the number of localized levels in a 20 nm square and 10 nm high region is 128, and that 32 are arranged in the first charge storage layer 5 and only 96 in the second charge storage layer 6. At this time, in the first charge storage layer 5 (type 2), the distance between the localized levels is 5 nm. In the second charge storage layer 6 (type 3), since 96 localized levels are arranged in two dimensions of 20 nm square, the distance between the localized levels is 20 nm / (96). ^1/2 = 2 nm or so.

The charge storage layers 5 and 6 can be produced, for example, by the ECR sputtering method described above. This case is realized by reducing the oxygen gas flow rate (metal rich region (1) in FIG. 18). That is, when the first charge storage layer 5 is formed, oxygen gas is refracted so that the refractive index of aluminum oxide deposited by sputtering is higher than the refractive index of Al ₂ O ₃ which is the stoichiometric composition of the aluminum oxide. The first supply amount is a rate. When forming the second charge storage layer 6, oxygen gas is used as a second supply amount in which the refractive index of aluminum oxide deposited by sputtering is higher than the refractive index of the first charge storage layer 5. . Accordingly, the composition of the first charge storage layer 5 becomes a composition Al _{2 + x1} O ₃ (x1> 0) in which Al atoms are excessively supplied, and the composition of the second charge storage layer 6 is Al atoms. _{Becomes the} composition Al _{2 + x2} O ₃ (x2> x1) supplied in excess, and the localized levels of these Al atoms are generated.

  According to the first embodiment, the number of localized levels in the charge storage type memory cell can be increased, and in the tunnel path to the p-type single crystal silicon substrate 1, the nearest localized levels can be mutually connected. The distance between them can be maintained at 5 nm, and good data retention characteristics can be maintained. FIG. 3 shows the space of the localized charge level P of the first charge storage layer 5 (type 2: 3 layer localized level) and the second charge storage layer 6 (type 3: 1 layer localized level). A schematic diagram of the target position is shown.

FIG. 9 shows the effect on the mutual distance of the localized levels when Example 1 is used. In the conventional example, when 128 localized levels are arranged in a memory cell region having a height of 20 nm and a height of 10 nm, the mutual interval between the localized levels is 3.15 nm. On the other hand, according to the first embodiment, since the second charge storage layer 6 having a high density of 2 nm between the localized levels is provided at the position farthest from the semiconductor substrate 1, it is involved in leakage. The interval between the localized levels is 5 nm of the first charge storage layer 5, and tunnels between the localized levels can be almost eliminated. FIG. 10 shows an effect related to the data holding time when the first embodiment is used. Whereas the data retention time of the conventional example is 8 hours (3 × 10 ⁴ seconds), in the first embodiment, a long data retention time of about 10 years (3 × 10 ⁸ seconds) can be realized.

FIG. 4 is a sectional view showing the structure of the charge storage type memory according to the second embodiment. In this Example 2, the bottom barrier layer 4 of SiO ₂ is 1 nm and the first Al _{2 + x1} O ₃ (x1> 0) is placed at a position straddling the source 2 and drain 3 of the p-type single crystal silicon substrate 1. 10 nm for the charge storage layer 5 (type 2), 0.3 nm (about 1 atomic layer) for the second charge storage layer 6 (type 3) of Al _{2 + x2} O ₃ (x2> x1), Al ₂ O ₃ The top barrier layer 7A (type 1) is sequentially laminated by 10 nm, and finally, an n-type polysilicon gate electrode 8 is laminated. That is, the second embodiment is obtained by replacing the top barrier layer 7 in the charge storage type memory of the first embodiment with a 10 nm Al ₂ O ₃ top barrier layer 7A having very few localized levels.

As a result, in the second embodiment, the first and second charge storage layers 5 and 6 and the top barrier layer 7A can be formed of the same insulator Al ₂ O ₃ . FIG. 6 shows a comparison of the distances between the localized levels of types 1 to 3. The type 2 is 5 nm and the type 3 is 2 nm, whereas the type 1 is about 50 nm, which is an order of magnitude larger than the types 2 and 3, and the charge barrier effect is larger than the charge accumulation effect.

  FIG. 5 is a diagram showing a band structure of the charge storage type memory of FIG. Trap levels exist in the regions of the first and second charge storage layers 5 and 6, and electrons are stored therein. The currents in the regions of these charge storage layers 5 and 6 become currents that flow through the trap levels. Further, the bottom barrier layer 4 does not have a trap level, and is a Fowler-Nordheim (F-N) tunnel type. In the top barrier layer 7A, although the barrier height is lower than that of the bottom barrier layer 4, since the film thickness is thicker than that of the bottom barrier layer 4, almost no current flows.

With this structure, it is not necessary to switch the charge storage layers 5 and 6 and the top barrier layer 7A to different materials, so that a fine thin film can be controlled and the manufacturing cost can be reduced. Further, since SiO ₂ of the bottom barrier layer 4 can be easily formed by thermal oxidation of the silicon substrate 1, it does not lead to an increase in manufacturing cost.

The charge storage layers 5 and 6 can be produced in the same manner as in Example 1 when produced by the ECR sputtering method described above. The top barrier layer 7A is formed as a film having a stoichiometric composition of Al ₂ O ₃ using the metal region (2) or the oxide region (3) of FIG.

FIG. 7 is a sectional view showing the structure of the charge storage type memory according to the third embodiment. The third embodiment, in a position astride the source 2 and drain 3 of p-type single crystal silicon substrate 1, 1 nm to bottom barrier layer 4A (type 1) of _{Al 2 O 3, Al 2 +} x1 O 3 (x1 > 0) first charge storage layer 5 (type 2) is 10 nm, and Al _{2 + x2} O ₃ (x2> x1) second charge storage layer 6 (type 3) is 0.3 nm (about one atomic layer) ), An Al ₂ O ₃ top barrier layer 7A (type 1) is sequentially laminated by 10 nm, and finally an n-type polysilicon gate electrode 8 is laminated. That is, the third embodiment replaces the top barrier layer 7 in the charge storage type memory of the first embodiment with a top barrier layer 7A of 10 nm Al ₂ O _{3 having} very few localized levels, and also includes a bottom barrier layer 4. This is replaced with a 1 nm Al ₂ O ₃ bottom barrier layer 4A having very few localized levels. As a result, in Example 3, the bottom barrier layer 4A, the charge storage layers 5 and 6, and the top barrier layer 7A can be formed of the same insulator Al ₂ O ₃ .

  FIG. 8 is a diagram showing a band structure of the charge storage type memory of FIG. Trap levels exist in the regions of the first and second charge storage layers 5 and 6, and electrons are stored therein. The currents in the regions of these charge storage layers 5 and 6 become currents that flow through the trap levels. Further, in the bottom barrier layer 4A, there is no trap level, and it becomes a Fowler-Nordheim (F-N) tunnel type. Further, in the top barrier layer 7A, since the film thickness is thicker than that of the bottom barrier layer 4A, almost no current flows.

  With this structure, it is not necessary to switch the bottom barrier layer 4A, the charge storage layers 5 and 6, and the top barrier layer 7A to different materials, so that fine thin film control can be performed and the manufacturing cost can be reduced. It becomes.

The charge storage layers 5 and 6 can be produced in the same manner as in Example 1 when produced by the ECR sputtering method described above. The bottom barrier layer 4A and the top barrier layer 7A are formed by using the metal region (2) or the oxide region (3) in FIG. 18 to form a film having a stoichiometric composition of Al ₂ O ₃ .

The insulating aluminum oxide used in Examples 1 to 3 can be replaced with silicon nitride. In this case, the first charge storage layer 5 has a silicon-rich composition Si _{3 + y1} N ₄ (y1> 0), and the second charge storage layer 6 has a more silicon-rich composition Si _{3 + y2} N ₄ (y2 > Y1), and the top barrier layer 7A and the bottom barrier layer 4A may be made of Si ₃ N ₄ having a stoichiometric composition.

In addition, the aluminum oxide charge storage layers 5 and 6 used in Examples 1 to 3 are made of Al ₂ O ₃ , Si ₃ N ₄ , SiO ₂ or the like as a base material, and there are metal atoms such as tungsten and aluminum, or It is also possible to generate localized levels by doping semiconductor atoms such as silicon and germanium. In these cases, the second charge storage layer 6 is more than the first charge storage layer 5. Increasing the doping density increases the density of localized levels.

  Further, in the first to third embodiments, the single crystal silicon substrate 1 can be replaced with a polycrystalline silicon substrate or an amorphous silicon substrate. In the method for manufacturing the charge storage type memory, the manufacturing method of the charge storage layers 5 and 6 is not limited to a manufacturing method other than the ECR sputtering method and the doping method.

1 is a cross-sectional view illustrating a structure of a charge storage type memory according to a first embodiment. FIG. 3 is an explanatory diagram of a band structure of the charge storage type memory according to the first embodiment. It is a schematic diagram of the spatial position of the localized level of type 2 and type 3 charge storage layers. 6 is a cross-sectional view showing a structure of a charge storage type memory according to Embodiment 2. FIG. 6 is an explanatory diagram of a band structure of a charge storage type memory according to Embodiment 2. FIG. It is a characteristic view of the distance between the localized levels of the type 1, type 2 and type 3 charge storage layers. 6 is a cross-sectional view illustrating a structure of a charge storage type memory according to Embodiment 3. FIG. 6 is an explanatory diagram of a band structure of a charge storage type memory according to Embodiment 3. FIG. FIG. 6 is a characteristic diagram of a distance between localized levels involved in leakage in a conventional example and Example 1. It is a characteristic view of the data retention time of a prior art example and Example 1. It is sectional drawing which shows the structure of the conventional charge storage type memory. It is explanatory drawing of the band structure of the conventional charge storage type memory. FIG. 12 is an explanatory diagram of erasing of the charge storage type memory of FIG. 11. FIG. 12 is an explanatory diagram of writing in the charge storage type memory of FIG. 11. It is a voltage distribution characteristic view of the threshold value of a binary memory cell. FIG. 11 is a voltage distribution characteristic diagram of threshold values of a quaternary memory cell. It is sectional drawing which shows the structure of the ECR sputtering apparatus used for the manufacturing method of the conventional charge storage type memory. It is a characteristic view of the growth rate and refractive index with respect to the oxygen flow rate of the produced aluminum oxide film. It is sectional drawing which shows the structure of the trap memory manufactured by the ECR sputtering apparatus of FIG. FIG. 20 is an explanatory diagram of a band structure of the charge storage type memory of FIG. 19. It is a CV characteristic diagram of a diode of an aluminum oxide film grown under conditions of an oxygen flow rate of 4 sccm. It is a CV characteristic diagram of a diode of an aluminum oxide film grown under an oxygen flow rate of 2 sccm. It is a characteristic view of the time change of the capacitance value of the diode of an aluminum oxide film.

Explanation of symbols

1: p-type single crystal silicon substrate 2: source 3: drain 4, 4A: bottom barrier layer 5: first charge storage layer 6: second charge storage layer 7, 7A: top barrier layer 8: gate electrode 11: p-type single crystal silicon substrate 12: source 13: drain 14: bottom barrier layer 15: charge storage layer 17: top barrier layer 18: gate electrode 21: waveguide 22: coil 23: quartz window 24: coil 25: chamber 26 : Holder 27: Semiconductor substrate 28: Target 29: High-frequency oscillator 30, 31: Gas injection part 32: Electron cyclotron resonance plasma 41: P-type single crystal silicon substrate 44: Bottom barrier layer 45: Charge storage layer 47: Top barrier layer 48 : Gate electrode

Claims (9)

A semiconductor substrate; a bottom barrier layer deposited on the top surface of the semiconductor substrate; a charge storage layer deposited on the top surface of the bottom barrier layer; a top barrier layer deposited on the top surface of the charge storage layer and thicker than the bottom barrier layer; A charge storage type memory having a gate electrode formed on the upper surface of the top barrier layer and changing a threshold value depending on whether electrons are stored in the charge storage layer;
The charge storage layer is composed of a first charge storage layer located on the bottom barrier layer side and a plurality of elements located on the top barrier layer side and the same as the first charge storage layer, 2. A charge storage type memory having a two-layer structure including a second charge storage layer having a localized level density higher than that of the first charge storage layer. The charge storage type memory according to claim 1,
The bottom barrier layer and the top barrier layer are silicon oxide;
The charge storage memory according to claim 1, wherein the charge storage layer is formed by excessively containing metal atoms or semiconductor atoms in any one of silicon nitride, aluminum oxide, and silicon oxide to generate localized levels. The charge storage type memory according to claim 1,
The charge storage layer and the top barrier layer are made of the same insulator,
The top barrier layer comprises a stoichiometric insulator,
The first charge storage layer has a stoichiometrically excessive amount of metal atoms or semiconductor atoms, which are elements constituting the insulator, and has a localized level of the metal atoms or the semiconductor atoms. So that the electrons accumulate in the level,
In the second charge storage layer, metal atoms or semiconductor atoms that are elements constituting the insulator are stoichiometrically present in an excessive amount more than the first charge storage layer, and the metal atoms or the semiconductor atoms A charge storage type memory characterized by having a localized level and storing electrons in the localized level. The charge storage type memory according to claim 1,
The bottom barrier layer, the charge storage layer and the top barrier layer are made of the same insulator,
The bottom barrier layer and the top barrier layer are made of an insulator having a stoichiometric composition,
The first charge storage layer has a stoichiometrically excessive amount of metal atoms or semiconductor atoms, which are elements constituting the insulator, and has a localized level of the metal atoms or the semiconductor atoms. So that the electrons accumulate in the level,
In the second charge storage layer, metal atoms or semiconductor atoms that are elements constituting the insulator are stoichiometrically present in an excessive amount more than the first charge storage layer, and the metal atoms or the semiconductor atoms A charge storage type memory characterized by having a localized level and storing electrons in the localized level. The charge storage type memory according to claim 3 or 4,
A charge storage type memory using aluminum oxide as the insulator and aluminum atoms as the metal atoms present in the charge storage layer. The charge storage type memory according to claim 3 or 4,
A charge storage type memory using silicon nitride as the insulator and silicon atoms as the semiconductor atoms present in the charge storage layer. The charge storage type memory according to any one of claims 1 to 6,
2. The charge storage memory according to claim 1, wherein the semiconductor substrate is a single crystal silicon substrate, a polycrystalline silicon substrate, or an amorphous silicon substrate. A method for manufacturing the charge storage type memory according to claim 3, comprising:
Electron cyclotron resonance type plasma generating means, gas supply means for supplying a rare gas and oxygen gas to the plasma generating means, a target made of aluminum installed in the plasma generating means, and installed in the plasma generating means Using a sputtering means having at least a semiconductor substrate and a high-frequency power application means to the target,
At the time of forming the first charge storage layer, the refractive index of Al ₂ O _{3 in which} the refractive index of aluminum oxide deposited on the semiconductor substrate by sputtering is the stoichiometric composition of the aluminum oxide is formed by using the oxygen gas. A first supply amount with a higher refractive index than
When the second charge storage layer is formed, oxygen gas is used to form a first refractive index of aluminum oxide deposited on the semiconductor substrate by sputtering so that the refractive index is higher than the refractive index of the first charge storage layer. 2 supply amount,
At the time of forming the top barrier layer, the oxygen gas is deposited on the semiconductor substrate by sputtering so that the refractive index of the aluminum oxide becomes the refractive index of Al ₂ O ₃ which is the stoichiometric composition of the aluminum oxide. 3 supply amount,
A method for manufacturing a charge storage type memory. A method of manufacturing the charge storage type memory according to claim 4, comprising:
Electron cyclotron resonance type plasma generating means, gas supply means for supplying a rare gas and oxygen gas to the plasma generating means, a target made of aluminum installed in the plasma generating means, and installed in the plasma generating means Using a sputtering means having at least a semiconductor substrate and a high-frequency power application means to the target,
At the time of forming the first charge storage layer, the refractive index of Al ₂ O _{3 in which} the refractive index of aluminum oxide deposited on the semiconductor substrate by sputtering is the stoichiometric composition of the aluminum oxide is formed by using the oxygen gas. A first supply amount with a higher refractive index than
When the second charge storage layer is formed, oxygen gas is used to form a first refractive index of aluminum oxide deposited on the semiconductor substrate by sputtering so that the refractive index is higher than the refractive index of the first charge storage layer. 2 supply amount,
At the time of forming the bottom barrier layer and the top barrier layer, the oxygen gas is sputtered with Al ₂ O ₃ whose refractive index of aluminum oxide deposited on the semiconductor substrate by sputtering is the stoichiometric composition of the aluminum oxide. A third supply amount that becomes a refractive index is used.
A method for manufacturing a charge storage type memory.

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