JP2005295254A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor device provided with an input circuit having a simple circuit configuration and capable of corresponding to input voltage specifications for a plurality of power supply voltages.
A semiconductor device includes an input circuit and an internal power generation circuit. The internal power supply generation circuit 2 outputs the external power supply Vex as the internal power supply Vint when the external power supply Vext supplied from the external terminal is equal to or lower than a predetermined value, and performs a step-down operation when the voltage is equal to or higher than the predetermined value, from the external power supply Vext. The internal power source Vint having a constant voltage is output at a low voltage. The internal power supply Vint output from the internal power supply generation circuit 2 is input to the input circuit 1 as the high potential side power supply Vdd. The input circuit 1 inputs the external power source Vext and the high potential side power source Vdd as power sources, inputs the input signal IN, and outputs a signal satisfying a plurality of input voltage specifications corresponding to the power source voltage.
[Selection] Figure 1

Description

  The present invention relates to an input circuit used in a semiconductor integrated circuit (hereinafter referred to as LSI), and more particularly to a semiconductor device provided with an input circuit that can handle input voltage specifications for a plurality of power supply voltages.

  In recent years, miniaturization of semiconductor elements constituting an LSI has progressed, and the breakdown voltage has been lowered with an increase in operating speed. In response to a decrease in the breakdown voltage of the semiconductor element, an optimum voltage is supplied from an external power supply or an internal power supply provided inside the LSI in order to perform an optimum operation of the semiconductor element for each generation of miniaturization. On the other hand, in order to meet the demand for low power consumption of portable electronic information devices such as notebook computers and PDAs, and portable electronic media devices such as digital cameras, the voltage of the battery used as a power source decreases and the types of batteries increase. ing.

  In accordance with the increase in voltage conditions of these power supplies, the input / output interface specifications of digitally operating LSIs have increased, for example, 5V, 3V, 1.8V, and the like. The input / output interface specifications vary in logic amplitude, maximum voltage, minimum voltage, and the like depending on the power supply voltage condition, and it is difficult to satisfy a plurality of input interface specifications with one input circuit, for example. For this reason, a plurality of input circuits are provided, and semiconductor devices corresponding to a plurality of input interface specifications are used by appropriately using them.

  As this type of semiconductor device, one shown in FIG. 10 is known (for example, see Patent Document 1). FIG. 10 is a block diagram illustrating a semiconductor device.

  As shown in FIG. 10, the semiconductor device disclosed in Patent Document 1 includes input circuits 101 and 102, a selection circuit 103, and a power supply voltage detection circuit 4. Here, the input circuit 101 can satisfy the input interface specification at a power supply voltage of 5V, and the input circuit 102 can satisfy the input interface specification at a power supply voltage of 3V.

  The input circuits 101 and 102 input an output signal output from the outside as an input signal IN via an external terminal, perform a logical operation, and output the output signal to the selection circuit 103. Based on the power supply voltage condition detected by the power supply voltage detection circuit 104, the selection circuit 103 outputs the output signal of the input circuit 101 when the power supply voltage is 5V and the output signal of the input circuit 102 when the power supply voltage is 3V. Each is selected and the output signal OUT is output to an internal circuit composed of, for example, a digital LSI.

In the semiconductor device described above, two input circuits are switched and used in order to satisfy the input voltage specification corresponding to the two power supply voltages. For this reason, a current flows through two input circuits, and there is a problem that current consumption is larger than in the case of one input circuit. In addition, there are problems that the circuit pattern area becomes large and a plurality of input circuits must be designed.
JP-A-6-295580 (page 3, FIG. 1)

  The present invention provides a semiconductor device including an input circuit that has a simple circuit configuration and can support input voltage specifications for a plurality of power supply voltages.

  In order to achieve the above object, in a semiconductor device of one embodiment of the present invention, when an external power supply voltage is applied and the external power supply voltage is equal to or lower than a predetermined value, the external power supply voltage is higher than a predetermined value. In this case, an internal power generation circuit that steps down and outputs an internal power supply voltage lower than the external power supply voltage as a high potential side power supply voltage, and the external power supply voltage is applied and the power supply voltage is adjusted to the external power supply side And an input circuit having a first stage provided with voltage adjusting means and a buffer stage to which the high-potential-side power supply voltage is applied.

  Furthermore, in order to achieve the above object, a semiconductor device according to another aspect of the present invention includes a first internal power supply voltage to which an external power supply voltage is applied, and the first internal power supply voltage lower than the external power supply voltage is stepped down and output. And a second internal power generation circuit to which the external power supply voltage is applied and stepped down to output a second internal power supply voltage that is lower than the external power supply voltage and higher than the first internal power supply voltage When the first internal power supply voltage and the second internal power supply voltage are input and the external power supply voltage is less than or equal to a predetermined value, the first internal power supply voltage is greater than the predetermined value. In this case, the selection circuit for outputting the second internal power supply voltage as the high-potential-side power supply voltage and the first stage provided with the voltage adjusting means for adjusting the power supply voltage to the external power supply side when the external power supply voltage is applied. And the high potential side power supply And an input circuit having a buffer stage to which pressure is applied.

  According to the present invention, it is possible to provide a semiconductor device including an input circuit that has a simple circuit configuration and can support input voltage specifications for a plurality of power supply voltages.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a semiconductor device, and FIG. 2 is a diagram illustrating a relationship between an external power source supplied to an input circuit and a high potential side power source.

  As shown in FIG. 1, the semiconductor device of this embodiment includes an input circuit 1 and an internal power generation circuit 2. The internal power supply generation circuit 2 (first internal power supply generation circuit) uses the external power supply Vex as the internal power supply Vint (first internal power supply) when the external power supply Vext supplied from the external terminal is a predetermined value or less, for example, 2 V or less. ), And operates as a limiter circuit that generates an internal power supply Vint having a constant voltage at a voltage lower than the external power supply Vext when the voltage exceeds a predetermined value. The internal power supply Vint output from the internal power supply generation circuit 2 is input to the input circuit 1 as the high potential side power supply Vdd.

  The input circuit 1 inputs an external power source Vext and a high potential side power source Vdd as power sources, and inputs an output signal output from an external device or another LSI as an input signal IN via an external terminal, and performs waveform shaping. A signal that satisfies the input voltage specification corresponding to the power supply voltage is output to the internal circuit 3. Here, the internal circuit 3 includes various circuits used for memories such as SRAM (static random access memory), DRAM (dynamic random access memory), ROM (read only memory), MPU (micro processor unit), FPU (floating− Various circuits used for logic such as point processing units) or various circuits used for SoC (system on a chip).

  As shown in FIG. 2, the high-potential-side power supply Vdd increases linearly because the external power supply Vext is used in the region where the external power supply Vext is in the standard of the power supply voltage 1.8V (± 10%). On the other hand, in the region of the power supply voltage standard 3V (± 10%) which is the TTL interface specification, the internal power generation circuit 2 steps down the voltage to 2V which is a constant voltage.

  Next, the circuit configuration of the input circuit and its input voltage characteristics will be described with reference to FIGS. FIG. 3 is a circuit diagram of the input circuit, and FIG. 4 is a diagram showing input voltage characteristics with respect to the external power supply voltage of the input circuit. Here, the voltage for selecting the internal power supply Vint is a region of 2 V or more.

  As shown in FIG. 3, the input circuit 1 includes an initial stage unit 11 that determines an input signal level and a buffer stage unit 12 that outputs an appropriate voltage as an output signal. The first stage unit 11 includes a two-input NAND circuit NAND1 and a D-type NchMOS transistor (also referred to as a normally-on NchMOS transistor) ND1. Here, the Pch MOS transistor and the Nch MOS transistor other than the D type Nch MOS transistor ND1 constituting the input circuit 1 are E type (also referred to as normally-off type) MOS transistors.

  The D-type NchMOS transistor ND1 is provided between the external power supply Vext and the source of the PchMOS transistor P1, and functions as a voltage adjusting unit that adjusts the power supply voltage of the NAND circuit NAND1. The NAND circuit NAND1 is provided between the source of the D-type NchMOS transistor ND1 and the low-potential-side power supply Vss, and between the drains of the PchMOS transistor P1, the PchMOS transistor P2, the NchMOS transistor N1, the PchMOS transistor P2, and the NchMOS transistor N1. It is composed of an Nch MOS transistor N2 between the low potential side power supply Vss.

  In the D type NchMOS transistor ND1, the drain is connected to the external power supply Vext, the gate is connected to the high potential power supply Vdd, and the drain current increases with the increase of the external power supply Vext in the region of the power supply voltage 1.8V (± 10%) standard. Increases, and a constant drain current flows in a region where the power supply voltage is 3 V (± 10%). Therefore, the power supply potential supplied to the 2-input NAND circuit is adjusted by the D-type NchMOS transistor ND1.

  The source of the PchMOS transistor P1 is connected to the source of the D-type NchMOS transistor ND1, and the chip enable signal CEB is input to the gate. The source of the PchMOS transistor P2 is connected to the drain of the PchMOS transistor P1, and the input signal IN is input to the gate. The NchMOS transistor N1 has a drain connected to the drain of the PchMOS transistor P2, and receives an input signal IN at the gate. The Pch MOS transistor P2 and the Nch MOS transistor N1 perform an inverter operation. The NchMOS transistor N2 has a drain connected to the output side of the inverter composed of the PchMOS transistor P2 and the NchMOS transistor N1, a source connected to the low potential side power supply, and a chip enable signal CEB input to the gate.

  The buffer stage unit 12 includes an inverter INV1. The inverter INV1 receives the signal output from the first stage unit 11 using the high-potential-side power supply Vdd as a power supply, operates as an inverter, and outputs the output signal Out of the input circuit 1.

  As shown in FIG. 4, the input voltage specification for the region of the power supply voltage 3 V (± 10%) is not more than HS1 that is a high level input voltage and not less than LS1 that is a low level input voltage. On the other hand, the high level input voltage characteristic VH1 is equal to or lower than HS1, and the low level input voltage characteristic VL1 is equal to or higher than LS1, each sufficiently satisfying the standard. On the other hand, the input voltage specification for the region of the power supply voltage 1.8V (± 10%) is not more than HS2 which is a high level input voltage and not less than LS2 which is a low level input voltage. On the other hand, the high level input voltage characteristic VH2 is equal to or lower than HS2, and the low level input voltage characteristic VL2 is equal to or higher than LS2, each sufficiently satisfying the standard.

  As described above, in the semiconductor device of this embodiment, the external power source Vex is output as the internal power source Vint when the external power source Vext supplied from the external terminal is equal to or lower than a predetermined value, and the step-down operation is performed when the voltage is equal to or higher than the predetermined value. The internal power generation circuit 2 that outputs a constant voltage at a lower voltage than the external power supply Vext, and the internal power output Vext supplied from the internal power generation circuit 2 to the buffer stage 12 are supplied to the first stage 11. And an input circuit 1 for supplying the power source Vint as the high potential side power source Vdd. The power supply potential supplied to the NAND circuit NAND1 in the first stage 11 is adjusted by the D-type NchMOS transistor ND1. Therefore, the input voltage characteristics can be satisfied with respect to the input voltage specifications for the two power supply voltages. Moreover, since the input voltage specification for two power supply voltages can be handled with one input circuit, current consumption can be suppressed as compared with the conventional case. Furthermore, since an input circuit having a simple circuit configuration is used, design work can be reduced.

In this embodiment, the input circuit 1 has a two-stage configuration of the first stage section 11 and the buffer stage section 12, but a waveform shaping circuit, an inverter, and the like are provided between the first stage section 11 and the buffer stage section 12 to provide three stages. It may be more than the configuration. Further, a NOR circuit or the like may be used instead of the NAND circuit. Further, although a silicon oxide film is used as the gate insulating film of the PchMOS transistor and the NchMOS transistor, a SiNxOy film obtained by nitriding the silicon oxide film, a silicon nitride film (Si ₃ N ₄ ) / silicon oxide film laminated film, or a high film A dielectric film (High-K gate insulating film) may be used. As this high dielectric film, an oxide of Hf (hafnium), Zr (zirconium), La (lanthanum), or a silicate thereof (for example, HfSiON) may be used.

  Next, a semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing the semiconductor device, and FIG. 6 is a diagram showing the relationship between the external power source supplied to the input circuit and the high potential side power source. In this embodiment, the internal power supply supplied to the input circuit is increased.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 5, the semiconductor device of this embodiment includes an input circuit 1, internal power generation circuits 2, 2 a, and a selection circuit 4. The internal power generation circuit 2a (second internal power generation circuit) performs a step-down operation when the external power supply Vext is higher than the voltage in the first embodiment, and is lower than the external power supply Vext and higher than the internal power supply Vint. As a voltage, an internal power supply Vanta (second internal power supply) having a constant voltage is generated, and the internal power supply Vanta is output to the selection circuit 4. The selection circuit 4 inputs the internal power supply Vint output from the internal power supply generation circuit 2 and the Vint output from the internal power supply generation circuit 2a. When the external power supply Vext is equal to or lower than the voltage in the first embodiment, the selection circuit 4 selects the internal power supply Vint. When the external power supply Vext is higher than that of the first embodiment, the internal power supply Vanta is selected and output to the input circuit 1 as the high potential side power supply Vdd.

  As shown in FIG. 6, in the region of the power supply voltage 5V (± 10%) standard that is the TTL interface specification, the high-potential-side power supply is stepped down to 2.4V, which is a constant voltage, by the internal power supply generation circuit 2a.

  Next, input voltage characteristics of the input circuit will be described with reference to FIG. FIG. 7 is a diagram showing the input voltage characteristics with respect to the external power supply voltage of the input circuit.

  As shown in FIG. 7, the input voltage specification for the region of the power supply voltage of 5 V (± 10%) is HS3 or less which is a high level input voltage and LS3 or more which is a low level input voltage. On the other hand, the high level input voltage characteristic VH3 is equal to or lower than HS3, and the low level input voltage characteristic VL3 is equal to or higher than LS3, which sufficiently satisfy the standards.

  As described above, in the semiconductor device of this embodiment, the external power source Vex is output as the internal power source Vint when the external power source Vext supplied from the external terminal is equal to or lower than a predetermined value, and the step-down operation is performed when the voltage is equal to or higher than the predetermined value. When the internal power generation circuit 2 outputs a constant voltage at a voltage lower than that of the external power supply Vext, and when the external power supply Vext is higher than the voltage in the first embodiment, the operation is stepped down to a voltage lower than that of the external power supply Vext. In addition, the internal power generation circuit 2a that generates the internal power supply Vta having a constant voltage that is higher than the internal power supply Vint, the internal power supply Vint that is output from the internal power generation circuit 2, and the internal power generation circuit 2a When Vtata is input and the external power supply Vext is equal to or lower than the voltage in the first embodiment, the internal power supply Vint is selected, and the external power supply Vext is higher than that in the first embodiment. In this case, the internal power supply Vta is selected, the selection circuit 4 that outputs the high-potential-side power supply Vdd to the input circuit 1, the external power supply Vext is supplied to the first stage unit 11, and the selection circuit 4 outputs the buffer stage unit 12. And an input circuit 1 to which a high potential side power supply Vdd is input. The power supply potential supplied to the NAND circuit NAND1 in the first stage 11 is adjusted by the D-type NchMOS transistor ND1. Therefore, the input voltage characteristics can be satisfied with respect to the input voltage specifications for the three power supply voltages. In addition, since the input voltage specifications for the three power supply voltages can be handled with one input circuit, the current consumption can be suppressed as compared with the conventional case. Furthermore, since an input circuit having a simple circuit configuration is used, design work can be reduced.

  Next, a semiconductor device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 8 is a circuit diagram showing the input circuit. In the present embodiment, the circuit configuration of the first stage of the input circuit of the first embodiment is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 8, the input circuit 1 a includes a first stage part 11 a and a buffer stage part 12. The first stage portion 11a includes a two-input NAND circuit NAND1, a Pch MOS transistor P3 (second Pch MOS transistor), a Pch MOS transistor (first Pch MOS transistor) P4, and an Nch MOS transistor N3. The Pch MOS transistor P3, the Pch MOS transistor P4, and the Nch MOS transistor N3 function as voltage adjusting means for adjusting the power supply voltage of the 2-input NAND circuit NAND1.

  The PchMOS transistor P3 is provided between the external power supply Vext and the source of the PchMOS transistor P1 of the two-input NAND circuit NAND1, and the PchMOS transistor P4 and the NchMOS transistor N3 are provided between the external power supply Vext and the low potential side power supply Vss. Yes.

  The PchMOS transistor P4 has a source connected to the external power supply Vext and a gate connected to the low potential power supply Vss, and is always on. The NchMOS transistor N3 has a drain connected to the drain of the PchMOS transistor P4, a source connected to the low potential side power supply Vss, a gate connected to the high potential side power supply Vdd, and a power supply voltage of 1.8 V (± 10%) standard. In the region, the drain current increases as the external power supply Vext increases, and a constant drain current flows in the region of the power supply voltage 3V (± 10%) standard.

  The PchMOS transistor P3 has a source connected to the external power supply Vext, a drain connected to the source of the PchMOS transistor P1, a gate connected to the drain of the PchMOS transistor P4 and the drain of the NchMOS transistor N3, and the potential of the drain of the PchMOS transistor P4. The drain current changes. Therefore, the power supply potential supplied to the two-input NAND circuit NAND1 is adjusted by the operations of the Pch MOS transistors P3 and P4 and the Nch MOS transistor N3.

  Next, input voltage characteristics of the input circuit will be described with reference to FIG. FIG. 9 is a diagram showing input voltage characteristics with respect to the external power supply voltage of the input circuit.

  As shown in FIG. 9, the input voltage specification for the region of the power supply voltage 3V (± 10%) is not more than HS1 that is a high level input voltage and not less than LS1 that is a low level input voltage. On the other hand, the high level input voltage characteristic VH11 is equal to or lower than HS1, and the low level input voltage characteristic VL11 is equal to or higher than LS1, each sufficiently satisfying the standard. On the other hand, the input voltage specification for the region of the power supply voltage 1.8V (± 10%) is not more than HS2 which is a high level input voltage and not less than LS2 which is a low level input voltage. On the other hand, the high-level input voltage characteristic VH21 is equal to or lower than HS2, and the low-level input voltage characteristic VL21 is equal to or higher than LS2, each sufficiently satisfying the standard.

  As described above, in the semiconductor device of this embodiment, the external power source Vex is output as the internal power source Vint when the external power source Vext supplied from the external terminal is equal to or lower than a predetermined value, and the step-down operation is performed when the voltage is equal to or higher than the predetermined value. The internal power generation circuit 2 that outputs a constant voltage at a lower voltage than the external power supply Vext, and the internal power supply Vext supplied from the internal power generation circuit 2 to the buffer stage 12 are supplied to the first stage 11a. And an input circuit 1a for supplying the power source Vint as the high potential side power source Vdd. The power supply potential supplied to the NAND circuit NAND1 of the first stage unit 11a is adjusted by the operations of the Pch MOS transistors P3 and P4 and the Nch MOS transistor N3. For this reason, it has the same effect as Example 1.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the third embodiment, the power supply potential supplied to the two-input NAND circuit NAND1 of the first stage unit 11a is adjusted using the Pch MOS transistors P3 and P4 and the Nch MOS transistor N3, but a current mirror circuit may be used instead. . The first and third embodiments correspond to the input voltage specifications for the power supply voltages 1.8V and 3V, and the second embodiment corresponds to the input voltage specifications for the power supply voltages 1.8V, 3V and 5V. The input voltage specification can be adapted by adjusting the circuit parameters.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) When an external power supply voltage is applied and the external power supply voltage is less than or equal to a predetermined value, the external power supply voltage is stepped down when the external power supply voltage is greater than or equal to a predetermined value and lower than the external power supply voltage. An internal power generation circuit that outputs a power supply voltage as a high-potential-side power supply voltage, a voltage to which the external power supply voltage is applied, a NAND circuit is provided, and a power supply voltage is adjusted between the external power supply side and the NAND circuit A semiconductor device comprising: an input circuit having a first stage provided with adjusting means and a buffer stage to which the high-potential side power supply voltage is applied and an inverter is provided.

(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the voltage adjusting means is a normally-on NchMOS transistor having a drain connected to the external power supply and a gate connected to the high potential power supply.

(Supplementary Note 3) The voltage adjusting means includes a first PchMOS transistor having a source connected to the external power supply, a gate connected to a low potential power supply, and a drain connected to the drain of the first PchMOS transistor, An NchMOS transistor having a gate connected to the high-potential side power supply, a source connected to the external power supply, a source connected to the low-potential side power supply, and a gate being the drain of the first PchMOS transistor and the drain of the NchMOS transistor The semiconductor device according to appendix 1, wherein the semiconductor device includes a second PchMOS transistor connected to the first PchMOS transistor.

(Additional remark 4) The said voltage adjustment means is a semiconductor device of Additional remark 1 which is a current mirror circuit provided between the said external power supply and the said NAND circuit.

1 is a block diagram showing a semiconductor device according to Embodiment 1 of the present invention. The figure which shows the relationship between the external power supply supplied to the input circuit which concerns on Example 1 of this invention, and a high potential side power supply. 1 is a circuit diagram showing an input circuit according to Embodiment 1 of the present invention. The figure which shows the input voltage characteristic with respect to the external power supply voltage of the input circuit which concerns on Example 1 of this invention. FIG. 6 is a block diagram illustrating a semiconductor device according to a second embodiment of the invention. The figure which shows the relationship between the external power supply supplied to the input circuit which concerns on Example 2 of this invention, and a high potential side power supply. The figure which shows the input voltage characteristic with respect to the external power supply voltage of the input circuit which concerns on Example 2 of this invention. FIG. 6 is a circuit diagram illustrating an input circuit according to a third embodiment of the invention. The figure which shows the input voltage characteristic with respect to the external power supply voltage of the input circuit which concerns on Example 3 of this invention. The block diagram which shows the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1a Input circuit 2, 2a Internal power generation circuit 3 Internal circuit 4 Selection circuit 11, 11a First stage part 12 Buffer stage part CEB Chip enable signal HS1 VIH voltage specification with power supply voltage 3V HS2 VIH voltage with power supply voltage 1.8V Specification HS3 VIH voltage specification IN with 5V power supply voltage IN Input signal INV1 Inverter LS1 VIL voltage specification with 3V power supply voltage LS2 VIL voltage specification with 1.8V power supply voltage LS3 VIL voltage specification with 5V power supply voltage NAND1 NAND circuits N1, N2 , N3 NchMOS transistor ND1 D type NchMOS transistor OUT Output signals P1, P2, P3, P4 PchMOS transistor Vdd High potential side power source Vext External power source VH1, VH11 VIH voltage characteristics VH2 at power source voltage 3V, VH21 VH21 at power source voltage 1.8V IH voltage characteristics VH3 VIH voltage characteristics Vint, Vanta internal power supply VL1, VL11 VIL voltage characteristics VL2 at VL11 power supply voltage 3V, VL21 VIL voltage characteristics VL3 at power supply voltage 1.8V VIL voltage characteristics at power supply voltage 5V Vss Low potential side power supply

Claims (5)

When an external power supply voltage is applied and the external power supply voltage is a predetermined value or less, the external power supply voltage is reduced, and when the external power supply voltage is a predetermined value or more, the internal power supply voltage lower than the external power supply voltage is reduced. An internal power generation circuit that outputs as a high-potential side power supply voltage,
An input circuit having an initial stage portion provided with voltage adjusting means for adjusting the power supply voltage on the external power supply side to which the external power supply voltage is applied, and a buffer stage portion to which the high potential side power supply voltage is applied;
A semiconductor device comprising: A first internal power generation circuit to which an external power supply voltage is applied, steps down and outputs a first internal power supply voltage lower than the external power supply voltage;
A second internal power supply generating circuit that applies the external power supply voltage, steps down and outputs a second internal power supply voltage that is lower than the external power supply voltage and higher than the first internal power supply voltage;
When the first internal power supply voltage and the second internal power supply voltage are input and the external power supply voltage is less than or equal to a predetermined value, the first internal power supply voltage is greater than the predetermined value. A selection circuit for outputting the second internal power supply voltage as a high-potential-side power supply voltage,
An input circuit having an initial stage portion provided with voltage adjusting means for adjusting the power supply voltage on the external power supply side to which the external power supply voltage is applied, and a buffer stage portion to which the high potential side power supply voltage is applied;
A semiconductor device comprising: When an external power supply voltage is applied and the external power supply voltage is less than or equal to a predetermined value, the external power supply is stepped down and the first internal power supply voltage lower than the external power supply voltage when the external power supply voltage is greater than or equal to a predetermined value. A first internal power generation circuit that outputs
A second internal power generation circuit that is applied with the external power supply voltage, steps down and outputs a second internal power supply voltage that is lower than the external power supply voltage and higher than the first internal power supply voltage;
When the first internal power supply voltage and the second internal power supply voltage are input and the external power supply voltage is less than or equal to a predetermined value, the external power supply voltage is greater than or equal to a predetermined value and the second When the external power supply voltage is lower than the first internal power supply voltage, the second internal power supply voltage is set as the high potential side power supply voltage. A selection circuit to output,
An input circuit having an initial stage portion provided with voltage adjusting means for adjusting the power supply voltage on the external power supply side to which the external power supply voltage is applied; and a buffer stage portion to which the high potential side power supply voltage is applied;
A semiconductor device comprising:   4. The voltage adjustment unit is a normally-on NchMOS transistor having a drain connected to the external power supply and a gate connected to the high-potential-side power supply. 5. Semiconductor device.   The voltage adjusting means includes a first PchMOS transistor having a source connected to the external power supply and a gate connected to a low potential side power supply, a drain connected to the drain of the first PchMOS transistor, and a gate connected to the high power supply. An NchMOS transistor connected to the potential side power supply, a source connected to the low potential side power supply, a source connected to the external power supply, and a gate connected to the drain of the first PchMOS transistor and the drain of the NchMOS transistor. 4. The semiconductor device according to claim 1, wherein the semiconductor device comprises a second PchMOS transistor.

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