JP2005286091A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the conventional problem that a manufacturing cost is high and an adhesive remains when a pressure sensitive adhesive sheet for semiconductor wafer protection is formed and stuck on a semiconductor wafer, in order to prevent the warpage of the semiconductor wafer under heating environment of a process for forming an element on the semiconductor wafer. <P>SOLUTION: A warpage preventing layer 16 which consists of e.g. a silicon nitride film is formed on the back of the semiconductor wafer 41 in the former stage of a process for depositing a metallization layer which constitutes a wiring layer. As a result, a multilayer wiring layer is formed in a state that the semiconductor wafer 41 is previously curved in a reverse direction in which warpage is generated by the wiring layers. By the above method, although the semiconductor wafer 41 is curved by formation of the wiring layers, an amount of warpage X can be reduced sharply. In an exposure device, the semiconductor wafer 41 is sucked certainly and can be fixed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  An object of the present invention is to reduce warping of a semiconductor wafer during a semiconductor element formation process.

  In recent years, semiconductor wafers are becoming larger and thinner for IC cards and the like. However, semiconductor wafers that have been increased in size and reduced in thickness are easily damaged due to warpage caused by the heat in a heating environment such as an aluminum (Al) layer as a wiring layer. In the exposure process, the edge of the semiconductor wafer is sucked and the semiconductor wafer is fixed, and then the exposure operation is performed. However, due to the warping of the semiconductor wafer, the wafer cannot be sucked and the exposure cannot be performed. It was.

Therefore, in a conventional method for manufacturing a semiconductor device, for example, a pressure-sensitive adhesive solution is applied to the surface of a base film and dried (heat-crosslinked as necessary) to form a pressure-sensitive adhesive layer. And the adhesive sheet for semiconductor wafer protection was created by bonding a separator on the surface of this adhesive layer as needed. Then, there existed a technique which affixed this adhesive sheet for semiconductor wafer protection to a semiconductor wafer, and prevented warping of a semiconductor wafer etc. (for example, refer patent document 1).
Japanese Patent Laid-Open No. 03-206671 (page 2, pages 8-11, Fig. 1-2)

  As described above, in the conventional method for manufacturing a semiconductor device, in order to prevent warpage of the semiconductor wafer in a heating environment in the process of forming elements on the semiconductor wafer, an adhesive sheet for protecting the semiconductor wafer is prepared, I was pasting them together. However, there is a problem in that the production of the pressure-sensitive adhesive sheet for protecting a semiconductor wafer increases the cost. In addition, there is a problem that an extra step of attaching a pressure-sensitive adhesive sheet for protecting a semiconductor wafer and peeling the pressure-sensitive adhesive sheet occurs.

  Further, in the conventional method for manufacturing a semiconductor device, the adhesive may remain on the back surface of the semiconductor wafer after the adhesive sheet for protecting the semiconductor wafer is peeled off. For example, when the back electrode is formed, a process for removing the remaining pressure-sensitive adhesive is required, which increases the number of processes and causes a problem in cost.

  The present invention has been made in view of the above-described circumstances, and in the method for manufacturing a semiconductor device of the present invention, a first main surface serving as a semiconductor element formation region and a second main surface that forms a pair with the first main surface. A warp prevention layer is provided on the second main surface to warp the semiconductor wafer so that at least the first main surface has a convex curve with respect to the first main surface. The warpage preventing layer is removed after forming at least two wiring layers from the surface side. Therefore, in the present invention, the warp prevention layer is formed on the second main surface of the semiconductor wafer, thereby causing the semiconductor wafer to warp upward with respect to the first main surface. As a result, when a metal layer forming a wiring layer is deposited on the first main surface and cured, the semiconductor wafer is warped in a downward convex curve with respect to the first main surface. The amount of warpage can be reduced.

  The method for manufacturing a semiconductor device according to the present invention is characterized in that the warpage preventing layer is formed on the first main surface before depositing a metal layer to be the wiring layer. Therefore, in the present invention, before the warp that draws a downward convex curve with respect to the first main surface of the semiconductor wafer occurs, the upward warp is generated in advance with respect to the first main surface of the semiconductor wafer. be able to.

  In the method of manufacturing a semiconductor device according to the present invention, the semiconductor wafer is placed in an exposure apparatus in a state where a metal layer to be the wiring layer is deposited and the warp preventing layer is formed on the second main surface. It is characterized by. Therefore, in the present invention, the metal layer exposure process is performed in a state in which the warp preventing layer is formed on the second main surface of the semiconductor wafer. Therefore, the amount of warpage of the semiconductor wafer is reduced, and the exposure apparatus reliably secures the semiconductor wafer. Can be fixed.

  In the method for manufacturing a semiconductor device of the present invention, a warp preventing layer is formed on the second main surface of the semiconductor wafer. As a result, the amount of the semiconductor wafer that warps so as to draw a downwardly convex curve with respect to the first main surface can be reduced by curing the metal layer constituting the wiring layer.

  In the method for manufacturing a semiconductor device of the present invention, a warp preventing layer is formed in advance on the second main surface of the semiconductor wafer before the wiring layer is formed. Thereby, the hardening of the metal layer constituting the wiring layer can counter the force that the semiconductor wafer warps so as to draw a downwardly convex curve with respect to the first main surface.

  In the semiconductor device manufacturing method of the present invention, the semiconductor wafer is placed on the exposure apparatus in a state in which the warp preventing layer is formed on the second main surface of the semiconductor wafer. As a result, the exposure apparatus can securely fix the semiconductor wafer against warping of the semiconductor wafer.

  Below, the manufacturing method of the semiconductor device which is one embodiment of this invention is demonstrated in detail with reference to FIGS.

  1 to 9 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the present embodiment. In the following description, for example, an N-channel MOS transistor is formed in one element formation region, but the present invention is not limited to this case. For example, an NPN transistor, a lateral PNP transistor, or the like may be formed in another element formation region to form a semiconductor integrated circuit device.

First, as shown in FIG. 1, a P-type single crystal silicon substrate 1 is prepared. The illustrated substrate 1 shows a part of a semiconductor wafer, and the same applies to the following description. The surface of the substrate 1 is thermally oxidized to form a silicon oxide film on the entire surface, for example, about 0.03 to 0.05 μm. Thereafter, a photoresist having an opening in a portion where the N-type buried layer 2 is formed is formed as a selection mask by a known photolithography technique. Then, an N-type impurity such as phosphorus (P) is ion-implanted at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

Next, as shown in FIG. 2, using the silicon oxide film formed in FIG. 1, a photoresist having an opening in a portion where the first isolation region 3 is formed is selected by a known photolithography technique. Form as. Then, a P-type impurity, for example, boron (B) is ion-implanted at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

Next, as shown in FIG. 3, all of the silicon oxide film formed in FIG. 2 is removed, and the substrate 1 is placed on the susceptor of the epitaxial growth apparatus. Then, a high temperature of, for example, about 1200 ° C. is given to the substrate 1 by lamp heating, and SiHCl ₃ gas and H ₂ gas are introduced into the reaction tube. As a result, an epitaxial layer 4 having a specific resistance of 0.1 to 3.5 Ω · cm and a thickness of about 1.0 to 6.0 μm is grown on the substrate 1. Thereafter, the surface of the epitaxial layer 4 is thermally oxidized to form a silicon oxide film of about 0.03 to 0.05 μm, for example. Thereafter, a photoresist having an opening in a portion where the second isolation region 5 is formed is formed as a selection mask by a known photolithography technique. Then, a P-type impurity, for example, boron (B) is ion-implanted at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

  Next, as shown in FIG. 4, a LOCOS oxide film 7 is formed in a desired region of the epitaxial layer 4. First, a silicon nitride film (not shown) is formed on the silicon oxide film 6 by about 0.05 to 0.2 μm, for example. Thereafter, the silicon nitride film is selectively removed so that an opening is provided in a portion where the LOCOS oxide film 7 is formed.

  Then, using this silicon nitride film as a mask, an oxide film is formed from above the silicon oxide film 6 by, for example, steam oxidation at about 800 to 1200 ° C. At the same time, heat treatment is performed on the entire substrate 1 to form the LOCOS oxide film 7. At this time, in particular, element isolation is further achieved by forming the LOCOS oxide film 7 on the P-type isolation region 8. The LOCOS oxide film 7 is formed with a thickness of, for example, about 0.5 to 1.0 μm in the flat portion.

Next, as shown in FIG. 5, a silicon oxide film 9 is formed on the surface of the epitaxial layer 4 to a thickness of about 0.01 to 0.20 μm, for example. The silicon oxide film 9 is used as a gate oxide film below the gate electrode 11 (see FIG. 6). Then, a photoresist having an opening in a portion where the N-type diffusion region 10 is formed is formed using a known photolithography technique as a selection mask. Then, an N-type impurity such as phosphorus (P) is ion-implanted at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

Next, as shown in FIG. 6, a polysilicon (PolySi) film is deposited on the silicon oxide film 9 formed in FIG. 5 to about 0.2 to 0.3 μm, for example. Thereafter, an N-type impurity, for example, phosphorus (P) is ion-implanted into the polysilicon film at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, the PolySi film other than the gate electrode 11 formation region is removed by a known photolithography technique.

Thereafter, as shown in the figure, the silicon oxide film 9 formed in FIG. 5 is used and a photoresist having an opening in a portion where the P type diffusion region 12 is formed is formed by a known photolithography technique as a selection mask. To do. Then, a P-type impurity, for example, boron (B) is ion-implanted at an acceleration voltage of 60 to 100 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused. At this time, ion implantation can be performed more accurately by using the gate electrode 11 as a mask.

Next, as shown in FIG. 7, using the silicon oxide film 9 formed in FIG. 5, a photoresist in which openings are provided in portions where N-type diffusion regions 13 and 14 are formed by a known photolithography technique. As a selection mask. Then, an N-type impurity such as phosphorus (P) is ion-implanted at an acceleration voltage of 20 to 65 keV and an introduction amount of 1.0 × 10 ^{13 to} 1.0 × 10 ¹⁵ / cm ² . Then, after removing the photoresist, the ion-implanted impurity is diffused.

  Next, as shown in FIG. 8, a TEOS (Tetra-Ethyl-Orso-Silicate) film layer (not shown), a BPSG (Boron Phospho Silicate Glass) film layer 15 and the like are formed on substantially the entire upper surface of the epitaxial layer 4. .

  At this time, in this embodiment, a silicon nitride film (SiN) is deposited from the upper surface side of the BPSG film layer 15 and from the rear surface side of the substrate 2. That is, silicon nitride films are deposited from both sides of the substrate 1. Thereafter, only SiN formed on the upper surface of the BPSG film layer 15 is removed, and a warp preventing layer 16 made of an SiN layer is formed on the back surface of the substrate 1.

  In the present embodiment, the warp prevention layer 16 is formed before the deposition process of the metal layer constituting the first wiring layer and each electrode, for example, the Al layer. Therefore, although details will be described later, the semiconductor wafer 41 (see FIG. 10) is warped so as to draw an upwardly convex curve with respect to the surface. As a result, by forming a multilayer wiring layer, the semiconductor wafer 41 eventually warps against its surface, but the amount of warpage can be reduced more efficiently.

  On the other hand, on the upper surface of the BPSG film layer 15 from which SiN has been removed, contact holes 17 and 18 for the source electrode 22 or the drain electrode 23 of the MOS transistor are formed in the BPSG film layer 15 or the like by, for example, a known photolithography technique.

  Next, a barrier metal layer 19, a tungsten (W) layer 20, and an Al layer 21 are deposited by sputtering. At this time, the barrier metal layer 19 is formed by laminating a titanium (Ti) layer and a titanium nitride (TiN) layer. The W layer 20 is selectively formed in the contact hole 17 and 18 formation region, and the Al layer 21 is selectively formed in the electrode and first wiring layer formation region. In this embodiment, the source electrode 22 and the drain electrode 23 of the MOS transistor are formed by this process. In addition, although not shown, a first wiring layer of the semiconductor device is formed.

  Next, as shown in FIG. 9, an interlayer insulating layer between the first wiring layer and the second wiring layer 24, and between the second wiring layer 24 and the third wiring layer 25. An interlayer insulating layer and a third wiring layer 25 are formed. A TEOS film layer 26 is deposited on the upper surface of the first wiring layer or the like. The TEOS film layer 26 has irregularities formed on the surface thereof by the first wiring layer or the like. In order to eliminate this unevenness and form a flat surface, liquid SOG (Spin On Glass) is applied to form the SOG film layer 27. Thereafter, a TEOS film layer 28 is deposited again on the SOG film layer 27. As a result, the second wiring layer 24 is formed while maintaining flatness, and thus it is possible to prevent the wiring layer 24 from being short-circuited.

  Thereafter, the TEOS film layer 29, the SOG film layer 30, the TEOS film layer 31, and the third wiring layer 25 are formed on the upper surface of the second wiring layer 24 by the manufacturing method described above. Then, the SiN layer 32 is deposited on the entire upper surface of the third wiring layer 25 by, for example, plasma CVD (Plasma-Enhanced Chemical Vapor Deposition) at a formation temperature of 450 ° C. or lower in a reduced pressure state. At this time, the film thickness of the SiN layer 32 is deposited at about 3000 to 10000 mm. Thereafter, the warp preventing layer 16 formed on the back surface of the substrate 1 is removed, and the semiconductor device is completed.

  Next, with reference to FIG. 10 and FIG. 11, the relationship between the amount of warpage of the semiconductor wafer and the suction process in the reduction projection exposure apparatus (hereinafter referred to as a stepper) will be described.

  FIG. 10 is a cross-sectional view for explaining the amount of warpage of the semiconductor wafer. FIG. 11 is an explanatory diagram for explaining the relationship between the wiring forming process formed on the semiconductor wafer surface and the amount of warpage of the wafer.

  As described above, for example, when the pattern drawn on the mask is transferred onto the photoresist as in the process of forming the wiring layers 24 and 25, for example, an Al layer is formed on substantially the entire surface of the semiconductor wafer 41. After the formation, the surface of the Al layer is covered with a photoresist. Then, the semiconductor wafer 41 covered with the photoresist is fixed on the stage of the stepper, and the pattern drawn on the mask is transferred through a projection optical system using ultraviolet rays as a light source. At this time, in this embodiment, the semiconductor wafer 41 is fixed by an electrostatic chuck that is attracted to the semiconductor wafer 41 using an electric Coulomb force in a vacuum.

  Here, on the upper surface of the semiconductor wafer 41, an Al layer, a TEOS film layer, and an SOG film layer constituting the wiring layers 24 and 25 having different thermal expansion coefficients are deposited, and the respective materials are cured. Then, as shown in FIG. 10, the periphery of the end portion 42 of the semiconductor wafer 41 is warped.

  Specifically, for example, the thermal expansion coefficient of silicon constituting the semiconductor wafer 41 is 2.42E6 (/ deg), and the thermal expansion coefficient of Al is 2.313E5 (/ deg). Then, due to the difference in thermal expansion coefficient of the stacked materials, the material hardens while shrinking as the temperature during deposition decreases, and compressive stress is applied to the semiconductor wafer 41. In particular, since the wiring layers 24 and 25 are arranged over a wide area of the semiconductor wafer 41, the wiring layers 24 and 25 have a great influence on the warp amount X of the semiconductor wafer 41. Similarly, the semiconductor wafer 41 warps so as to draw an upwardly convex curve with respect to the surface due to the compressive stress caused by the shrinkage of the warp preventing layer 16 formed on the back surface of the semiconductor wafer 41.

  In FIG. 11, the warp amount X of the semiconductor wafer 41 is compared between the case where the warp preventing layer 16 made of a silicon nitride film layer is formed on the back surface of the semiconductor wafer 41 and the case where the warp preventing layer 16 is not formed. Specifically, the solid line is a case where the warp prevention layer 16 is not formed, the alternate long and short dash line is a case where the warp prevention layer 16 is formed about 1000 mm, and the two-dot chain line is a case where the warpage prevention layer 16 is formed about 2000 mm. This is the case.

  In the following description, a case where a downwardly convex curve is drawn with respect to the surface of the semiconductor wafer 41 is described as being warped, and a case where an upwardly convex curve is drawn is described as being warped down.

  As shown in the figure, first, before the warp preventing layer 16 is formed, the semiconductor wafer 41 is warped by about 30 μm due to its own weight in all three cases. When a warp preventing layer is formed on the back surface of the semiconductor wafer 41, the semiconductor wafer 41 warps by about 42 μm when the thickness is about 1000 mm, and the semiconductor wafer 41 warps by about 48 μm when the thickness is about 2000 mm. Go down.

  Next, in the state where the metal layer for forming the first wiring layer or the like is deposited and the photoresist is formed so as to cover the metal layer, when the warp preventing layer 16 is not formed, the semiconductor wafer 41 is Warps up about 35 μm. On the other hand, when the warp preventing layer 16 is formed, when the thickness is about 1000 mm, the semiconductor wafer 41 is warped by about 13 μm, and when the thickness is about 2000 mm, the semiconductor wafer 41 is warped by about 10 μm.

  Next, in the state where the metal layer for forming the second wiring layer or the like is deposited and the photoresist is formed so as to cover the metal layer, when the warp prevention layer 16 is not formed, the semiconductor wafer 41 is Warps up by about 80 μm. On the other hand, when the warp prevention layer 16 is formed, when the thickness is about 1000 mm, the semiconductor wafer 41 warps by about 57 μm, and when the thickness is about 2000 mm, the semiconductor wafer 41 warps by about 44 μm.

  Finally, when a metal layer for forming a third wiring layer or the like is deposited and a photoresist is formed so as to cover the metal layer, when the warp prevention layer 16 is not formed, the semiconductor wafer 41 is Warps up about 120 μm. On the other hand, when the warp preventing layer 16 is formed, when the thickness is about 1000 mm, the semiconductor wafer 41 is warped about 100 μm, and when the thickness is about 2000 mm, the semiconductor wafer 41 is warped about 85 μm.

  As described above, in the present embodiment, when the warp preventing layer 16 is not formed on the back surface of the semiconductor wafer 41, the semiconductor wafer 41 is in the process of depositing the first to third metal layers. The warp is about 35 μm, about 80 μm, and about 120 μm. In particular, as in the present embodiment, in a multilayer wiring structure consisting of three layers, the third metal layer forms a wiring layer such as a power supply line, so that the current thickness is secured, the layer thickness is Thick deposit. Therefore, after depositing the third metal layer, the semiconductor wafer 41 is warped by about 120 μm, and fixing of the semiconductor wafer 41 with the exposure apparatus at this stage becomes a problem.

  On the other hand, the case where the warp preventing layer 16 is formed on the back surface of the semiconductor wafer 41 after the third metal layer is deposited is measured. Then, when the thickness of the warp preventing layer 16 is about 1000 mm, the semiconductor wafer 41 warps about 100 μm, and when the thickness is about 2000 mm, the semiconductor wafer 41 warps about 85 μm. That is, compared with the case where the warpage prevention layer 16 is not formed, when the thickness of the warpage prevention layer 16 is about 1000 mm, the warpage can be reduced by about 20 μm, and when the thickness of the warpage prevention layer 16 is about 2000 mm, Warpage can be reduced by about 35 μm.

  Even after the first and second metal layers are deposited, the warpage of the semiconductor wafer 41 of about 20 to 30 μm can be reduced by forming the warpage prevention layer 16.

  That is, in the present embodiment, the thickness of the warp preventing layer formed on the back surface of the semiconductor wafer can be adjusted according to the use conditions such as the size of the semiconductor wafer to be used and the fixing capability of the stepper. When transferring a pattern such as a wiring layer to the photoresist on the upper surface of the semiconductor wafer, the stepper can securely fix the semiconductor wafer on the stage by reducing the amount of warpage of the semiconductor wafer.

  In this embodiment, the case where a silicon nitride film is used as the warpage preventing film has been described. However, the present invention is not limited to this case. For example, a polysilicon film layer or a TEOS film layer can be used as a warp prevention film.

  Further, the manufacturing process can be simplified by forming the warpage preventing layer as a common process with the multilayer wiring forming process. In addition, various modifications can be made without departing from the scope of the present invention.

It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the manufacturing method of the semiconductor device in embodiment of this invention. It is sectional drawing explaining the curvature amount of the semiconductor wafer in embodiment of this invention. It is explanatory drawing for demonstrating the relationship between the wiring formation process formed in the semiconductor wafer surface in embodiment of this invention, and the curvature amount of a wafer.

Explanation of symbols

1 P-type single crystal silicon substrate 4 Epitaxial layer 7 LOCOS oxide film 15 BPSG film layer 16 Warpage prevention layer 19 Barrier metal layer 20 Tungsten layer 21 Aluminum layer 24 Second wiring layer 25 Third wiring layer 26 TEOS film Layer 27 SOG film layer 28 TEOS film layer 29 TEOS film layer 30 SOG film layer 31 TEOS film layer 32 Silicon nitride film layer 41 Semiconductor wafer 42 Edge

Claims (5)

A semiconductor wafer having a first main surface serving as a semiconductor element formation region and a second main surface opposite to the first main surface is prepared, and the semiconductor wafer has a convex curve upward at least with respect to the first main surface. Forming a warp preventing layer on the second main surface to warp as drawn,
A method of manufacturing a semiconductor device, comprising: forming at least two wiring layers from the first main surface side, and then removing the warpage preventing layer. The method of manufacturing a semiconductor device according to claim 1, wherein the warpage preventing layer is formed before depositing a metal layer to be the wiring layer on the first main surface. 3. The semiconductor wafer according to claim 1, wherein the semiconductor wafer is placed in an exposure apparatus in a state where a metal layer serving as the wiring layer is deposited and the warp preventing layer is formed on the second main surface. The manufacturing method of the semiconductor device of description. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the warpage preventing layer is a silicon nitride film layer, a polysilicon layer, or a TEOS film layer. The method of manufacturing a semiconductor device according to claim 1, wherein the warpage preventing layer is formed after a LOCOS oxide film is formed on the first main surface side.

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