JP2005272874A - Method for producing circuit board - Google Patents
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- JP2005272874A JP2005272874A JP2004084522A JP2004084522A JP2005272874A JP 2005272874 A JP2005272874 A JP 2005272874A JP 2004084522 A JP2004084522 A JP 2004084522A JP 2004084522 A JP2004084522 A JP 2004084522A JP 2005272874 A JP2005272874 A JP 2005272874A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000004020 conductor Substances 0.000 claims abstract description 32
- 238000009713 electroplating Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000007747 plating Methods 0.000 claims description 28
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 12
- 229910000365 copper sulfate Inorganic materials 0.000 claims description 9
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 6
- 238000013019 agitation Methods 0.000 claims description 6
- 239000000460 chlorine Substances 0.000 claims description 6
- 229910052801 chlorine Inorganic materials 0.000 claims description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-O Ammonium Chemical compound [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 claims description 3
- 239000004721 Polyphenylene oxide Substances 0.000 claims description 3
- 125000002091 cationic group Chemical group 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 229920000570 polyether Polymers 0.000 claims description 3
- BWGNESOTFCXPMA-UHFFFAOYSA-N Dihydrogen disulfide Chemical compound SS BWGNESOTFCXPMA-UHFFFAOYSA-N 0.000 claims description 2
- 125000000129 anionic group Chemical group 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000001556 precipitation Methods 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000003795 chemical substances by application Substances 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000003112 inhibitor Substances 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 239000011295 pitch Substances 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- -1 anionic disulfide sulfur compound Chemical class 0.000 description 1
- 230000005587 bubbling Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 150000002830 nitrogen compounds Chemical class 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Landscapes
- Electroplating And Plating Baths Therefor (AREA)
- Electroplating Methods And Accessories (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
本発明は、回路基板の製造方法に関するものである。 The present invention relates to a circuit board manufacturing method.
近年、電子機器の小型化、高機能化に伴い、配線基板における細線化、ファインピッチ化、高密度実装化への要求が高まってきている。この要求に対し、特にめっき分野では、接続端子の微細化に対応する処理方法が求められており、狭ピッチ対応のマイクロバンプの形成方法や、高密度多層配線板の一括積層のための接続端子としてフィルドビア構造を持つバンプの形成方法が検討されている。 In recent years, with the miniaturization and high functionality of electronic devices, there has been an increasing demand for thinning, fine pitch, and high density mounting in wiring boards. In response to this requirement, particularly in the field of plating, there is a need for a processing method corresponding to the miniaturization of connection terminals. A method of forming micro bumps corresponding to narrow pitches and connection terminals for batch lamination of high-density multilayer wiring boards. A method for forming a bump having a filled via structure is being studied.
しかし、これらのバンプを銅めっきで形成する場合、従来のものは、電流密度が０．１〜３Ａ/ｄｍ2が一般的で、このため、数百μｍ高さの高アスペクトのバンプ形成においては、１回の処理時間が１〜20時間かかっていた。このため、生産性が悪く実用上の問題があった。さらに、一般に用いられる硫酸銅めっき液は貫通スルーホール内にめっきのレベリング性のよい添加剤が使われており、これをバンプ形成に用いた場合、バンプのXY方向の析出が比較的大きいため、Z方向の所定のバンプ高さを得るために、バンプ径が広がってしまい、狭ピッチのバンプ形成に向いていなかった。さらに、これらのメッキにはパルスメッキなどの特殊な整流方法や、差圧噴流法、回転法、パドル法などの特別な液攪拌が必要とされ、生産する上で設備的、工数的制約を大きく受けていた。（例えば特許文献１）
本発明は、生産性がよく、より微小化に適し、より品質の安定した銅バンプを形成するための回路基板の製造方法を提供するものである。 The present invention provides a method of manufacturing a circuit board for forming copper bumps with good productivity, suitable for miniaturization, and stable quality.
このような目的は、下記（１）〜（８）に記載の本発明により達成される。
（１）導体回路上に電気めっきによって導体バンプを形成する回路基板の製造方法であって、前記導体バンプの水平方向の形成速度に対して、垂直方向の形成速度が２〜１０倍であることを特徴とする回路基板の製造方法。
（２）前記電気めっきの電流密度を、漸増して導体バンプを形成するものである上記（１）に記載の回路基板の製造方法。
（３）前記電流密度が、初期が１〜１０Ａ／ｄｍ2で、最終が１０〜３０Ａ／ｄｍ2である上記（２）に記載の回路基板の製造方法。
（４）前記電気めっきは、直流電流で行うものである上記（１）ないし（３）のいずれかに記載の回路基板の製造方法。
（５）前記電気めっきの工程で、１〜２０Ｌ/分の割合で直径１ｃｍ以下の気泡でエアー攪拌をおこなうことを特徴とする上記（１）ないし（４）のいずれかに記載の回路基板の製造方法。
（６）前記電気めっきの、めっき浴のめっき浴組成が硫酸銅濃度１００〜１６０ｇ／Ｌ、硫酸濃度１００〜１７０ｇ／Ｌ、塩素２０〜８０ｐｐｍを含むものである上記（１）ないし（５）のいずれかに記載の回路基板の製造方法。
（７）さらには、前記めっき浴に分子量１０００〜３００００の非イオン性ポリエーテル系成分を１〜１０ｍｌ／Ｌと、アニオン性ジスルフィド系成分を０．１〜３ｍｌ／Ｌと、カチオン性アンモニウム系成分を１〜１０ｍｌ／Ｌとを含むものである上記（６）に記載の回路基板の製造方法。
（８）さらには、前記めっき浴のめっき浴温が２５〜４５℃である上記（６）または（７）に記載の回路基板の製造方法。
Such an object is achieved by the present invention described in the following (1) to (8).
(1) A method of manufacturing a circuit board in which conductor bumps are formed on a conductor circuit by electroplating, wherein the formation speed in the vertical direction is 2 to 10 times the horizontal formation speed of the conductor bumps. A method of manufacturing a circuit board characterized by the above.
(2) The method for manufacturing a circuit board according to (1), wherein the current density of the electroplating is gradually increased to form a conductor bump.
(3) the current density, the initial stage at 1 to 10 A / dm 2, a manufacturing method of a circuit board according to the final is 10~30A / dm 2 (2).
(4) The method for manufacturing a circuit board according to any one of (1) to (3), wherein the electroplating is performed with a direct current.
(5) The circuit board according to any one of (1) to (4), wherein in the electroplating step, air agitation is performed with bubbles having a diameter of 1 cm or less at a rate of 1 to 20 L / min. Production method.
(6) Any one of the above (1) to (5), wherein the plating bath composition of the electroplating contains a copper sulfate concentration of 100 to 160 g / L, a sulfuric acid concentration of 100 to 170 g / L, and chlorine of 20 to 80 ppm. A method for producing a circuit board according to claim 1.
(7) Furthermore, a nonionic polyether component having a molecular weight of 1000 to 30000, 1 to 10 ml / L, an anionic disulfide component to 0.1 to 3 ml / L, and a cationic ammonium component in the plating bath. The manufacturing method of the circuit board as described in said (6) which contains 1-10 ml / L.
(8) Furthermore, the method for manufacturing a circuit board according to (6) or (7), wherein the plating bath temperature of the plating bath is 25 to 45 ° C.
本発明により、生産性が高く、高さばらつきが少なく、バンプ径の広がりが少ない微小銅バンプを作成する回路基板の製造方法を提供することができる。 According to the present invention, it is possible to provide a circuit board manufacturing method for producing a fine copper bump with high productivity, small height variation, and small bump diameter spread.
以下、本発明の実施形態について、詳細に説明するが、本発明はこれに何ら限定されるものではない。 Hereinafter, although an embodiment of the present invention is described in detail, the present invention is not limited to this at all.
本発明の、回路基板の製造方法では、絶縁層で囲われた導体回路上に電気めっきでボトムアップにより導体バンプを形成する際、絶縁層表層より突出した導体バンプは水平方向の形成速度に対して、垂直方向の形成速度が２〜１０倍となる。これは以下の方法によって得ることができる。 In the method for manufacturing a circuit board according to the present invention, when a conductor bump is formed by bottom-up by electroplating on a conductor circuit surrounded by an insulating layer, the conductor bump protruding from the surface layer of the insulating layer has a horizontal formation speed. Thus, the formation speed in the vertical direction is 2 to 10 times. This can be obtained by the following method.
電気めっきの際、めっきの電流密度を初期の電流密度より漸増させつつめっき析出をおこなう。このときの電流密度の水準は２種類以上あればよく、特に限定されないが、必要な導体バンプ高さや径にあわせ、特に高アスペクトになるほど多くすることが望ましい。そして、各電流密度水準での処理時間は少なくとも０．５μｍ以上めっき析出させることが望ましい。 During electroplating, plating deposition is performed while gradually increasing the plating current density from the initial current density. There are no particular limitations on the level of current density at this time, and there are no particular limitations. However, it is desirable that the current density be increased as the aspect ratio increases in accordance with the required height and diameter of the conductor bumps. And, it is desirable that the processing time at each current density level is at least 0.5 μm or more.
また、このとき、初期の電流密度は１〜１０Ａ／ｄｍ2の中から選ばれ、選ばれた電流密度から漸増して、最終の電流密度は１０〜３０Ａ／ｄｍ2となるようにする。このとき、漸増する電流密度や処理時間は等間隔、等増率にする必要はなく、必要な導体バンプ高さや導体バンプ径にあわせ、高アスペクトになるほど初期電流密度を低く取り漸増間隔を狭く、低アスペクトになるほど初期電流密度を高めに漸増間隔を広くしてやればよい。 At this time, the initial current density is selected from 1 to 10 A / dm 2 , and gradually increases from the selected current density so that the final current density is 10 to 30 A / dm 2 . At this time, the increasing current density and processing time do not need to be equal intervals, equal increase rate, according to the required conductor bump height and conductor bump diameter, the higher the aspect, the lower the initial current density and the gradually increasing interval, The lower the aspect, the higher the initial current density and the wider the increment interval.
また、これらの電流密度は一般の直流電流でよい。特に微小導体バンプに対するめっきに対しては、極微量な電流制御がおこなえる直流電源を用意する。このとき被めっき物は導体バンプを形成する部分以外は全てめっきレジストで保護してあることが望ましい。 These current densities may be general DC currents. In particular, a direct current power source capable of controlling a very small amount of current is prepared for plating on a minute conductor bump. At this time, it is desirable that the object to be plated is protected by the plating resist except for the portion where the conductor bump is formed.
次に、この電気めっきの際におこなわれる液攪拌はエアー攪拌を用いるとより簡便であり、風量１〜２０L／分、望ましくは８L／分で処理されることが望ましい。このとき、エアーバブリングの気泡は液の均一な対流を促すため直径１ｃｍ以下、好ましくは１ｍｍ以下に調整される。そして陽極と陰極の間に設置され、好ましくは被めっき物から１〜１０ｃｍ離れた位置に被めっき物全体をカバーするように配置されることが望ましい。 Next, the liquid agitation performed during the electroplating is simpler if air agitation is used, and the air volume is 1 to 20 L / min, preferably 8 L / min. At this time, the air bubbling bubbles are adjusted to a diameter of 1 cm or less, preferably 1 mm or less in order to promote uniform convection of the liquid. And it is installed between an anode and a cathode, It is desirable to arrange | position so that it may cover the whole to-be-plated object preferably in the position 1-10 cm away from the to-be-plated object.
さらに、使用するめっき液は硫酸銅浴であり、無機組成は硫酸銅、硫酸、塩素からなる。ここで硫酸銅濃度は１００〜１６０ｇ／L、硫酸濃度は１００〜１７０ｇ／L、塩素２０〜８０ｐｐｍが好ましく、さらに硫酸銅１３０ｇ／L、硫酸１３５ｇ／L、塩素５０ｐｐｍであることが好ましい。さらに、めっき添加剤としては、特に指定されるものではなく、高電流密度に対応したもので、抑制剤、促進剤、レベリング剤の３成分からなり、抑制剤は分子量１０００〜３００００の非イオン性ポリエーテル系の高分子化合物。促進剤はアニオン性のジスルフィド系のイオウ化合物。レベリング剤はカチオン性アンモニウム系の窒素化合物であることが望ましい。 Further, the plating solution used is a copper sulfate bath, and the inorganic composition is composed of copper sulfate, sulfuric acid, and chlorine. Here, the copper sulfate concentration is preferably 100 to 160 g / L, the sulfuric acid concentration is preferably 100 to 170 g / L, and chlorine 20 to 80 ppm, and further preferably copper sulfate 130 g / L, sulfuric acid 135 g / L, and chlorine 50 ppm. Further, the plating additive is not particularly specified, and corresponds to a high current density, and is composed of three components, an inhibitor, an accelerator, and a leveling agent, and the inhibitor is a nonionic having a molecular weight of 1000 to 30000. Polyether-based polymer compound. The accelerator is an anionic disulfide sulfur compound. The leveling agent is preferably a cationic ammonium-based nitrogen compound.
また、これらのめっき液の浴温は２５〜４０℃であり、より高電流域のめっき析出や光沢を安定させるためには４０℃に設定されることが望ましい。 Moreover, the bath temperature of these plating solutions is 25-40 degreeC, and in order to stabilize the plating precipitation and glossiness of a higher electric current range, it is desirable to set to 40 degreeC.
このような方法でえられた導体バンプは、導体回路面に対して垂直なＺ方向に優先的にめっきが析出し、導体回路面に対して水平なＸＹ方向の析出が比較的小さいため、導体バンプが絶縁層表面までめっき析出したときに、径が小さくより突出した高さの均一な導体バンプの形状となる。たとえば４０μm高さの導体バンプを形成する場合、３Ａ／ｄｍ2で１μｍ、次に５Ａ／ｄｍ2で４μｍ、更に１０Ａ／ｄｍ2で５μｍと段階的に電流を上昇させながらバンプを形成していき、最終的に２０Ａ／ｄｍ2で２０μｍ処理することにより、微小径、高アスペクト比の導体バンプであっても、約１３．２分で、高さばらつき、コゲ、ボイド、異常析出の少ない良好なバンプを効率よく形成することができる。 The conductor bumps obtained in this way are preferentially deposited in the Z direction perpendicular to the conductor circuit surface, and the deposition in the XY direction horizontal to the conductor circuit surface is relatively small. When the bumps are deposited to the surface of the insulating layer, the shape of the conductor bumps having a small diameter and a more protruding height is obtained. For example, when forming a 40 μm high conductor bump, the bump is formed while increasing the current stepwise from 1 μm at 3 A / dm 2 , then 4 μm at 5 A / dm 2 , and further 5 μm at 10 A / dm 2 . Finally, by processing 20 μm at 20 A / dm 2 , even in the case of a conductor bump with a small diameter and a high aspect ratio, the height variation, kogation, voids, and abnormal precipitation are good in about 13.2 minutes. Bumps can be formed efficiently.
さらに、この方法で得られる導体バンプを絶縁層表層上に突出させた場合、絶縁層表層上の導体バンプは絶縁層面に対して平行なＸＹ方向の析出に対して、絶縁層面に垂直なＺ方向の析出が２〜１０倍の割合で大きい。これによって、導体バンプ径の広がりが小さく、より突出した導体バンプを絶縁層表層上に形成することができる。 Furthermore, when the conductor bump obtained by this method is projected on the surface of the insulating layer, the conductor bump on the surface of the insulating layer is in the Z direction perpendicular to the surface of the insulating layer with respect to precipitation in the XY direction parallel to the surface of the insulating layer. Is large at a rate of 2 to 10 times. As a result, the conductor bump diameter is small and a more protruding conductor bump can be formed on the surface of the insulating layer.
銅箔１８μm、ポリイミド２５μmの片面フレキシブル銅張板にＵＶレーザーでポリイミドを除去しトップ径φ５０μｍ、ボトム径φ４０μｍのブラインドビアを形成したものに、硫酸銅濃度１３０ｇ／L、硫酸濃度２４３ｇ／L、塩素５０ｐｐｍ、抑制剤５ｍｌ／Ｌ、促進剤１ｍｌ／Ｌ、レベリング剤５ｍｌ／Ｌの硫酸銅メッキを浴温４０℃、エアー攪拌８Ｌ／分の状態で、銅箔面側をマスキングし、めっき処理電流条件を５A/ｄｍ2で５μｍ、１０Ａ／ｄｍ2で５μｍ、１５Ａ／ｄｍ2で５μｍ、２０A／ｄｍ2で２０μmと段階的に処理し、ポリイミド表層にバンプメッキを形成した。 A single-sided flexible copper-clad plate with 18 μm copper foil and 25 μm polyimide, with polyimide removed by UV laser to form blind vias with a top diameter of 50 μm and a bottom diameter of 40 μm, has a copper sulfate concentration of 130 g / L, a sulfuric acid concentration of 243 g / L, chlorine 50ppm, inhibitor 5ml / L, accelerator 1ml / L, leveling agent 5ml / L copper sulfate plating at a bath temperature of 40 ° C and air agitation at 8L / min. the 5A / dm 2 at 5 [mu] m, 10A / dm 2 at 5 [mu] m, 15A / dm 2 at 5 [mu] m, 20A / dm 2 in treated 20μm stepwise, to form a bump plating the polyimide surface.
形成された銅バンプはポリイミド面から平均高さ１７μｍ、平均直径φ５８μｍの突出したドーム状の銅バンプであり、高さばらつきはσ＝０．８μｍ、直径ばらつきはσ＝１．９μｍであった。 The formed copper bumps were dome-shaped copper bumps protruding from the polyimide surface with an average height of 17 μm and an average diameter φ of 58 μm. The height variation was σ = 0.8 μm and the diameter variation was σ = 1.9 μm.
また、このバンプの径と高さの関係から、水平方向の析出めっきの広がりが（５８−５０）÷２＝４μｍに対し、垂直方向のめっきの析出が１７μｍであるため、水平方向に対する垂直方向の析出速度が１７÷４≒４倍であることがわかる。 In addition, from the relationship between the diameter and height of the bumps, the horizontal plating plating spread is (58-50) / 2 = 4 μm, whereas the vertical plating deposition is 17 μm. It can be seen that the precipitation rate of is 17 ÷ 4≈4 times.
本発明は、電子機器の部品として用いられる配線回路のマイクロバンプ形成用のめっき液に関するものである。 The present invention relates to a plating solution for forming micro bumps of a wiring circuit used as a component of an electronic device.
Claims (8)
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| JP2004084522A JP2005272874A (en) | 2004-03-23 | 2004-03-23 | Method for producing circuit board |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2007149920A (en) * | 2005-11-28 | 2007-06-14 | Toppan Printing Co Ltd | BGA type carrier substrate manufacturing method and BGA type carrier substrate |
| JP2009102674A (en) * | 2007-10-22 | 2009-05-14 | Ebara Corp | Plating method and plating apparatus |
| JP2012122097A (en) * | 2010-12-08 | 2012-06-28 | Ebara Corp | Electroplating method |
| US9006580B2 (en) | 2011-06-09 | 2015-04-14 | Ngk Spark Plug Co., Ltd. | Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate |
| JP2017036501A (en) * | 2015-08-06 | 2017-02-16 | ローム アンド ハース エレクトロニック マテリアルズ エルエルシーＲｏｈｍ ａｎｄ Ｈａａｓ Ｅｌｅｃｔｒｏｎｉｃ Ｍａｔｅｒｉａｌｓ ＬＬＣ | Method for electroplating photoresist defining features from an electrocopper plating bath containing a reaction product of an alpha amino acid and a bisepoxide |
| JPWO2015162775A1 (en) * | 2014-04-25 | 2017-04-13 | 株式会社Ｊｃｕ | High speed copper filling method |
Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4944942A (en) * | 1972-09-05 | 1974-04-27 | ||
| JPS5337542A (en) * | 1976-09-20 | 1978-04-06 | Nippon Electric Co | Constant current density bump plating method |
| JPS57210988A (en) * | 1981-06-22 | 1982-12-24 | Sumitomo Electric Ind Ltd | Plating method |
| JPS58177488A (en) * | 1982-04-09 | 1983-10-18 | Fujitsu Ltd | Electroplating method |
| JPS644091A (en) * | 1987-06-26 | 1989-01-09 | Sony Corp | Plating |
| JPH05243730A (en) * | 1992-03-03 | 1993-09-21 | Hitachi Chem Co Ltd | Manufacture of printed wiring board |
| JPH05295589A (en) * | 1992-04-21 | 1993-11-09 | Oki Electric Ind Co Ltd | Bump electrode plating device for semiconductor wafer and plating method thereof |
| JPH06158396A (en) * | 1992-11-25 | 1994-06-07 | Sakae Denshi Kogyo Kk | Method for agitating electroplating liquid |
| JPH11100690A (en) * | 1997-09-25 | 1999-04-13 | Tdk Corp | Microstructure and manufacturing method thereof |
| JP2000080496A (en) * | 1998-09-03 | 2000-03-21 | Ebara Corp | Filling plating method for base material having fine holes and / or fine grooves |
| JP2001181895A (en) * | 1999-07-12 | 2001-07-03 | Applied Materials Inc | Process window for electrochemical deposition of high aspect ratio structures |
| JP2001234396A (en) * | 1999-11-12 | 2001-08-31 | Applied Materials Inc | Conductive bias member for metal layer |
| JP2002105687A (en) * | 2000-09-26 | 2002-04-10 | Morita Kagaku Kogyo Kk | Copper thin film plating method |
| JP2003213489A (en) * | 2002-01-15 | 2003-07-30 | Learonal Japan Inc | Via filling method |
| WO2004016829A2 (en) * | 2002-08-16 | 2004-02-26 | Atofina Chemicals, Inc. | Electrolytic copper plating solutions |
| JP2004068088A (en) * | 2002-08-07 | 2004-03-04 | C Uyemura & Co Ltd | Copper sulfate plating bath and electrolytic copper plating method |
| JP2005097732A (en) * | 2003-08-21 | 2005-04-14 | Ebara Corp | Plating apparatus |
-
2004
- 2004-03-23 JP JP2004084522A patent/JP2005272874A/en active Pending
Patent Citations (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4944942A (en) * | 1972-09-05 | 1974-04-27 | ||
| JPS5337542A (en) * | 1976-09-20 | 1978-04-06 | Nippon Electric Co | Constant current density bump plating method |
| JPS57210988A (en) * | 1981-06-22 | 1982-12-24 | Sumitomo Electric Ind Ltd | Plating method |
| JPS58177488A (en) * | 1982-04-09 | 1983-10-18 | Fujitsu Ltd | Electroplating method |
| JPS644091A (en) * | 1987-06-26 | 1989-01-09 | Sony Corp | Plating |
| JPH05243730A (en) * | 1992-03-03 | 1993-09-21 | Hitachi Chem Co Ltd | Manufacture of printed wiring board |
| JPH05295589A (en) * | 1992-04-21 | 1993-11-09 | Oki Electric Ind Co Ltd | Bump electrode plating device for semiconductor wafer and plating method thereof |
| JPH06158396A (en) * | 1992-11-25 | 1994-06-07 | Sakae Denshi Kogyo Kk | Method for agitating electroplating liquid |
| JPH11100690A (en) * | 1997-09-25 | 1999-04-13 | Tdk Corp | Microstructure and manufacturing method thereof |
| JP2000080496A (en) * | 1998-09-03 | 2000-03-21 | Ebara Corp | Filling plating method for base material having fine holes and / or fine grooves |
| JP2001181895A (en) * | 1999-07-12 | 2001-07-03 | Applied Materials Inc | Process window for electrochemical deposition of high aspect ratio structures |
| JP2001234396A (en) * | 1999-11-12 | 2001-08-31 | Applied Materials Inc | Conductive bias member for metal layer |
| JP2002105687A (en) * | 2000-09-26 | 2002-04-10 | Morita Kagaku Kogyo Kk | Copper thin film plating method |
| JP2003213489A (en) * | 2002-01-15 | 2003-07-30 | Learonal Japan Inc | Via filling method |
| JP2004068088A (en) * | 2002-08-07 | 2004-03-04 | C Uyemura & Co Ltd | Copper sulfate plating bath and electrolytic copper plating method |
| WO2004016829A2 (en) * | 2002-08-16 | 2004-02-26 | Atofina Chemicals, Inc. | Electrolytic copper plating solutions |
| JP2005535787A (en) * | 2002-08-16 | 2005-11-24 | アーケマ・インコーポレイテッド | Electrolytic copper plating solution |
| JP2005097732A (en) * | 2003-08-21 | 2005-04-14 | Ebara Corp | Plating apparatus |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007149920A (en) * | 2005-11-28 | 2007-06-14 | Toppan Printing Co Ltd | BGA type carrier substrate manufacturing method and BGA type carrier substrate |
| JP2009102674A (en) * | 2007-10-22 | 2009-05-14 | Ebara Corp | Plating method and plating apparatus |
| JP2012122097A (en) * | 2010-12-08 | 2012-06-28 | Ebara Corp | Electroplating method |
| US9006580B2 (en) | 2011-06-09 | 2015-04-14 | Ngk Spark Plug Co., Ltd. | Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate |
| JPWO2015162775A1 (en) * | 2014-04-25 | 2017-04-13 | 株式会社Ｊｃｕ | High speed copper filling method |
| JP2017036501A (en) * | 2015-08-06 | 2017-02-16 | ローム アンド ハース エレクトロニック マテリアルズ エルエルシーＲｏｈｍ ａｎｄ Ｈａａｓ Ｅｌｅｃｔｒｏｎｉｃ Ｍａｔｅｒｉａｌｓ ＬＬＣ | Method for electroplating photoresist defining features from an electrocopper plating bath containing a reaction product of an alpha amino acid and a bisepoxide |
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