JP2005268738A - Solid-state imaging device and manufacturing method thereof, and semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve high reliability in a solid-state imaging device and a semiconductor integrated circuit device in which constituent elements are formed on both surfaces of a substrate.
An alignment mark 17 comprising a buried layer 19 made of a material distinguishable from the semiconductor substrate 2 and having a surface of the buried layer 19 flush with the surface of the semiconductor substrate 2 is formed on the semiconductor substrate 2. 2 are provided with components 9, PD, 14, 15 and the like formed with the alignment mark 17 as a reference.
[Selection] Figure 1

Description

  The present invention relates to a solid-state imaging device and a method for manufacturing the same, and a semiconductor integrated circuit device and a method for manufacturing the same.

  Typical examples of the solid-state image pickup device include a charge transfer type CCD solid-state image pickup device (so-called CCD image sensor) and a CMOS solid-state image pickup device (so-called CMOS image sensor) which reads by specifying an XY address. Each of these solid-state imaging devices is similar in that light incident on a two-dimensionally arranged photodiode is photoelectrically converted, and one of the charges (for example, electrons) is used as a signal charge.

  For example, in the case of a CMOS solid-state imaging device, each pixel has a MOS transistor such as a read transistor, a reset transistor, or an amplification transistor, and processes signal charges photoelectrically converted by a photodiode. Each pixel is selected by a vertical wiring (X-direction wiring) and a horizontal wiring (Y-direction wiring), and aluminum (Al), copper (Cu), or the like is placed above each pixel. Metal wiring exists in multiple layers. In a CMOS solid-state imaging device, it is known that when light is collected from an on-chip lens formed on a pixel to a photodiode, the light is kicked by a multilayer wiring and sensitivity is lowered. Furthermore, the light kicked by these multilayer wirings may enter adjacent pixels and cause color mixing or the like.

Also in a CCD solid-state imaging device, it is known that light is absorbed by an interlayer insulating film on the device and sensitivity is lowered (see Patent Document 1). In these imaging devices, a structure has been proposed in which the back side of a silicon semiconductor substrate is polished to form a thin film, and light is incident from the back side of the substrate to perform photoelectric conversion (see Patent Document 1). Furthermore, the CCD solid-state imaging device has a configuration in which a charge transfer portion is formed on the front surface side of the semiconductor substrate and a charge accumulation portion is formed on the back surface side. When forming these charge transfer portion and charge accumulation portion, A manufacturing method has been proposed in which dedicated concave and convex alignment marks are formed in order to align front and back patterns (see Patent Document 2).
JP-A-6-29506 JP 2002-151676 A

  By the way, using the uneven alignment marks formed on the back surface or the front surface of the conventional semiconductor substrate, the interlayer insulation of the color filter, on-chip lens, photodiode, MOS transistor, or multilayer wiring on the back surface or the front surface of the substrate, respectively. When forming a film or the like, uneven alignment marks induce uneven coating in a step of applying a coating material such as a photoresist or SOG (Spin On Glass). This coating unevenness may affect the resolution of the photoresist pattern, for example, and it may not be possible to form an interlayer film with a uniform thickness, leading to a defect in the pattern of each component of the solid-state imaging device. . In particular, the pattern accuracy of each component formed on the surface side of the semiconductor substrate was important. Therefore, it is necessary to avoid a pattern defect of each component at least on the surface side of the semiconductor substrate.

  Such a problem is not limited to a solid-state image sensor, and may occur in a semiconductor integrated circuit device in which semiconductor elements and / or wirings are formed on both front and back surfaces of a semiconductor substrate, for example.

  In view of the above, the present invention provides a solid-state imaging device in which each component is accurately formed on both front and back sides of a semiconductor substrate, a manufacturing method thereof, a semiconductor integrated circuit device, and a manufacturing method thereof.

  In the solid-state imaging device according to the present invention, an alignment mark made of an embeddable layer of an identifiable material that is flush with the substrate surface is formed on a semiconductor substrate, and the alignment mark is formed on the front side and the back side of the semiconductor substrate. A component is provided.

  A semiconductor integrated circuit device according to the present invention has an alignment mark made of a buried layer on the same surface as a substrate surface on a semiconductor substrate, and is provided with components formed on the front side and the back side of the semiconductor substrate based on the alignment mark. It is characterized by being made.

As a preferred embodiment of the present invention, a silicon substrate is used as the semiconductor substrate, and a buried layer made of a material different from silicon is formed in a groove in which alignment marks are formed in the silicon substrate. As a material different from this silicon, any material of SiO, SiN, SiC, SiON, SiOC, SiCN, and polysilicon can be used.
The aspect ratio of the groove depth to the opening width or opening diameter of the groove forming the alignment mark is preferably 1.0 or more.

  As a preferred embodiment of the present invention, an SOI substrate is used, at least the other silicon layer of the SOI substrate is removed, a semiconductor substrate is formed with one silicon layer after that, and an alignment mark is embedded in a groove reaching the insulating layer of the SOI substrate. The buried layer is formed.

The alignment mark is formed so as to reach the back surface side from the front surface side of the semiconductor substrate.
The alignment mark can be formed in a multilayer structure including a thin film of a first material different from silicon of the substrate formed in the groove and a buried layer of a second material different from the first material. The thin film of the first material is preferably formed excluding the side wall near the opening of the groove.

  As the first material of the thin film, any material of SiO, SiN, SiCN, SiC, SiOC, SiO or SiON is used, and as the second material of the buried layer, a material having an etching selectivity with respect to the thin film is used. it can.

When an SOI substrate is used, the insulating layer can be removed or left as necessary.
The alignment mark can be formed in a square shape with each side being separated in plan view.

In a preferred embodiment of the present invention, a silicon substrate is used as a semiconductor substrate, and an alignment mark is formed in a first buried layer made of a material different from silicon formed on the opening side of the groove in the depth direction of the silicon substrate and in the groove. The second buried layer is made of a material different from that of the buried layer.
The thickness of the first buried layer is preferably 5 nm or more.
As the material of the first buried layer, any one of silicon nitride, polysilicon, amorphous silicon, and silicon containing carbon can be used.

  In the method for manufacturing a solid-state imaging device according to the present invention, an alignment mark is formed on a semiconductor substrate, which includes an embedded layer made of a material distinguishable from the semiconductor substrate, and the surface of the embedded layer is flush with the surface of the semiconductor substrate. And a step of forming components on the front surface side and the back surface side of the semiconductor substrate having a required thickness finally obtained from the semiconductor substrate with reference to the alignment mark.

  In the method for manufacturing a semiconductor integrated circuit device according to the present invention, an alignment mark is formed on a semiconductor substrate. The alignment mark includes a buried layer made of a material distinguishable from the semiconductor substrate, and the surface of the buried layer is flush with the surface of the semiconductor substrate. And a step of forming a component on the front side and the back side of the semiconductor substrate having a required thickness finally obtained from the semiconductor substrate with reference to the alignment mark.

As a preferred form of the manufacturing method, a silicon substrate is used as a semiconductor substrate, and an embedded layer made of a material different from silicon is formed in the groove to form an alignment mark.
As a material different from this silicon, any material of SiO, SiN, SiC, SiON, SiOC, SiCN, and polysilicon can be used.
The aspect ratio of the groove for forming the alignment mark, that is, the ratio A / B of the groove depth A to the groove width or the groove diameter B is preferably set to 10 or more.

  As a preferred form of the manufacturing method, an SOI substrate is used as a semiconductor substrate, and the insulating layer is used as an etching stop layer, and a groove reaching the insulating layer is formed in one silicon layer to be a finally obtained semiconductor substrate. Forming a buried layer therein to form an alignment mark.

  The alignment mark is preferably formed so as to reach the rear surface side from the front surface side of the finally obtained semiconductor substrate.

As a preferred form of the above manufacturing method, a thin film of a first material different from silicon and a buried layer of a second material different from the first material are formed in the groove of the silicon substrate to form an alignment mark having a multilayer structure.
The thin film of the first material is preferably formed excluding the side wall near the opening of the groove.

  Any material of SiO, SiN, SiCN, SiC, SiOC, SiO, or SiON can be used as the first material of the thin film, and a material having an etching selectivity with respect to the thin film can be used as the second material of the buried layer. .

When an SOI substrate is used, the insulating layer may be removed as necessary, or the insulating layer may be left.
The alignment mark may be formed in a square shape with each side being separated in plan view.

A preferred embodiment of the present invention uses an SOI substrate having silicon layers on both sides of an insulating layer,
The step of forming a groove reaching the insulating layer from the main surface of one of the silicon layers, using the insulating layer as an etching blocking layer in one silicon layer of the required thickness finally obtained, and removing the groove opening in the groove Forming a second buried layer made of a material different from silicon, and forming a first buried layer made of a material different from silicon and the second buried layer in the groove opening portion. An alignment mark is formed by the first buried layer and the second buried layer.
As the material of the first buried layer, any one of silicon nitride, polysilicon, amorphous silicon, and silicon containing carbon can be used, and as the material of the second buried layer, silicon oxide can be used.

  According to the solid-state imaging device according to the present invention, the semiconductor substrate has the alignment mark in which the surface of the buried layer made of an identifiable material is flush with the surface of the semiconductor substrate. Uneven application of the coating material when forming the component is avoided. Therefore, it is possible to provide a highly reliable solid-state imaging device having a highly accurate component without pattern defects on the front surface side and the back surface side of the semiconductor substrate, in particular, a color filter having excellent optical characteristics and an on-chip lens.

  According to the semiconductor integrated circuit device of the present invention, the semiconductor substrate has the alignment mark in which the surface of the embedment layer made of an identifiable material is flush with the surface of the semiconductor substrate, so that it is necessary from both the front and back surfaces of the semiconductor substrate. When the components are formed, uneven application of the coating material is avoided. Accordingly, it is possible to provide a highly reliable semiconductor integrated circuit device having a high-precision component without pattern defects on the front surface side and the back surface side of the semiconductor substrate, for example, a transistor having excellent characteristics or a multilayer wiring layer. it can.

As an alignment mark, a buried layer made of a material different from silicon, for example, any material of SiO, SiN, SiC, SiON, SiOC, SiCN, or polysilicon is embedded in a groove formed in the thickness direction of a semiconductor substrate, preferably a silicon substrate. Therefore, the alignment mark can be accurately identified from both the front and back surfaces.
By setting the aspect ratio of the groove for forming the alignment mark, that is, the ratio A / B of the groove depth A to the groove width or the groove diameter B to 1.0 or more, the exposed surface of the alignment mark is uneven, voids, etc. A good alignment mark that does not occur is obtained.

When the solid-state imaging device of the present invention is configured using an SOI substrate, the alignment mark is formed by a buried layer embedded in the groove reaching the insulating layer serving as an etching blocking layer from the main surface of one silicon layer. Therefore, unevenness does not occur on the back surface layer of one silicon layer of the alignment mark.
When the alignment mark is formed in a square shape in which each side is separated as viewed in a plan view, generation of voids at the four corner portions can be avoided, and a favorable component can be formed.

When the alignment mark is composed of a first embedded layer formed on the opening side of the groove in the depth direction of the silicon substrate and a second embedded layer made of a material different from the first embedded layer formed in the groove,
When a required component is formed on the surface side of the silicon substrate, the second buried layer embedded in the alignment mark can be prevented from being etched by the first buried layer. In addition, it is possible to simultaneously prevent the etching of the components on the front side, particularly the components of the same material as the second buried layer, which are concerned when the components on the back surface of the silicon substrate are formed.
When the film thickness of the first buried layer is 5 nm or more, it sufficiently serves as an etching stopper and does not damage the components on the surface side.
When silicon nitride, polysilicon, amorphous silicon, or silicon containing carbon is used as the material of the first buried layer and silicon oxide is used as the material of the second buried layer, it is possible to distinguish between both front and back surfaces. A good alignment mark.

  According to the method for manufacturing a solid-state imaging device according to the present invention, the alignment mark is formed so that the surface of the buried layer made of an identifiable material on the semiconductor substrate is flush with the surface of the semiconductor substrate. The required constituent elements can be formed on both the front and back surfaces of the semiconductor substrate without causing the above.

  According to the method for manufacturing a semiconductor integrated circuit device according to the present invention, the alignment mark is formed so that the surface of the buried layer made of an identifiable material on the semiconductor substrate is flush with the surface of the semiconductor substrate. Necessary components can be formed on both the front and back surfaces of the semiconductor substrate without causing unevenness.

In the above manufacturing method, a silicon substrate is used as the semiconductor substrate, a groove is formed in the thickness direction of the substrate, and a material different from silicon, such as SiO, SiN, SiC, SiON, SiOC, SiCN, or polysilicon, is formed in the groove. By embedding a buried layer of the above material to form an alignment mark, an accurate alignment mark that can be identified from both the front and back surfaces can be formed.
In the above manufacturing method, by setting the aspect ratio (A / B ratio) of the groove for forming the alignment mark to 1.0 or more, an alignment mark that does not generate irregularities or voids on the exposed surface of the alignment mark is formed. be able to.

By using a SOI substrate and forming a groove in the silicon layer on one side from the main surface to the insulating layer that serves as an etching stop layer, and by embedding a buried layer in the groove to form an alignment mark, high reliability is achieved. Kotoga can be used to form a solid-state imaging device or a semiconductor integrated circuit device.
By forming the alignment mark so as to reach the back surface side from the front surface side of the finally obtained semiconductor substrate, alignment can be performed easily and accurately when components are formed on both the front and back surfaces of the substrate. .

In the above manufacturing method, when the alignment mark is formed with a multilayer structure of a thin film of a first material different from silicon and an embedded layer of a second material different from the first material, the other silicon layer particularly when an SOI substrate is used. In addition, the buried layer of the alignment mark is not removed in the step of removing the insulating layer.
By using any material of SiO, SiN, SiCN, SiC, SiOC, SiO or SiON as the first material, and using a material having an etching selectivity with respect to the thin film as the second material of the buried layer, an alignment mark having a multilayer structure Can be formed with high accuracy.
Further, when the thin film of the first material is formed excluding the side wall near the opening of the groove, the thin film of the first material does not extend to the substrate surface, and the flatness of the substrate surface can be ensured.

  When the alignment mark is formed in a square shape in which each side is separated when seen in a plan view, it is possible to prevent the occurrence of voids that are likely to occur at the four corners of the square shape.

Using an SOI substrate, a groove reaching the insulating layer is formed in one silicon layer, a second embedded layer made of a material different from silicon is formed in the groove except for the groove opening, and silicon and the above-described silicon are formed in the groove opening. By forming a first buried layer made of a material different from that of the second buried layer and forming an alignment mark, a second buried layer embedded in the alignment mark is formed when a required component is formed on the surface side of the silicon layer. Etching of the layer can be prevented by the first buried layer. In addition, when the constituent elements on the back surface of the silicon layer are formed, it is possible to prevent etching of constituent elements on the front surface side, which are concerned, in particular, constituent elements of the same material as the second buried layer.
By using any one of silicon nitride, polysilicon, amorphous silicon, and silicon containing carbon as the material of the first embedded layer and using silicon oxide as the material of the second embedded layer, the alignment mark can be formed with high accuracy. .

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment in which the solid-state imaging device according to the present invention is applied to a backside illumination type CMOS solid-state imaging device. FIG. 1 shows a schematic configuration of a main part including an imaging region in which pixels are arranged in a matrix and a peripheral circuit unit formed around the imaging region.
In the backside illuminated CMOS solid-state imaging device 1 according to the present embodiment, a unit pixel 5 composed of one photodiode PD and a plurality of MOS transistors Tr1 is formed in a matrix in an imaging region 3 of a semiconductor substrate, for example, a silicon semiconductor substrate 2. A plurality of peripheral circuit portions 6 each including a plurality of CMOS transistors are formed in the peripheral region 4.

  The semiconductor substrate 2 is thinned, and the photodiode PD is formed so as to extend from the front surface side to the back surface side of the semiconductor substrate 2. The CMOS transistor Tr2 in the peripheral circuit section 6 is also configured by forming a gate electrode 21 between a pair of source / drain regions formed on the semiconductor substrate 2 via a gate insulating film. A multilayer wiring layer 9 is formed on the surfaces of the imaging region 3 and the peripheral region 4 of the semiconductor substrate 2 via an interlayer insulating film 8. The multilayer wiring layer 9 may be formed so as to overlap the photodiode PD. Further, a support substrate 10 made of, for example, a silicon substrate is bonded to the wiring layer 9 via the adhesive layer 11 in order to maintain the mechanical strength of the solid-state imaging device. On the other hand, on the back side of the semiconductor substrate 2, a color filter 14 and an on-chip lens 15 corresponding to each pixel 5 are formed on the color filter 14 via an antireflection film 12. In the CMOS solid-state imaging device 1, light is irradiated to the photodiode PD from the back surface of the substrate through the on-chip lens 15.

  In the present embodiment, in particular, the alignment mark 17 in which both the front and back surfaces are flattened is formed on the semiconductor substrate 2. The alignment mark 17 is formed on the substrate surface side when forming components such as the photodiode PD and the MOS transistor Tr1 of each pixel 5, the CMOS transistor Tr2 of the peripheral circuit section 6, and the multilayer wiring layer 9 from the substrate surface side. It is used for pattern matching when forming components such as the color filter 14 and the on-chip lens 15 from the back side of the substrate in accordance with the pattern of the components. The alignment mark 17 is distinguishable from, for example, silicon of the semiconductor substrate 2 in a groove (so-called trench or via hole) 8 formed so as to reach the substrate rear surface from the substrate surface in the thickness direction (that is, depth direction) of the semiconductor substrate 2. A buried layer 19 made of an appropriate material is formed, and the front and back surfaces of the buried layer 19 are configured to be flush with the front and back surfaces of the semiconductor substrate 2.

  The alignment mark 17 may be formed in any part of the solid-state imaging device, but it is preferable to form 20 in a peripheral field region away from the imaging region 3 and the peripheral circuit unit 6. At the time of manufacture, the alignment mark 17 is used as a reference, that is, the alignment mark 17 is identified from the front surface side and the back surface side of the substrate, and pattern matching is performed. Each photodiode, MOS transistor, multilayer wiring layer, color filter, ON Components such as a chip lens are formed.

  The alignment mark 17 is made of a material different from silicon, for example, silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxide carbide (SiOC), silicon carbonitride (SiCN). , Polysilicon or the like.

The CMOS solid-state imaging device 1 according to the present embodiment can be configured using a so-called SOI substrate having silicon layers on both sides with an insulating layer interposed therebetween. The SOI substrate is formed of a normal SOI substrate in which one silicon layer is used as a supporting substrate and the other silicon layer of a thin film serving as an element forming portion is formed on an upper surface of the SOI substrate via an insulating layer. When an SOI substrate is used, a thin silicon layer corresponds to the semiconductor substrate 2 described above. At this time, the alignment mark 17 has a groove 18 formed by etching in a thin silicon layer using the insulating layer as an etching stop layer so as to reach the insulating layer from the surface, and an embedded layer of the above material different from silicon in the groove 18 19 is embedded. Components such as photodiode PD, MOS transistors Tr1, Tr2 and multilayer wiring layer 9 are formed from the surface side of the thin film silicon layer, and the supporting substrate 10 is bonded together, and then the other silicon layer, and hence the silicon substrate, is polished. The back surface of the thin silicon layer is exposed by etching or the like. Components such as the color filter 14 and the on-chip lens 15 are formed on the back side.
Note that when an SOI substrate is used, the solid-state imaging device 1 can be configured such that an insulating layer is finally left as necessary.

  FIG. 2 shows a specific example of the unit pixel 5 of the backside illumination type CMOS solid-state imaging device 1. In this example, a pixel isolation region 32 made of a p-type semiconductor region of the second conductivity type is formed so as to partition each pixel region 31 on a first conductivity type, eg, n-type silicon substrate 2. The n-type semiconductor substrate 2 in the pixel region 31 is formed of a p-type semiconductor region having a relatively low impurity concentration. A p-type semiconductor well region 33 is formed on the surface of the n-type semiconductor substrate 2 in the pixel region 31 so as to connect to the p-type pixel isolation region 32 and partially extend into the pixel region 31. The photodiode PD serving as a photoelectric conversion unit is formed of an n-type semiconductor substrate 2 surrounded by a p-type pixel isolation region 32 and a p-type semiconductor well region 33. That is, the photodiode PD is formed by the n-type semiconductor region 2A and the high impurity concentration n + semiconductor region 2B on the surface side thereof. A p + accumulation layer 34 made of a high impurity concentration p-type semiconductor region for suppressing dark current generation is formed at the interface on the surface side of the n + semiconductor region 2B. Further, in common with each pixel region 31, a p + accumulator made of a high impurity concentration p semiconductor region for suppressing dark current generation on the back surface of the n-type semiconductor substrate 2, that is, the interface on the back surface side of the n-type semiconductor region 2 A. The formation layer 35 is formed.

  Since the photodiode PD includes p + accumulation layers 34 and 35 on the front surface of the n + semiconductor region 2B and the back surface of the n semiconductor region 2A, the photodiode PD is configured as a so-called HAD (Hole Accumulation Diode) sensor. The photodiode PD is formed in a large area so as to cover the entire pixel region because the n semiconductor region 2A extends below the p-type semiconductor well region 33.

  On the other hand, the MOS transistor Tr 1 is formed in the p-type semiconductor well region 33. That is, when one pixel is composed of one photodiode PD and four MOS transistors, the MOS transistor Tr1 has a read transistor, a reset transistor, an amplifier transistor, and a vertical selection transistor. In FIG. 2, one n + source / drain region 37 is formed in the p-type semiconductor well region 33 in the vicinity of the photodiode, and the photodiode serving as one n + source / drain region 37 and the other source / drain region is formed. A gate electrode 7 is formed on the p-type semiconductor well region 33 between the n + semiconductor region 2B of the PD via a gate insulating film, and a read transistor Tr11 is formed. Corresponding n + source / drain regions 38 and 39 are formed in the other part of the p-type semiconductor well region 3, and a gate insulating film is formed on the p-type semiconductor well region 33 between the n + source / drain regions 38 and 39. Thus, the gate electrode 7 is formed, and other MOS transistors, that is, a reset transistor Tr12, an amplifier transistor Tr13, and a vertical selection transistor Tr14 are formed.

  A multilayer wiring 9 is formed on the surface of the semiconductor substrate 2 via an interlayer insulating film 8 made of, for example, a silicon oxide film, and a support substrate 10 made of, for example, a silicon substrate is bonded onto the interlayer insulating film 8. An antireflection film 12 is formed on the light irradiation surface 41 on the back surface of the semiconductor substrate 2, and an on-chip lens 15 is formed on the antireflection film 12 via a color filter 14.

Next, an embodiment of a method of manufacturing the backside illumination type CMOS solid-state imaging device 1 described above will be described with reference to FIGS.
In the present embodiment, first, as shown in FIG. 3A, an SOI substrate 54 having silicon layers 52 and 53 on both surfaces of an insulating layer 51 is used. Here, an SOI substrate 54 in which a silicon layer 53 is a silicon substrate and a thin silicon layer 52 is formed on the substrate 53 with an insulating layer 51 interposed therebetween is used. This insulating layer 53 becomes an etching stop layer in a later process of etching the silicon layer 52, and is formed of a material having an etching ratio different from that of silicon. In this example, the insulating layer 51 is formed of a silicon oxide layer.

  Next, as shown in FIG. 3B, a groove 18 having the same pattern as the alignment mark pattern is formed in one silicon layer (surface-side silicon layer) 52 of the SOI substrate 54 in the thickness direction of the silicon layer 52 (so-called depth direction). ) To form. That is, a groove having the same pattern as the alignment mark is formed so as to reach a required region of the silicon layer 52, in this example, the region 20 corresponding to the field region in the peripheral portion of each imaging chip so as to reach the back surface 52b from the front surface 52a of the silicon layer 52 18 is formed. At this time, the insulating layer 51 acts as an etching stop layer, and the groove 18 is formed by etching up to the insulating layer 51.

Next, as shown in FIG. 4C, a material that can be distinguished from silicon and has an etching ratio with silicon, for example, a silicon oxide film 19a in this example, is buried in the groove 18 of the silicon layer 52. At this time, the silicon oxide film 19 a fills the trench 18 and is also deposited on the surface of the silicon layer 52.
Next, as shown in FIG. 4D, the silicon oxide film 19a on the upper surface of the silicon layer 52 is removed by etching back or the like to form the buried layer 19 with the silicon oxide film 19a, thereby forming the alignment mark 17. At this time, the surface of the alignment mark 17 is flush with the surface 52a of the silicon layer.

  Next, as shown in FIG. 5E, the pixel separation region, the semiconductor well region, the photodiode PD, the MOS transistor Tr1, and the CMOS transistor in the peripheral region 4 from the surface side to the imaging region 3 of the silicon layer 52 with the alignment mark 17 as a reference. Tr2 and the like are formed, and a multilayer wiring layer 9 is formed on the imaging region 3 and the peripheral region 4 via the interlayer insulating film 8 with the alignment mark 17 as a reference.

Next, as shown in FIG. 5F, for example, an organic film or an adhesive layer 11 made of an SOG material is formed on the interlayer insulating film 8 on the silicon layer 52 side in order to bond the support substrate 10.
Next, as shown in FIG. 6G, the support substrate 11 made of, for example, silicon Si or silicon oxide SiO ₂ and the interlayer insulating film 8 on the SOI substrate 54 are bonded via the adhesive layer 11.

Next, as shown in FIG. 6H, the SOI substrate 54 is inverted.
Next, as shown in FIG. 7I, the silicon layer (silicon substrate) 53 is removed with high precision while taking the etching selectivity with the silicon oxide layer 51 by polishing, etching or the like so that the photodiode PD faces the surface layer. Then, the silicon oxide layer 51, which is an etching stop layer, is removed while maintaining an etching selectivity with silicon. As a result, the back surface 52b of the thin silicon layer 52 is exposed.

  Next, as shown in FIG. 7J, the antireflection film 12 is formed on the entire back surface 52b of the thin silicon layer 52, and the color filter 14 is aligned with the photodiode PD with the alignment mark 17 as a reference. And the on-chip lens 15 is formed.

  Next, although not shown, the wafer is separated from the scribe line to obtain each imaging chip, that is, the back-illuminated CMOS solid-state imaging device 1 shown in FIG.

  In addition to forming the alignment mark 17 for each imaging chip, it is also possible to form the alignment mark 17 at a plurality of locations that do not affect the imaging device for each one-shot exposure area of the stepper in the exposure process. The alignment mark 17 may be formed on a scribe line for separating each imaging chip.

In the above example, the components formed from the back surface 52b side are the color filter 14 and the on-chip lens 15. However, in principle, the components such as the photodiode PD formed from the front surface 52a side are formed from the back surface 52b side. It is also possible to do.
In the above example, the solid-state imaging device 1 is manufactured using the SOI substrate, but it can be manufactured similarly using a silicon bulk substrate. In that case, the groove 18 is formed to a certain depth of the substrate, and when the silicon substrate is thinned, the back surface of the substrate is polished and etched so that the photodiode PD is on the surface layer.

According to the back-illuminated CMOS solid-state imaging device 1 according to the above-described embodiment, the surface side is provided by providing the alignment mark 17 with the embedded layer 19 formed on the silicon substrate 2 so as to have the same surface as both surfaces of the substrate. When forming components such as photodiode PD, MOS transistor Tr1, CMOS transistor Tr2 and multilayer wiring layer 9 from the back, and when forming components such as color filter 14 and on-chip lens 15 from the back side These constituent elements can be formed with high accuracy so that there is no occurrence of uneven application of the material and no pattern defect occurs. Further, by embedding the buried layer 19 with a material other than silicon that can be optically contrasted to form the alignment mark 17, the front and back surfaces can be aligned in a normal exposure apparatus. Therefore, it is possible to provide a highly reliable back-illuminated CMOS solid-state imaging device that has no pattern defects in the constituent elements.
When the back-illuminated CMOS solid-state imaging device 1 is configured using the SOI substrate 54, the insulating layer 51 of the SOI substrate 54 acts as an etching blocking layer when forming the groove 18, and the groove 18 is formed at a constant depth. Can be formed. Then, since the buried layer is buried in the groove 18 to form the alignment mark 17, when the silicon layer 53 on the front surface side is thinned, irregularities are generated on the back surface layer of the silicon layer 42 of the thin film on the back surface side. Instead, it becomes a flattened substrate surface. Therefore, it is possible to provide a highly reliable back-illuminated CMOS solid-state imaging device that has no pattern defects in the constituent elements.

Next, the structure of the alignment mark 17 will be further described with reference to FIGS. FIG. 8A shows a cross-sectional structure of the alignment mark 17 and corresponds to the process of FIG. 3D described above. A groove (so-called trench or via hole) 18 is formed by etching from the surface side of the silicon layer 52 where the photodiode PD is formed. When the SOI substrate 54 is used, the depth of the groove 18 can be controlled with high accuracy because the etching selectivity with the insulating layer (for example, SiO ₂ layer) 51 can be obtained.

After the groove 18 is formed, a material other than silicon, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride ( A material such as SiCN) or polysilicon is buried in the groove 18 by, for example, a CVD method or a coating method. At this time, in order not to generate a step due to the groove 18, the aspect ratio A: B (see FIG. 10) of the alignment mark 17 is 1: 1 or more (that is, the groove depth A with respect to the groove width B of the groove 18). The ratio is preferably set to A / B is 1.0 or more. This is due to the following reason. When the aspect ratio (A / B ratio) is 1.0 or more, as shown in FIG. 10A, the material of the buried layer 19 is formed with a film thickness (A / 2) that is ½ of the groove depth A. No step occurs. On the other hand, when the aspect ratio (A / B ratio) is smaller than 1.0, as shown in FIG. 10B, the material of the buried layer 19 is ½ of the groove depth A (A / 2). When forming a film, a step is generated.
The upper limit of the aspect ratio of the alignment mark 17 is preferably set to A / B = 50 from the characteristic limit of embedding an insulating film.
The material film other than the alignment mark portion formed on the surface of the silicon layer 52 is removed by, for example, a CMP (Chemical Mechanical Polishing) method or an EB (etchback) method (see FIGS. 4C and D). .

As described above, by selecting the aspect ratio (A / B) of the groove 18 of the alignment mark 17 to be 1.0 or more, the alignment mark 17 is exposed even if the silicon is thinned from the back side and the alignment mark 17 is exposed. No unevenness occurs on the exposed surface of 17. Further, since contrast with silicon can be obtained, there is no defect in the coating film system at the time of forming the back surface, and alignment with the pattern on the front surface side can be performed with high accuracy.
In FIG. 10, depending on the case, the groove 18 may be formed by slightly over-etching so as to enter the insulating layer 51, and the alignment mark may be projected. This may provide better alignment.

  8B and 8C show examples of pattern shapes when the alignment mark 17 of FIG. 8A is viewed from above. The alignment mark 17 in FIG. 8B is a case where a plurality of linear portions 17a having a long and narrow rectangular shape are formed in parallel. The alignment mark 17 in FIG. 8C is a case where the pattern shape is an array of a plurality of circular granular portions 17b. In this case, a pattern shape is formed by arranging a plurality of granular rows 17bb in which a plurality of granular portions 17b are arranged in the vertical direction, and a plurality of (for example, five) granular rows 17bb are formed on one linear portion 17a in FIG. 8B. Equivalent to. When the aspect ratio A / B is increased so as not to cause a step as shown in FIG. 10B, the burying of the silicon oxide film 19a may become severe. In such a case, it is preferable to apply a pattern formed by circular granular portions 17b shown in FIG. 8C. By arranging the granular portions 17a, it is detected as a pattern in one elongated rectangle.

  When the aspect ratio A / B is large, as shown in FIG. 9A, the alignment mark 17 can be formed in an annular rectangular pattern excluding the middle. Furthermore, in the pattern shown in FIG. 9A, there is a risk of voids occurring at the four corners Q. At this time, as shown in FIG. 9B, in order to suppress the generation of voids, the alignment mark 17 can be a rectangular pattern from which the four corner portions are deleted. In this case, the silicon oxide film 17a is easily embedded in each side.

  FIG. 11 shows another embodiment of the alignment mark portion of the solid-state imaging device according to the present invention. When the alignment mark 17 shown in FIG. 8A described above is formed by being embedded with a silicon oxide film, during the process of thinning the back surface side of the SOI substrate 54, when etching the silicon layer 51 as an etching blocking layer, There is a possibility that a part of the silicon oxide layer 52 to be the alignment mark 17 is etched at the same time. A configuration suitable for this measure is shown in FIG.

In the present embodiment, a thin film 57 made of a first material having an etching selectivity with respect to the silicon oxide layer 51 is provided on the inner surface of the groove 18 formed on the side of one silicon layer 52 to be an element forming portion of the SOI substrate 54 (liner ( Then, a buried layer 19 made of a second material different from the thin film 57 made of the first material is buried in the groove 17 to form an alignment mark 17 having a multilayer structure. As the first material, an insulating material such as SiN, SiC, or SiOC can be used. As the second material, a material different from the first material and having an etching selectivity with the first material, in this example, SiO can be used. When the insulating layer 51 of the SOI substrate 54 is formed of an insulating layer other than the SiO ₂ layer, SiO can be used as the first material. The first material and the second material are not limited to the above materials.
According to the alignment mark 17 having the multilayer structure of the present embodiment, when the silicon oxide layer 51 is etched from the back surface of the SOI substrate 54, the recon oxide film 19a as the buried layer 19 is not etched, and the normal alignment mark 17 is normal. An alignment mark 17 can be formed.

FIG. 12 shows another embodiment of the alignment mark portion of the solid-state imaging device according to the present invention. In the present embodiment, the multi-layered alignment mark 17 shown in FIG. 11 is formed by removing the first material thin film 57 in the vicinity of the opening in the groove 18.
According to the alignment mark 17 of the multilayer structure of the present embodiment, even when the thin film 57 is formed to extend partially on the surface of the silicon layer 52 in the formation of the thin film 57 of the first material, the groove is finally formed. Since the thin film 57 is not formed in the vicinity of the opening in 18, the flatness of the surface of the silicon layer 52 can be ensured.

13 to 16 show still another embodiment of the solid-state imaging device according to the present invention, that is, a back-illuminated CMOS solid-state imaging device similar to that described above. In the figure, only the alignment mark portion is shown together with its manufacturing process.
When the alignment mark 17 is formed by being embedded with a silicon oxide film, the silicon oxide film 19a embedded in the groove 18 to be the alignment mark 17 is etched in the step of forming the element and the wiring layer after the alignment mark is formed. The film may be peeled off and the interlayer film may be etched. Further, when the back surface element is formed, the SOI substrate 54 on which the element, the multilayer wiring layer and the like are formed on the surface side of the silicon layer 52 and the support substrate 10 are bonded together, and then the back surface grinding process (the silicon substrate is mechanically bonded). A chemical mechanical polishing (CMP) process after the back grinding process, a chemical treatment for removing Si, and then a silicon oxide layer 51 which is an etching prevention layer of the SOI substrate. Peel off using highly concentrated hydrofluoric acid. When the silicon oxide layer 51 is removed by this hydrofluoric acid, as shown in FIG. 17, the silicon oxide film 19a in the groove 18 to be the alignment mark 17 is etched, and further, an interlayer formed on the surface side of the silicon layer 52. Even the surface forming layer 79 made of the insulating film and the multilayer wiring may be etched to form the cavity 82. The present embodiment is suitable for this countermeasure.

  That is, in the present embodiment, first, as shown in FIG. 13A, an SOI substrate 4 having silicon layers 52 and 53 on both sides with a silicon oxide layer 51 similar to the above is used. A thermal silicon oxide film 71, a silicon nitride film 72, and a silicon oxide film 73 are formed on the surface of one silicon layer 52 of the SOI substrate 54, and a resist having a desired pattern for forming an alignment mark on the silicon oxide film 73. A mask (not shown) is formed. The resist mask is formed by forming a photoresist film and patterning using a lithography method. Through this resist mask, a so-called hard mask 75 made of a silicon oxide film 73 and a silicon nitride film 72 formed in the lower layer is patterned by a dry etching method to form an opening 74 corresponding to the pattern of the alignment mark. The hard mask 75 at this time is necessary to form the deep groove 18 described later.

  Next, as shown in FIG. 13B, the silicon layer 72 that becomes an active layer for forming an element is selectively etched through the hard mask 75 including the silicon oxide film 73 and the silicon nitride film 72 to reach the silicon oxide layer 51. A groove 18 is formed. Then, the hard mask 65 is peeled off such that a part of the silicon nitride film 72 remains thin by, for example, chemical treatment. Note that the hard mask 75 may be subjected to the next process without being peeled off.

  Next, as shown in FIG. 13C, the trench 18 is filled with, for example, a low pressure TEOS (organosilane) film, that is, a low pressure CVD silicon oxide film 19a. At this time, the silicon oxide film 18a is also deposited on the silicon nitride film 72 used as the hard mask.

  Next, as shown in FIG. 14D, only the silicon oxide film 18a in the trench 18 is left, and the silicon oxide film 19a deposited on the surface is used as a hard mask by CMP (Chemical Mechanical Polishing) method. Polishing is performed until the used silicon nitride film 72 is exposed.

  Next, as shown in FIG. 14E, a chemical solution treatment such as hydrofluoric acid is performed to remove a part of the silicon oxide film 19a embedded in the groove 18 to a required depth. In this example, the surface of the silicon oxide film 19 a embedded in the groove 18 is etched to the extent that the silicon layer 52 on the SOI substrate 54 side is exposed, and a step 66 is formed in the opening of the groove 18.

  Next, as shown in FIG. 14F, the etching selectivity ratio between the silicon oxide layer 51 serving as an etching stop layer of the SOI substrate 54 and the silicon oxide film 18a buried in the groove 18 is filled on the entire surface so as to fill the step 66 of the groove 18. A different material layer, for example, a silicon nitride film 78 is formed. In this example, the silicon nitride film 78 is formed by using a low pressure CVD method.

  Next, as shown in FIG. 15G, for example, the silicon nitride film 78 on the surface of the silicon layer 52 and the silicon nitride film 52 used as a hard mask are formed so that the silicon nitride film 78 in the groove 18 (that is, near the groove opening) remains. Peel off by hot phosphoric acid treatment. The film thickness of the remaining silicon nitride film 78 is set to 5 nm or more that can sufficiently serve as an etching stopper when a silicon oxide film 19a described later is etched. The upper limit of the thickness of the silicon nitride film 78 can be about 1000 nm in consideration of alignment mark variations and SiNCVD characteristics. It should be noted that the present invention is not limited to hot phosphoric acid treatment, and a mixed liquid such as glycerol hydrofluoric acid or ethylene glycol hydrofluoric acid may be used. In this way, the trench 18 is filled with the silicon oxide film 19a and the silicon nitride film 78, and the alignment mark 17 is formed.

  Next, an element isolation region is formed in the silicon layer 52 using the alignment mark 17, and an element (for example, a MOS transistor, a photodiode, or the like) is formed on the surface side of the silicon layer 52 as shown in FIG. 15H. A so-called surface formation layer 79 in which a multilayer wiring is formed through a gate insulating film, a gate electrode, and an interlayer pre-insulating film is formed.

Next, as shown in FIG. 15I, the support substrate 10 is bonded to the surface formation layer 79 side of the SOI substrate 54 via the adhesive layer 11.
Next, as shown in FIG. 16J, a back surface grinding process, a CMP process, an etching process using a chemical solution, and the like are performed, and the silicon layer 53 is removed until the silicon oxide layer 51 as an etching prevention layer is exposed.

  Next, the silicon oxide layer 51 is removed by etching. When this etching is performed with high concentration hydrofluoric acid, as shown in FIG. 16K, the bottom of the groove 18 is exposed and the silicon oxide film 19a embedded in the groove 18 is etched. Since the silicon nitride film 78 is buried on the side, the silicon nitride film 68 prevents further penetration of the etchant and does not etch the surface forming layer 79.

  Thereafter, as described above, an antireflection film is formed on the back side of the silicon layer 52, and a color filter and an on-chip lens are formed so as to be aligned with the photodiode PD with the alignment mark 17 as a reference.

  As a result, even if the SOI substrate is thinned from the back side and the alignment mark 17 is exposed, the alignment mark 17 can be contrasted with silicon (Si), so that the coating film system is not defective and does not occur when the back side is formed. Precise alignment with the surface pattern.

According to the backside illumination type CMOS solid-state imaging device according to the present embodiment, by providing the alignment mark 17 with the embedded layers 19a and 78 formed on the silicon layer 52 so as to have the same surface as the substrate surface, from the front surface side. When forming components such as a photodiode, a MOS transistor, and a surface forming layer 79 of a multilayer wiring layer, forming these components with high accuracy that does not cause uneven coating of the coating material and does not cause pattern defects. Can do. Further, by embedding the buried layers 19a and 78 with a material other than silicon capable of obtaining an optical contrast, the alignment mark 17 is formed, whereby the front and back surfaces can be aligned in a normal exposure apparatus. A color filter and an on-chip lens are formed on the back surface side, but even if a cavity is exposed in the alignment mark 17 at this time (see FIG. 16K), no major problem occurs in the pattern accuracy of the color filter and the on-chip lens. Therefore, it is possible to provide a highly reliable back-illuminated CMOS solid-state imaging device that has no pattern defects in the constituent elements.
In this embodiment, as described above, the silicon nitride film 78 is buried together with the silicon oxide film 19a in the groove 18 constituting the alignment mark, so that an element such as a photodiode or a MOS transistor, a multilayer wiring, etc. When the surface formation layer 79 is formed, the silicon oxide film 19a embedded in the alignment mark 17 can be prevented from being etched. The flatness of the alignment mark can be maintained. Furthermore, etching of the surface forming layer 79, particularly its interlayer insulating film, which is a concern when forming components on the back surface (antireflection film, color filter, on-chip lens, etc.) can be prevented at the same time.

  FIG. 18 shows still another embodiment of the alignment mark portion of the solid-state imaging device according to the present invention. In the present embodiment, as shown in FIG. 18A (corresponding to the step of FIG. 16J), the groove 18 is formed in the silicon layer 52, the silicon nitride film 78 is embedded in the vicinity of the opening on the surface side of the groove 18, and the groove A silicon nitride film is also formed on the inner wall of 18, and a silicon oxide film 19 a is buried in the groove 18 so as to be surrounded by the silicon nitride films 78 and 80, thereby forming an alignment mark 17. In this case, the bottom of the silicon oxide film 19 a is also covered with the silicon nitride film 80, and the alignment mark 17 is formed on the same surface as the surface of the silicon layer 52.

  Next, as shown in FIG. 18B, the silicon oxide layer 51 is removed with high-concentration hydrofluoric acid. At this time, even if the silicon nitride film 80 formed on the inner wall of the alignment mark 17, particularly on the groove bottom (see reference numeral 83 in FIG. 18B) breaks down and the embedded silicon oxide film 19 a is etched, The formed silicon nitride film 78 can suppress intrusion of hydrofluoric acid into the surface formation layer 79.

According to the back-illuminated CMOS solid-state imaging device according to the embodiment of FIG. 18, by providing the alignment mark 17 with the embedded layers 19a, 78, and 80 formed on the silicon layer 52 so as to have the same surface as both surfaces of the substrate. When forming components such as photodiodes, MOS transistors, and surface forming layer 79 of the multilayer wiring layer from the front side, and when forming components such as a muller filter and an on-chip lens from the back side Therefore, it is possible to form these constituent elements with high accuracy so that there is no occurrence of coating unevenness and pattern defects do not occur. Further, by embedding the buried layers 19a and 78 with a material other than silicon capable of obtaining an optical contrast, the alignment mark 17 is formed, whereby the front and back surfaces can be aligned in a normal exposure apparatus. A color filter and an on-chip lens are formed on the back surface side, but even if a cavity is exposed in the alignment mark 17 at this time (see FIG. 16K), no major problem occurs in the pattern accuracy of the color filter and the on-chip lens. Therefore, it is possible to provide a highly reliable back-illuminated CMOS solid-state imaging device that has no pattern defects in the constituent elements.
In this embodiment, since the silicon nitride film 78 is embedded so as to surround the silicon oxide film 19a together with the silicon oxide film 19a in the groove 18 constituting the alignment mark as described above, the photodiode It is possible to prevent the silicon oxide film 19a embedded in the alignment mark 17 from being etched when the surface formation layer 79 such as an element such as a MOS transistor or a multilayer wiring is formed. The flatness of the alignment mark can be maintained. Furthermore, even if the silicon nitride film 80 at the bottom of the groove breaks down as shown in FIG. 18B when forming the constituent elements on the back surface (antireflection film, color filter, on-chip lens, etc.) (reference numeral in FIG. 18B). 83), etching of the surface forming layer 79, particularly the interlayer insulating film, which is concerned by the silicon nitride film 78, can be prevented at the same time. At this time, even if the cavity is exposed in the alignment mark 17 (see FIG. 18B), no significant problem occurs in the pattern accuracy of the color filter and the on-chip lens.

  Although the silicon nitride film 78 is used in the above example, a polysilicon film or an amorphous silicon film can be used instead of the silicon nitride film 78. Further, instead of the silicon nitride film 78, a film containing carbon such as SiOC or SiC can be used.

  In the above-described embodiment, the present invention is applied to the back-illuminated CMOS solid-state image sensor. However, the present invention can also be applied to other solid-state image sensors, for example, a back-illuminated CCD solid-state image sensor.

  The present invention can also be applied to a semiconductor integrated circuit device in which semiconductor elements and / or wiring layers are formed on both sides of a semiconductor substrate, for example, a silicon substrate. When applied to a semiconductor integrated circuit device, the alignment mark 17 is the same as the above example except that the specific configurations of the semiconductor elements and wiring layers formed on both surfaces of the semiconductor substrate are different.

  FIG. 19 shows an embodiment when the present invention is applied to a semiconductor integrated circuit device. In the semiconductor integrated circuit device 61 according to the present embodiment, an alignment mark 17 in which a buried layer 19 is embedded in a groove 18 in the thickness direction is formed on a thinned silicon substrate 62, and the substrate is based on the alignment mark 17. A wiring layer 66 having a multilayer structure (three-layer structure in this example) is formed on the surface side of 62 through a MOS transistor group Tr31 having a gate electrode 64 and an interlayer insulating film 65, and the substrate is formed with reference to the alignment mark 17 A wiring layer 69 having a multilayer structure (three-layer structure in this example) is formed on the back surface side of 62 through a MOS transistor group Tr32 having a gate electrode 67 and an interlayer insulating film 68.

  In the example of FIG. 19, the present invention is applied to a semiconductor integrated circuit device having a structure in which a MOS transistor group and a multilayer wiring layer are formed on both sides of the silicon substrate 62. The present invention can also be applied to various types of semiconductor integrated circuit devices such as forming a transistor or other semiconductor element and forming a wiring layer on the other surface side.

  Such a semiconductor integrated circuit device and a method for manufacturing the same also exhibit the same operations and effects as those of the solid-state imaging device described above.

It is a block diagram which shows one Embodiment of the solid-state image sensor which concerns on this invention. It is sectional drawing which shows the specific structural example of 1 pixel of the backside illumination type solid-state image sensor which concerns on this invention. FIGS. 3A and 3B are process diagrams (part 1) illustrating an embodiment of a method for producing a solid-state imaging device according to the present invention. FIGS. C, D It is process drawing (the 2) which shows one Embodiment of the manufacturing method of the solid-state image sensor which concerns on this invention. E, F It is process drawing (the 3) which shows one Embodiment of the manufacturing method of the solid-state image sensor concerning this invention. G and H are process diagrams (part 4) showing an embodiment of a method for producing a solid-state imaging device according to the present invention. I, J is a process diagram (part 5) showing an embodiment of a method for producing a solid-state imaging device according to the present invention. A It is sectional drawing of the principal part of the alignment mark which concerns on this invention. B is a plan view showing an example of an alignment mark according to the present invention. FIG. It is a top view which shows the other example of the alignment mark which concerns on C this invention. A is a top view which shows the other example of the alignment mark which concerns on this invention. B is a plan view showing another example of the alignment mark according to the present invention. FIG. It is sectional drawing with which it uses for description of the aspect-ratio of the groove | channel in A and B alignment mark. It is sectional drawing which shows an example of the alignment mark of the multilayered structure which concerns on this invention. It is sectional drawing which shows the other example of the alignment mark of the multilayered structure which concerns on this invention. AC is process drawing (the 1) which shows other embodiment of the manufacturing method of the solid-state image sensor which concerns on this invention. DF is process drawing (the 2) which shows other embodiment of the manufacturing method of the solid-state image sensor which concerns on this invention. GI is process drawing (the 3) which shows other embodiment of the manufacturing method of the solid-state image sensor which concerns on this invention. J to K are process diagrams (part 4) illustrating another embodiment of the method for manufacturing a solid-state imaging device according to the present invention. It is sectional drawing with which it uses for description of this invention. A to B are process diagrams illustrating still another embodiment of a method for manufacturing a solid-state imaging device according to the present invention. 1 is a configuration diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention.

Explanation of symbols

  1 .. Backside illuminated solid-state imaging device 2.. Semiconductor substrate 3.. Imaging area 4.. Peripheral region 5.. Pixel part 6.. Peripheral circuit part 7, 21. 8 .. Interlayer insulating film, 9 .. Multi-layer wiring layer, 10.. Support substrate, 11 .. Adhesive layer, 12 .. Antireflection film, 14 .. Color filter, 15. ... Alignment mark, 18 .. groove, 19 .. buried layer, 20 .. field region, PD, photodiode, Tr1, Tr2 .. MOS transistor, Tr13, Tr14 .. MOS transistor group, 51 .. insulating layer, 52, 53 .. Silicon layer, SOI substrate... 54, 57 .. Thin film, 61 .. Semiconductor integrated circuit device, 62 .. Semiconductor substrate, 64, 67 .. Gate electrode, 65, 68. 66, 69 ... Multi-layer structure Wiring layer, 71 ... silicon thermal oxide film, 72 ... silicon nitride film, 73 ... silicon oxide film, 75 ... hard mask, 78, 80 ... silicon nitride film, 79 ... surface layer

Claims (58)

The semiconductor substrate is formed of an embedded layer made of a material distinguishable from the semiconductor substrate, and an alignment mark is formed with the surface of the embedded layer being the same as the surface of the semiconductor substrate,
A solid-state imaging device, characterized in that constituent elements formed with reference to the alignment mark are provided on the front surface side and the back surface side of the semiconductor substrate. A silicon substrate is used as the semiconductor substrate,
The solid-state imaging device according to claim 1, wherein the alignment mark is configured by forming a buried layer made of a material different from silicon in a groove formed in the thickness direction on the silicon substrate. The solid-state imaging device according to claim 2, wherein the material different from silicon is any one of SiO, SiN, SiC, SiON, SiOC, SiCN, and polysilicon. The solid-state imaging device according to claim 1, wherein an aspect ratio of a groove depth to an opening width or an opening diameter of the groove forming the alignment mark is 1 or more. An SOI substrate having silicon layers on both sides of the insulating layer is used,
The semiconductor substrate is formed with one silicon layer after removing at least the other silicon layer of the SOI substrate;
2. The solid-state imaging according to claim 1, wherein the alignment mark is formed by the embedded layer embedded in a groove reaching the insulating layer serving as an etching prevention layer from a main surface of one silicon layer. element. The solid-state imaging device according to claim 1, wherein the alignment mark is formed so as to reach the back surface side from the front surface side of the semiconductor substrate. A silicon substrate is used as the semiconductor substrate,
The alignment mark includes a thin film made of a first material different from silicon formed on the inner surface of the groove in the depth direction of the silicon substrate, and a buried layer made of a second material different from the first material embedded in the groove. The solid-state imaging device according to claim 1, wherein the solid-state imaging device has a multilayer structure. The solid-state imaging device according to claim 7, wherein the thin film of the first material of the alignment mark having the multilayer structure is formed except for a side wall portion in the vicinity of the opening of the groove. As the first material of the thin film, any material of SiO, SiN, SiCN, SiC, SiOC, SiO or SiON is used,
The solid-state imaging device according to claim 7, wherein the second material of the buried layer is made of a material having an etching selectivity with respect to the thin film. The semiconductor substrate is formed with one silicon layer after the other silicon layer and the insulating layer of the SOI substrate are removed,
The solid-state imaging device according to claim 5, wherein the alignment mark is formed on the semiconductor substrate. A semiconductor substrate is formed with one silicon layer after the other silicon layer is removed leaving the insulating layer of the SOI substrate;
The solid-state imaging device according to claim 5, wherein the alignment mark is formed on the semiconductor substrate. The solid-state imaging device according to claim 1, wherein the alignment mark is formed in a square shape in which each side is separated in plan view. A silicon substrate is used as the semiconductor substrate,
The alignment mark is a first buried layer made of a material different from silicon formed on the opening side of the groove in the depth direction of the silicon substrate, and a second buried layer made of a material different from the first buried layer formed in the groove. It is comprised by these. The solid-state image sensor of Claim 1 characterized by the above-mentioned. The solid-state imaging device according to claim 13, wherein the film thickness of the first buried layer is 5 nm or more. The solid-state imaging device according to claim 13, wherein any one of silicon nitride, polysilicon, amorphous silicon, and silicon containing carbon is used as a material for the first buried layer. The semiconductor substrate is formed of an embedded layer made of a material distinguishable from the semiconductor substrate, and an alignment mark is formed with the surface of the embedded layer being the same as the surface of the semiconductor substrate,
2. A semiconductor integrated circuit device according to claim 1, wherein components formed with reference to the alignment mark are provided on a front surface side and a back surface side of the semiconductor substrate. A silicon substrate is used as the semiconductor substrate,
The semiconductor integrated circuit device according to claim 16, wherein the alignment mark is configured by forming a buried layer made of a material different from silicon in a groove formed in the thickness direction in the silicon substrate. The semiconductor integrated circuit device according to claim 16, wherein the material different from silicon is any one of SiO, SiN, SiC, SiON, SiOC, SiCN, and polysilicon. The semiconductor integrated circuit device according to claim 16, wherein an aspect ratio of a groove depth to an opening width or an opening diameter of the groove forming the alignment mark is 1 or more. An SOI substrate having silicon layers on both sides of the insulating layer is used,
The semiconductor substrate is formed with one silicon layer after removing at least the other silicon layer of the SOI substrate;
17. The semiconductor integrated circuit according to claim 16, wherein the alignment mark is formed of the buried layer buried in a groove reaching the insulating layer serving as an etching stop layer from the main surface of one silicon layer. Circuit device. The semiconductor integrated circuit device according to claim 16, wherein the alignment mark is formed so as to reach the back surface side from the front surface side of the semiconductor substrate. A silicon substrate is used as the semiconductor substrate,
The alignment mark includes a thin film made of a first material different from silicon formed on the inner surface of the groove in the depth direction of the silicon substrate, and a buried layer made of a second material different from the first material embedded in the groove. The semiconductor integrated circuit device according to claim 16, wherein the semiconductor integrated circuit device has a multilayer structure. 23. The semiconductor integrated circuit device according to claim 22, wherein the thin film of the first material of the alignment mark having the multilayer structure is formed except for a side wall portion in the vicinity of the opening of the groove. As the first material of the thin film, any material of SiO, SiN, SiCN, SiC, SiOC, SiO or SiON is used,
23. The semiconductor integrated circuit device according to claim 22, wherein a material having an etching selectivity with respect to the thin film is used as the second material of the buried layer. The semiconductor substrate is formed with one silicon layer after the other silicon layer and the insulating layer of the SOI substrate are removed,
The semiconductor integrated circuit device according to claim 20, wherein the alignment mark is formed on the semiconductor substrate. A semiconductor substrate is formed with one silicon layer after the other silicon layer is removed leaving the insulating layer of the SOI substrate;
The semiconductor integrated circuit device according to claim 20, wherein the alignment mark is formed on the semiconductor substrate. The semiconductor integrated circuit device according to claim 16, wherein the alignment mark is formed in a square shape in which each side is separated as viewed in a plan view. A silicon substrate is used as the semiconductor substrate,
The alignment mark is a first buried layer made of a material different from silicon formed on the opening side of the groove in the depth direction of the silicon substrate, and a second buried layer made of a material different from the first buried layer formed in the groove. The semiconductor integrated circuit device according to claim 16, comprising: The semiconductor integrated circuit device according to claim 28, wherein the film thickness of the first buried layer is 5 nm or more. 29. The semiconductor integrated circuit device according to claim 28, wherein any one of silicon nitride, polysilicon, amorphous silicon, and silicon containing carbon is used as a material for the first buried layer. Forming an alignment mark on a semiconductor substrate, which is made of a buried layer made of a material distinguishable from the semiconductor substrate, and the surface of the buried layer is flush with the surface of the semiconductor substrate;
A method of manufacturing a solid-state imaging device, comprising: forming components on the front surface side and the back surface side of a semiconductor substrate having a required thickness finally obtained from the semiconductor substrate with reference to the alignment mark. A silicon substrate is used as the semiconductor substrate,
32. The solid-state imaging device according to claim 31, further comprising a step of forming a groove in the thickness direction in the silicon substrate, forming a buried layer of a material different from silicon in the groove, and forming the alignment mark. Manufacturing method. 33. The method of manufacturing a solid-state imaging device according to claim 32, wherein any material different from silicon is SiO, SiN, SiC, SiON, SiOC, SiCN, or polysilicon. The method for manufacturing a solid-state imaging device according to claim 32, wherein an aspect ratio of the groove for forming the alignment mark is 1 or more. An SOI substrate having silicon layers on both sides of an insulating layer is used as the semiconductor substrate,
Forming a groove reaching the insulating layer from the main surface of the one silicon layer, using the insulating layer as an etching stop layer in one silicon layer to be a semiconductor substrate having a required thickness finally obtained;
32. The method of manufacturing a solid-state imaging element according to claim 31, further comprising a step of forming the buried layer in the groove to form the alignment mark. 32. The method of manufacturing a solid-state imaging device according to claim 31, wherein the alignment mark is formed so as to reach from the front surface side to the back surface side of the finally obtained semiconductor substrate. A silicon substrate is used as the semiconductor substrate,
Forming a groove in the depth direction in the silicon substrate;
A thin film of a first material different from silicon is formed on the inner surface of the groove, and then a buried layer of a second material different from the first material is buried in the groove to form a multi-layer alignment mark. The manufacturing method of the solid-state image sensor of Claim 31. 38. The method of manufacturing a solid-state imaging device according to claim 37, wherein the thin film of the first material of the alignment mark having the multilayer structure is formed except for a side wall portion in the vicinity of the opening of the groove. As the first material of the thin film, any material of SiO, SiN, SiCN, SiC, SiOC, SiO or SiON is used,
38. The method of manufacturing a solid-state imaging device according to claim 37, wherein a material capable of obtaining an etching selectivity with respect to the thin film is used as the second material of the buried layer. 36. The method of manufacturing a solid-state imaging device according to claim 35, wherein after the alignment mark is formed, the other silicon layer and the insulating layer of the SOI substrate are removed to leave one silicon layer. 36. The method of manufacturing a solid-state imaging device according to claim 35, wherein after the alignment mark is formed, the other silicon layer of the SOI substrate is removed to leave the insulating layer and one silicon layer. 32. The method of manufacturing a solid-state imaging device according to claim 31, wherein the alignment mark is formed in a square shape with each side being separated when viewed in plan. Using an SOI substrate having silicon layers on both sides of the insulating layer,
Forming a groove reaching the insulating layer from the main surface of the one silicon layer, using the insulating layer as an etching stop layer, in the one finally obtained silicon layer having a required thickness;
Forming a second buried layer made of a material different from silicon except for the groove opening in the groove;
Forming a first buried layer of a material different from silicon and the second buried layer in the groove opening portion,
32. The method of manufacturing a solid-state imaging device according to claim 31, wherein an alignment mark is formed by the groove and the first and second embedded layers in the groove. As a material for the first buried layer, any one of silicon nitride, polysilicon, amorphous silicon, and silicon containing carbon is used.
44. The method of manufacturing a solid-state imaging element according to claim 43, wherein silicon oxide is used as a material of the second embedded layer. Forming an alignment mark on a semiconductor substrate, which is made of a buried layer made of a material distinguishable from the semiconductor substrate, and the surface of the buried layer is flush with the surface of the semiconductor substrate;
A method of manufacturing a semiconductor integrated circuit device, comprising: forming a component on the front surface side and the back surface side of a semiconductor substrate having a required thickness finally obtained from the semiconductor substrate with reference to the alignment mark. . A silicon substrate is used as the semiconductor substrate,
46. The semiconductor integrated circuit according to claim 45, further comprising a step of forming a groove in the thickness direction in the silicon substrate, forming a buried layer made of a material different from silicon in the groove, and forming the alignment mark. Device manufacturing method. 47. The method of manufacturing a semiconductor integrated circuit device according to claim 46, wherein any one of SiO, SiN, SiC, SiON, SiOC, SiCN, and polysilicon is used as the material different from the silicon. 47. The method of manufacturing a semiconductor integrated circuit device according to claim 46, wherein an aspect ratio of the groove for forming the alignment mark is 1 or more. An SOI substrate having silicon layers on both sides of an insulating layer is used as the semiconductor substrate,
Forming a groove reaching the insulating layer from the main surface of the one silicon layer, using the insulating layer as an etching stop layer in one silicon layer to be a semiconductor substrate having a required thickness finally obtained;
46. The method of manufacturing a semiconductor integrated circuit device according to claim 45, further comprising: forming the buried layer in the groove to form the alignment mark. 46. The method of manufacturing a semiconductor integrated circuit device according to claim 45, wherein the alignment mark is formed so as to reach from the front surface side to the back surface side of the finally obtained semiconductor layer. A silicon substrate is used as the semiconductor substrate,
Forming a groove in the depth direction in the silicon substrate;
A thin film of a first material different from silicon is formed on the inner surface of the groove, and then a buried layer of a second material different from the first material is buried in the groove to form a multi-layer alignment mark. 46. A method of manufacturing a semiconductor integrated circuit device according to claim 45. 52. The method of manufacturing a semiconductor integrated circuit device according to claim 51, wherein the thin film of the first material of the alignment mark having the multilayer structure is formed except for a side wall portion in the vicinity of the opening of the groove. As the first material of the thin film, any material of SiO, SiN, SiCN, SiC, SiOC, SiO or SiON is used,
52. The method of manufacturing a semiconductor integrated circuit device according to claim 51, wherein a material having an etching selectivity with respect to the thin film is used as the second material of the buried layer. 50. The method of manufacturing a semiconductor integrated circuit device according to claim 49, wherein after the alignment mark is formed, the other silicon layer and the insulating layer of the SOI substrate are removed to leave one silicon layer. 50. The method of manufacturing a semiconductor integrated circuit device according to claim 49, wherein after the alignment mark is formed, the other silicon layer of the SOI substrate is removed to leave the insulating layer and the one silicon layer. 46. The method of manufacturing a semiconductor integrated circuit device according to claim 45, wherein the alignment mark is formed in a square shape in which each side is separated in plan view. Using an SOI substrate having silicon layers on both sides of the insulating layer,
Forming a groove reaching the insulating layer from the main surface of the one silicon layer, using the insulating layer as an etching stop layer, in the one finally obtained silicon layer having a required thickness;
Forming a second buried layer made of a material different from silicon except for the groove opening in the groove;
Forming a first buried layer of a material different from silicon and the second buried layer in the groove opening portion,
45. The method of manufacturing a semiconductor integrated circuit device according to claim 44, wherein an alignment mark is formed by the groove and the first embedded layer and the second embedded layer in the groove. As a material for the first buried layer, any one of silicon nitride, polysilicon, amorphous silicon, and silicon containing carbon is used.
58. The method of manufacturing a semiconductor integrated circuit device according to claim 57, wherein silicon oxide is used as a material of the second buried layer.

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