JP2005268101A - Image display device and its drive method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems wherein electric power consumption at a scan driver LSI in a display process and discharge interference at adjacent cells in the longitudinal direction of a panel have occured in prior art. <P>SOLUTION: This is an image display device which is provided with a display panel having first electrodes So1, Se1, So2 to apply scanning pulses to carry out scanning, second electrodes Xodd, Xeven, third electrodes Yodd, and Yeven to apply alternating current voltage pulses to carry out display, and an address electrode to apply an address pulse, and which is constituted so that two of the first electrodes is electrically connected, by straddling the second electrodes or the third electrodes in the vertical direction. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an image display device and a driving method thereof, and more particularly to an image display device suitable for driving a plasma display panel (PDP) and a driving method thereof.

  In recent years, AC plasma display devices that perform surface discharge have been put to practical use as flat image display devices, and display image display devices such as personal computers and workstations, flat wall-mounted televisions, or advertisements and information. Has been widely used as a device for. For example, in a three-electrode surface discharge type plasma display device, power consumption is increased because the Y electrode plays the role of a scanning electrode. Further, in the conventional plasma display device, discharge interference between adjacent cells in the vertical direction is a problem. Therefore, there is a demand for providing an image display apparatus and a driving method thereof that can perform high-resolution display with less power consumption and can further reduce the cost.

  2. Description of the Related Art Conventionally, a plasma display device that performs surface discharge has been put to practical use as a flat-type image display device, and all pixels on a screen are caused to emit light simultaneously according to display data. A plasma display device that performs surface discharge has a structure in which a pair of electrodes is formed on the inner surface of a front glass substrate, and a rare gas is sealed therein. When a voltage is applied between the electrodes, surface discharge occurs on the surfaces of the dielectric layer and the protective layer formed on the electrode surface, and ultraviolet rays are generated. The inner surface of the back glass substrate is coated with phosphors of three primary colors, red (R), green (G), and blue (B), and these phosphors are excited to emit light with ultraviolet rays for color display. To do.

  FIG. 1 schematically shows an example of a conventional plasma display panel, which shows a three-electrode surface discharge AC type plasma display panel.

  In FIG. 1, reference numeral 10 is a plasma display panel (PDP), 11 is a front substrate (front substrate), 12 is a transparent electrode for X electrode, 13 is a bus electrode for X electrode, and 14 is for Y electrode. A transparent electrode, 15 is a bus electrode for Y electrode, 16 is a substrate on the back side (back substrate), 17 is an address electrode, 18 is a partition wall (rib), and 19R, 19G, and 19B are phosphor layers. . In the actual PDP 10, a dielectric layer and a protective film are provided on the X electrode and the Y electrode, and a dielectric layer is provided on the address electrode. Further, a mixture of neon and xenon is provided between the front substrate 11 provided with the X electrodes (12, 13) and the Y electrode (14, 15) and the rear substrate 16 provided with the address electrodes 17. A discharge gas such as a gas is filled, and a discharge space at the intersection of the X electrode and the Y electrode and the address electrode constitutes one discharge cell.

  FIG. 2 is a diagram showing an example of a gradation driving sequence in a conventional plasma display apparatus.

  As shown in FIG. 2, in the gradation driving sequence in the plasma display apparatus, one field (frame) is composed of a plurality of subfields (subframes) SF1 to SFn each having a predetermined luminance weight, and each subfield The desired gradation display is performed by the combination. Specifically, as the plurality of subfields, for example, eight subfields SF1 to SF8 having a luminance weight of a power of 2 (the ratio of the number of sustain discharges is 1: 2: 4: 8: 16: 32: 64). : 128), 256 gradations are displayed.

  FIG. 3 is a diagram for explaining a driving method of a conventional plasma display apparatus.

  As shown in FIGS. 2 and 3, each subfield (for example, SF1 to SF8) has an initialization process (reset period) TR that makes the wall charges (charged states) of all the cells in the display region uniform. Address process (address period) TA in which wall charges are formed in the cells to be lit to select the lit cells, and display process (maintenance) in which the lit cells in which the wall charges are formed are discharged (lit) a number of times according to the luminance. The discharge period is composed of TS, and the cell is turned on according to the brightness for each display of each subfield, and for example, one subfield is displayed by displaying eight subfields (SF1 to SF8). Yes.

  That is, in the initialization process TR, first, discharge is generated in all the cells by the pulse P1 to write wall charges, and discharge to erase the wall charges in all the cells is generated by the next pulse P2 to adjust the charged state to zero. . Further, in the subsequent address process TA, a scan pulse is sequentially applied to the Y electrodes (14, 15), and at the same time, an address pulse is applied to the cells to be lit based on the display data to cause an address discharge, Form wall charges.

  In the subsequent display process TS, a sustain discharge pulse (display discharge pulse) is applied to the X electrode and the Y electrode (display electrode), and only the cells in which wall charges are formed by the address discharge are turned on. The brightness of the cell is controlled by the number of sustain discharge pulses.

  FIG. 4 is a block diagram schematically showing an overall configuration of an example of a conventional plasma display device. For example, FIG. 4 schematically shows an example of a plasma display device 100 using the PDP 10 as shown in FIG. is there.

  The plasma display apparatus 100 includes a PDP 10, an X-side driver 32, a Y-side driver 33 and an address-side driver 34 for driving each cell of the PDP 10, and a control circuit 31 that controls these drivers. The control circuit 31 receives field data Df, which is multi-valued image data indicating luminance levels of three colors R, G, and B, and various synchronization signals (clock signal CLK, horizontal) from an external device such as a TV tuner or a computer. A synchronization signal Hsync and a vertical synchronization signal Vsync) are input. The control circuit 31 outputs a control signal suitable for each of the drivers 32 to 34 from the field data Df and various synchronization signals to perform a predetermined image display.

  The Y-side driver 33 controls the Y electrode and includes a scan driver (scan driver LSI) 331 and a common driver 332. The X-side driver 32 controls the X electrode and includes a common driver 320. .

  In recent years, for example, in the market of PDP televisions (plasma display devices), the price has been reduced, and the price per inch of panel size has come to be less than $ 100 or even 10,000 yen. Therefore, cost reduction is essential to supply competitive products.

  By the way, normally, the number of display electrodes necessary for displaying the vertical resolution N lines is N X electrodes + N Y electrodes = 2N. On the other hand, conventionally, display discharge light emission is performed between all display electrodes, and a total of (N + 1) display electrodes of X electrodes (N / 2 + 1) and N / 2 electrodes has a vertical resolution of N lines. One that performs interlaced display and realizes cost reduction has been proposed (see, for example, Patent Document 1).

  Further, conventionally, N independent scanning electrodes S are provided separately from the X electrodes (N / 2 + 1) and the Y electrodes N / 2, and the vertical resolution N lines are progressively displayed by a total of (2N + 1) electrodes. The thing is also proposed (for example, refer patent documents 2-5).

  Further, conventionally, in order to improve the light emission luminance and stabilize the writing discharge, the address electrode and the scan electrode are partially overlapped with each other, and the sustain electrode is separated from the scan electrode in parallel with a predetermined distance. There has also been proposed a surface discharge type plasma display panel in which scan electrodes and sustain electrodes are formed in a comb-like shape (see, for example, Patent Document 6).

Japanese Patent No. 2801893 (JP 09-160525 A: whole) JP-A-10-144225 (paragraph numbers 0021 to 0046, FIGS. 3 to 5) JP-A-10-199427 (Overall) JP 2000-123740 A (Overall) JP 2000-305512 A (Overall) JP 2002-008548 A (Overall)

  2. Description of the Related Art Conventionally, for example, a plasma display device that displays interlaced vertical resolution N lines with only a total of (N + 1) display electrodes of X electrodes (N / 2 + 1) and Y electrodes N / 2 (for example, described in Patent Document 1) In such plasma display devices, an increase in power consumption is a problem. Here, the increase in power consumption, which is a problem, indicates the power lost in the scan driver LSI.

  FIG. 5 is a block circuit diagram showing an example of the Y-side driver in the plasma display device shown in FIG. 4, and FIG. 6 is a circuit diagram showing an example of the scan driver LSI in the Y-side driver shown in FIG.

  As shown in FIG. 5, the Y-side driver 33 is a p-channel MOS transistor (pMOS transistor) 3301 whose source is connected to the high potential power supply line (Vdd) and whose gate is supplied with the control signal CS1, and whose source is low. An n-channel MOS transistor (nMOS transistor) 3302 connected to the potential power supply line (Vss) and supplied with the control signal CS2 to the gate, connected between the drain of the pMOS transistor 3301 and the scan driver LSI 331 and the common driver 332 A diode 3303 and a diode 3304 connected between the scan driver LSI 331 and the common driver 332 and the drain of the nMOS transistor 3302 are provided.

  As shown in FIG. 6, the scan driver LSI 331 includes a pMOS transistor 3311 (Q1) whose source is connected to the high potential power supply line (Vdd) and the gate supplied with the control signal CS11, and the source is the low potential power supply line (Vss). ) And a gate to which the control signal CS12 is supplied, an nMOS transistor 3312 (Q2), a diode 3313 (D1) provided between the source and drain of the pMOS transistor 3311, and a source and drain of the nMOS transistor 3312 Is provided with a diode 3314 (D2).

  For example, the control signals CS1 and CS2 become low level “L” and high level “H” in the address process (TA), respectively, to turn on the pMOS transistor 3301 and the nMOS transistor 3302. That is, in the initialization process (TR) and the display process (TS), the control signals CS1 and CS2 become the high level “H” and the low level “L”, respectively, to turn off the pMOS transistor 3301 and the nMOS transistor 3302. Here, in the initialization process and the display process, when a current flows from the common driver 332 toward the Y electrodes (14, 15), the Y electrode passes from the common driver 332 through the diode 3314 (D2) of the scan driver LSI 331. When a current flows from the Y electrode toward the common driver 332, the current flows from the Y electrode to the common driver 332 through the diode 3313 (D1) of the scan driver LSI 331. The diodes D1 and D2 are diodes (FET parasitic diodes) that are parasitic on the off-state transistors 3311 and 3312 or external diodes.

  Further, in the address process (TA), the control signals CS11 and CS12 are sequentially turned to the low level “L” and the high level “H” in accordance with the respective scanning lines to sequentially turn on the pMOS transistor 3311 and the nMOS transistor 3312. Address discharge is sequentially performed between all address electrodes and each Y electrode.

  As described above, in the conventional plasma display device (for example, the plasma display device described in Patent Document 1), the Y electrode plays the role of the scanning electrode. Therefore, in the time region other than the address process, in FIG. The transistors Q1 and Q2 were turned off, and current was output to the Y electrode (scanning electrode) via the FET parasitic diode or the diodes D1 and D2 which are external diodes. For example, this current has a value of about 3 [A] when the maximum gradation display (white display) is performed on the entire surface of the 42-inch diagonal plasma display panel. Therefore, since the voltage drop of the diode is about 1 [V], the power loss is 1 [V] × 3 [A] × 2 = 6 [W]. Furthermore, when considering the thermal resistance loss inside the LSI package that is caused by passing a current, the power of about 10 [W] is lost as a whole. The power loss becomes greater than the increase in the panel area as the panel size increases. Here, the power loss by the scan driver LSI during the period other than the address process occurs in both the initialization process and the display process. For example, the power loss in the display process in which the sustain discharge occurs about 600 times at the maximum (power consumption) Increase) is a big problem. That is, in the conventional plasma display device, reduction of power consumption in the scan driver LSI in the display process is an issue.

  In addition to the above power consumption problem, discharge interference of adjacent cells in the vertical direction of the panel is also a problem to be solved.

  This is because, for example, when the vertical resolution N lines are interlaced with only a total of (N + 1) display electrodes of X electrodes (N / 2 + 1) and Y electrodes N / 2, the discharge may be partitioned in the vertical direction. This is because it cannot be done. In other words, the discharge of the lighted cell spreads to the upper and lower adjacent cells, and the upper and lower adjacent cells that should not be lit up gradually light up, and the normal lighting state cannot be maintained.

  On the other hand, for example, in addition to the X electrodes (N / 2 + 1) and the Y electrodes N / 2, N independent scanning electrodes S are provided, and the vertical resolution N lines are progressively displayed with a total of (2N + 1) electrodes. Therefore, a scan driver LSI having a total output of N bits is required. That is, as compared with the case where 2N display electrode pairs of N lines are progressively displayed, only the non-display portion is reduced, and the cost cannot be further reduced.

  SUMMARY OF THE INVENTION In view of the above-described problems in the conventional technology, the present invention provides an image display apparatus and a driving method thereof that can perform high-resolution display with less power consumption and can further reduce costs. For the purpose of provision.

  According to the first aspect of the present invention, a first electrode that applies a scan pulse for performing scanning, a second electrode and a third electrode that apply an alternating voltage pulse for performing display, and an address pulse are applied. An image display device comprising a display panel having address electrodes that are connected, wherein the two first electrodes are electrically connected across the second electrode or the third electrode in the vertical direction. A display device is provided.

  According to the second aspect of the present invention, a first electrode for applying a scan pulse for performing scanning, a second electrode and a third electrode for applying an alternating voltage pulse for performing display, and an address pulse are applied. A display panel having an address electrode, and driving the image display device in which the two first electrodes are electrically connected across the second electrode or the third electrode in the vertical direction, An initialization process for initializing the voltage state, and a scan pulse is applied to the first electrode to form a wall voltage corresponding to the pixel data in each cell, and data corresponding to the pixel data is applied to the address electrode Driving an image display device comprising: repeatedly performing an address process of applying a pulse and a display process of applying an AC voltage pulse between the second electrode and the third electrode serving as display electrodes The law is provided.

  According to the present invention, it is possible to provide an image display apparatus that can perform high-resolution display with less power consumption and can further reduce costs, and a driving method thereof. Furthermore, according to the present invention, it is possible to provide an image display apparatus capable of eliminating discharge interference between adjacent cells in the vertical direction and a driving method thereof.

  First, before describing embodiments of an image display device and a driving method thereof according to the present invention in detail, the principle configuration of the present invention will be described in detail with reference to the drawings.

  FIG. 7 is a view for explaining the display electrode structure of the image display device according to the present invention, and shows the electrode structure on the front substrate side of the plasma display panel.

  As shown in FIG. 7, scanning electrodes S (So1, Se1, So2, Se2,...) Are provided independently of X electrodes (Xodd, Xeven) and Y electrodes (Yodd, Yeven) as display electrodes. Two adjacent scanning electrodes are electrically connected. That is, the two scanning electrodes S are electrically connected across the X or Y electrode in the vertical direction.

  In the present invention, vertical resolution N lines are displayed in an interlaced manner with a configuration of (N / 2 + 1) X electrodes, N / 2 Y electrodes, and N / 2 S electrodes. Here, the S electrodes look like N, but since the two electrodes straddling the X electrode or the Y electrode are electrically connected and driven in common, a scan driver LSI for N / 2 outputs is sufficient. It will be. In addition, since no current flows through the scan driver LSI during the display process, for example, a power consumption of about 10 W can be reduced in a 42-inch diagonal plasma display panel. Furthermore, since the address discharge between the S electrode and the address electrode is a trigger discharge directed to the main address discharge between the X electrode and the Y electrode, the address discharge current flowing through the LSI can be made smaller than before. Therefore, according to the present invention, it is possible to reduce the cost by using an LSI with a smaller rated current.

  Furthermore, since the S electrodes that did not cause the address discharge play a role of partitioning the discharge in the upper and lower adjacent cells of the lighting cell, it is possible to eliminate the discharge interference of the adjacent cells in the vertical direction, which has been a problem in the past.

  Hereinafter, embodiments of an image display apparatus and a driving method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 8 is a block diagram schematically showing the overall configuration of the first embodiment of the image display apparatus according to the present invention. For example, the plasma display apparatus using the PDP 20 having the display electrode structure shown in FIG. 1 schematically shows the overall configuration of 200 first embodiments.

  The plasma display apparatus 200 includes a PDP 20, an X-side driver 42, a Y-side driver 43, an address-side driver 44, and an S-side driver 45 for driving each cell of the PDP 20, and a control circuit 41 that controls these drivers. It has. The control circuit 41 receives field data Df, which is multi-value image data indicating luminance levels of three colors R, G, and B, and various synchronization signals (clock signal CLK, horizontal) from an external device such as a TV tuner or a computer. A synchronization signal Hsync and a vertical synchronization signal Vsync) are input. The control circuit 41 outputs a control signal suitable for each of the drivers 42 to 45 from the field data Df and various synchronization signals to perform a predetermined image display.

  The X-side driver 42 controls the X electrodes, and includes an odd common driver 421 that controls the odd-numbered X electrodes and an even common driver 422 that controls the even-numbered X electrodes, and the Y-side driver 43 includes the Y electrodes. The odd common driver 431 for controlling the odd-numbered Y electrodes and the even common driver 432 for controlling the even-numbered Y electrodes are provided. Further, the S-side driver 45 controls a scan electrode (S electrode), and includes a scan driver (scan driver LSI) 450. Here, two S electrodes (scanning electrodes) that cross the X or Y electrode in the vertical direction are electrically connected.

  That is, according to the image display apparatus (plasma display apparatus) of the first embodiment, the scan driver LSI 450 is arranged in the S-side driver 45, and the common drivers 421, 422 and 431, 432 for applying the display discharge pulse are The X-side driver 42 and the Y-side driver 43 are arranged.

  FIG. 9 is a block diagram showing an example of the Y-side driver in the image display apparatus shown in FIG.

  As shown in FIG. 9, the Y-side driver 43 includes a common driver 430 that controls the Y electrode. Here, the common driver 430 corresponds to the odd common driver 431 and the even common driver 432 in FIG.

  FIG. 10 is a block circuit diagram showing an example of the S-side driver in the image display apparatus shown in FIG.

  As shown in FIG. 10, the S-side driver 45 includes a scan driver LSI (scan driver) 450, a pMOS transistor 4501 whose source is connected to a high potential power supply line (Vdd) and a control signal CS21 is supplied to the gate, source Are connected to the low potential power supply line (Vss) and the gate is supplied with the control signal CS22, the nMOS transistor 4502, the diode 4503 connected between the drain of the pMOS transistor 4501 and the scan driver LSI 450, and the scan driver LSI 450 A diode 4504 connected between the drain of the nMOS transistor 4502 is provided. Here, as the scan driver LSI 450, for example, a conventional scan driver LSI 331 as shown in FIG. 6 can be used as it is. Further, the control signals CS21 and CS22 become low level “L” and high level “H”, for example, in the address process (TA), respectively, to turn on the pMOS transistor 4501 and the nMOS transistor 4502. Note that in the address process (TA), the scan driver LSI 450 (331) causes the control signals CS11 and CS12 to sequentially change to the low level “L” and the high level “H” in accordance with each scan line, respectively, and the pMOS transistor 3311 and the nMOS. The transistors 3312 are sequentially turned on so that address discharge is sequentially performed between all address electrodes and each S electrode.

  In the S-side driver 45, the source is connected to the ground (GND) and the gate is supplied with the control signal CS31, and the source is connected to the ground (GND) and the gate is supplied with the control signal CS32. A pMOS transistor 452, a diode 453 connected between the drain of the nMOS transistor 451 and the scan driver LSI 450, and a diode 454 connected between the scan driver LSI 450 and the drain of the pMOS transistor 452 are provided.

  Transistors 451 and 452 and diodes 453 and 454 (a circuit surrounded by a broken line in FIG. 10) constitute a ground switch and are used when the S electrode is clamped to the ground potential in a time region other than the address process. It is. When clamping the S electrode to a positive potential, GND connected to the source of the pMOS transistor (switch) 452 may be replaced with a positive potential power source. Similarly, when clamping the S electrode to a negative potential, GND connected to the source of the nMOS transistor (switch) 451 may be replaced with a negative potential power source. Further, when the potential of the S electrode is made floating in a time region other than the address process, the transistors 451 and 452 and the diodes 453 and 454 surrounded by a broken line are not necessary. The control of these S electrodes will be described in detail later with reference to the drawings.

  FIG. 11 is a block circuit diagram showing another example of the S-side driver in the image display device shown in FIG.

  The S-side driver 45 shown in FIG. 11 includes a diode 4503 connected to the high potential power supply line (Vdd), a diode 4504 connected to the low potential power supply line (Vss), and a scan driver LSI 450.

  Thus, the S-side driver 45 can be variously modified according to the driving method of the plasma display apparatus.

  FIG. 12 is a diagram conceptually showing a lighted cell in the image display device according to the present invention, and FIG. 13 is a diagram showing a drive waveform in an odd field in the first embodiment of the image display device drive method according to the present invention. FIG. 14 is a diagram showing the drive waveforms of the even field in the first embodiment of the drive method of the image display apparatus according to the present invention.

  As shown in FIGS. 12 and 13, in the odd field, between the odd line X electrode Xodd and the odd line Y electrode Yodd, and between the even line X electrode Xeven and the even line Y electrode Yeven. The cell lights up. On the other hand, as shown in FIG. 12 and FIG. 14, in the even field, between the odd line Y electrode Yodd and the even line X electrode Xeven and between the even line Y electrode Yeven and the odd line X electrode Xodd The cells between are illuminated. That is, in the driving method shown in FIGS. 13 and 14, in the addressing process TA, the discharge between the scanning electrode (S electrode) and the address electrode (A electrode) is used as a trigger to discharge between the display electrodes (X electrode and Y electrode). It has been developed to display. The first embodiment of the image display apparatus driving method according to the present invention will be described in detail below.

  As shown in FIG. 13, in the odd field, the wall charge is written into the cell with the pulse P1 of the initialization process TR, and then the wall voltage is adjusted while erasing the wall charge with the pulse P2. The address process TA includes a first half address process TA1 and a second half address process TA2.

  In the first half address process TA1, the odd-numbered (odd-line) X electrode Xodd and the odd-numbered Y electrode Yodd, and the odd-numbered S-electrode Son (So1, So2,... Sandwiched between these electrodes Xodd, Yodd. ) To address the cell specified. Here, the applied voltage to Xodd is made larger than the applied voltage to Xeven, which is the even-numbered (even-numbered line) X electrode, so that no erroneous discharge occurs between Yodd-Son-Xeven.

  Similarly, in the second half address process TA2, even-numbered X electrode Xeven and even-numbered Y electrode Yeven, and even-numbered S electrode Sen (Se1, Se2,. ...) address the cell specified by Here, the voltage applied to Xeven is made larger than the voltage applied to Xodd so that erroneous discharge does not occur between Yeven-Sen-Xodd.

  Thereby, a wall voltage based on address discharge is formed between Xodd and Yodd and between Xeven and Yeven. Then, in the subsequent display process TS, an alternating pulse (display discharge pulse: sustain pulse) is applied between Xodd and Yodd and between Xeven and Yeven to cause display discharge only in the cell selected in the address process TA. .

  By applying the above sequence to the odd field and applying the sequence in which the applied voltage waveforms of Xodd and Xeven of the odd field sequence are switched to the even field as shown in FIG. Can cause a display discharge, and as shown in FIG. 12, the entire screen is interlaced.

  FIG. 15 is a diagram showing driving waveforms in odd fields in the second embodiment of the driving method of the image display apparatus according to the present invention. In the following description, each embodiment of the driving method of the image display device will be described with reference to the driving waveform of the odd field, but the driving waveform of the even field has the same relationship as in FIGS. I will omit it.

  In the driving method of the second embodiment shown in FIG. 15, the initialization process is performed by applying the reset pulse in the initialization step TR of FIG. 13 to the S electrode instead of the X and Y electrodes. That is, since the initialization process TR is a wall voltage setup period for the subsequent address process TA, the voltage application in the initialization process TR is performed using the S electrode (scan electrode) and the A electrode (address electrode). It may be between.

  FIG. 16 is a diagram showing driving waveforms in odd fields in the third embodiment of the driving method of the image display apparatus according to the present invention.

  As is apparent from a comparison between FIGS. 16, 13, and 15, the driving method of the third embodiment is not only applied to the X and Y electrodes shown in FIG. The initialization process is performed by applying a reset pulse to the S electrode shown. As described above, the charge adjustment can be performed more precisely by applying the reset pulse to the X electrode, the Y electrode, and the S electrode. In FIG. 16, for example, the pulse voltage Vr1 applied to the Y electrode is set to have a larger absolute value than the pulse voltage Vr2 applied to the S electrode. This is because the pulse voltage Vr2 applied to the S electrode can be reduced because the distance to the X electrode is short.

  By the way, since the S electrode does not perform display discharge, it is not necessary to apply a voltage to the S electrode in the display process. That is, if the potential of the S electrode in the display process is floated, it can be regarded as an insulator having a very high dielectric constant, so that unnecessary wall charges can be prevented from accumulating on the S electrode.

  On the other hand, in the display process, it is possible to positively apply a voltage to the S electrode so that the S electrode acts as a trigger electrode. In this case, the voltage of the display discharge pulse can be reduced and the light emission efficiency can be improved.

  FIG. 17 is a diagram showing driving waveforms of odd fields in the fourth embodiment of the driving method of the image display apparatus according to the present invention, and FIG. 18 is an odd number in the fifth embodiment of the driving method of the image display apparatus according to the present invention. It is a figure which shows the drive waveform of a field.

  In the driving method of the fourth embodiment, as shown in FIG. 17, in the display process TS, the S electrode is clamped to a predetermined positive potential Vf1 (for example, about several tens of volts). As described above, for example, in the circuit shown in FIG. 10, a predetermined positive potential is applied to the source of the nMOS transistor 452, and the S electrode is set to the positive potential Vf1 in the display process TS shown in FIG. During clamping, the control signal CS32 is set to the high level “H” to turn on the nMOS transistor 452. The current that has passed through the nMOS transistor 452 and the diode 454 flows to the S electrode via the diode D2 of the scan driver LSI 450 (331) (or the parasitic diode of the transistor 3312). At this time, power loss occurs. However, this is one time unlike the display discharge pulse, and the power loss is not a problem.

  Conversely, in the driving method of the fifth embodiment, as shown in FIG. 18, in the display process TS, the S electrode is clamped to a predetermined negative potential Vf2 (for example, about minus several tens of volts). Yes. For example, in the circuit shown in FIG. 10, control is performed while a predetermined negative potential is applied to the source of the nMOS transistor 451 and the S electrode is clamped to the negative potential Vf2 in the display process TS shown in FIG. The signal CS31 is set to a low level “L” to turn on the nMOS transistor 451. The current that has passed through the nMOS transistor 451 and the diode 453 flows to the S electrode via the diode D1 of the scan driver LSI 450 (331) (or the parasitic diode of the transistor 3311).

  FIG. 19 is a diagram showing driving waveforms in odd fields in the sixth embodiment of the driving method of the image display apparatus according to the present invention.

  As is apparent from the comparison between FIG. 19 and FIG. 17, the driving method of the sixth embodiment is a display instead of clamping the S electrode to a predetermined positive potential in the display process TS in the fourth embodiment of FIG. A pulse of a predetermined positive potential Vf1 synchronized with only the first discharge pulse is applied to the S electrode. The pulse applied to the S electrode may be the negative potential Vf2 instead of the positive potential Vf1.

  FIG. 20 is a diagram showing driving waveforms in odd fields in the seventh embodiment of the driving method of the image display apparatus according to the present invention.

  As apparent from the comparison between FIG. 20 and FIG. 19, in the driving method of the seventh embodiment, in the addressing process TA, after the address discharge is generated by the S electrode and the address electrode, Address discharge is generated between the X electrode and the Y electrode.

  FIG. 21 is a diagram showing driving waveforms in odd fields in the eighth embodiment of the driving method of the image display apparatus according to the present invention.

  As shown in FIG. 21, the driving method of the eighth embodiment displays not only the first display discharge pulse but also the pulse of the predetermined positive potential Vf1 in the driving method of the sixth embodiment of FIG. Only the first part of the process TS (for example, a period corresponding to the first three display discharge pulses) is applied to the S electrode. Needless to say, the pulse applied to the S electrode may be the negative potential Vf2 instead of the positive potential Vf1.

  As described above, the predetermined voltage applied to the S electrode in the display process TS may be positive or negative as long as the S electrode can act as a trigger electrode. It may be applied in synchronism with only the first shot or only at the beginning of the display process. Further, in the display process TS, since the display discharge pulse is not applied to the S electrode, various voltages (drive waveforms) other than those described above are applied to the S electrode, and the voltages of the display discharge pulses applied to the X electrode and the Y electrode are set. It is also possible to reduce or improve luminous efficiency.

  FIG. 22 is a block diagram schematically showing the overall configuration of the second embodiment of the image display apparatus according to the present invention.

  As apparent from the comparison between FIG. 22 and FIG. 8, the image display apparatus of the second embodiment switches the arrangement of the Y-side driver 43 and the S-side driver 45 in the image display apparatus of the first embodiment of FIG. In the display process TS, an X-side driver 42 and a Y-side driver 43 that cause display discharge by causing current to flow through the X electrode and the Y electrode are arranged on both sides of the panel 20 to prevent EMI and reduce noise (for example, infrared rays) To prevent the malfunction of the remote controller due to the radiation).

  FIG. 23 is a block diagram schematically showing the overall configuration of the third embodiment of the image display apparatus according to the present invention.

  As is apparent from the comparison between FIG. 23 and FIG. 22, the image display apparatus of the third embodiment electrically connects two S electrodes straddling the X electrode or the Y electrode in the vertical direction inside the panel 20. It is like that. Thereby, the number of connection terminals of the S electrode in the panel 20 can be halved.

  FIG. 24 is a block diagram schematically showing the overall configuration of the fourth embodiment of the image display apparatus according to the present invention.

  As shown in FIG. 24, in the image display apparatus according to the fourth embodiment, the address side driver 44 includes a delay circuit 441 for performing a delayed transfer of data (pixel data), and the data from the control circuit 41 is received. The data pulse is output to the address electrode with a delay in accordance with the distance from the S-side driver 45 (scan driver LSI 450) in the S electrode. As will be described later, for example, when the S electrode is composed of only the transparent electrode without providing the bus electrode, the propagation delay increases as the distance from the scan driver 450 to the S electrode increases. That is, the propagation delay of the scan pulse is small on the side close to the scan driver 450 in the S electrode (left side in FIG. 24), and conversely, on the side far from the scan driver 450 in the S electrode (right side in FIG. 24) The propagation delay becomes large, and there is a possibility that a luminance distribution is generated in the image display in the direction (lateral direction) in which the S electrode extends.

  Therefore, in the image display device of the fourth embodiment, display is performed with a relatively small delay time for the address electrode (address electrode driver LSI) corresponding to the side close to the scan driver 450 in the S electrode. Data is supplied, and conversely, the address electrode corresponding to the S electrode farther from the scan driver 450 is supplied with a relatively large delay time, and the data is supplied between the S electrode and each address electrode. The address discharge is caused at the optimum timing to prevent the deterioration of the image quality. Note that the delay time set by the delay circuit 441 may be configured to be set for each of a plurality of address electrodes.

  FIG. 25 is a plan view schematically showing a first embodiment of the electrode structure of the image display device according to the present invention, and FIG. 26 is a sectional view of the electrode structure shown in FIG. 25 cut along L1-L1. .

  As shown in FIGS. 25 and 26, the front substrate 21 (front substrate) has an S electrode (26, 27), an X electrode (22, 23), and a Y electrode (24, 25) from the front substrate side. A dielectric layer 28 and a protective layer 29 are sequentially formed. Here, the S electrode, the X electrode, and the Y electrode include transparent electrodes 26, 22 and 24 and bus electrodes 27, 23 and 25, respectively. 25 is provided on a rear substrate (back substrate 16) (not shown) facing the front substrate 21, and an address electrode (17) is provided between each partition 18 on the rear substrate. ing.

  The region where the X electrode (Xodd, Xeven), the S electrode and the Y electrode (Yodd, Yeven) intersect with the address electrode (A), the Y electrode (Yodd, Yeven), the S electrode and the X electrode (Xeven, The areas where Xodd) and the address electrodes intersect are the display areas Fodd and Feven of the cells that are lit in the odd and even fields, respectively. The widths of the transparent electrode 26 and the bus electrode 27 constituting the S electrode are formed narrower than the widths of the transparent electrodes 22 and 24 and the bus electrodes 23 and 25 constituting the X electrode and the Y electrode, and the display region (Fodd, The portion that prevents Feven) is made smaller. Thus, according to the first embodiment of the present electrode structure, a panel can be manufactured by directly applying the conventional electrode forming process by forming the S electrode, the X electrode, and the Y electrode on the same plane. .

  FIG. 27 is a plan view schematically showing a second embodiment of the electrode structure of the image display device according to the present invention, and FIG. 28 is a sectional view of the electrode structure shown in FIG. 27 cut along L2-L2. .

  As is apparent from a comparison between FIGS. 27 and 28 and FIGS. 25 and 26, in the second embodiment of the present electrode structure, the S electrode is composed only of the transparent electrode 26 and hinders the display area (Fodd, Feven). A different bus electrode (27) is eliminated. That is, in consideration of the fact that the S electrode is formed at a high luminance portion at the center of the cell (display area), light emission shielding by the metal electrode is avoided.

  However, when the S electrode is configured by only the transparent electrode 26 in this way, for example, when the panel size to be driven is large, the propagation delay increases as the distance from the scan driver (450) in the S electrode increases. Therefore, as described with reference to FIG. 24, the address side driver (44) is provided with the delay circuit (441) so as to cause the address discharge between the S electrode and each address electrode to occur at the optimum timing. Can be configured. As described above, the delay time by the delay circuit may be set for each address electrode, but can also be set for each of a plurality of address electrodes.

  FIG. 29 is a plan view schematically showing a third embodiment of the electrode structure of the image display device according to the present invention.

  As is clear from comparison between FIG. 29 and FIG. 27, in the third embodiment of the present electrode structure, the S electrode formed of the transparent electrode 26 has a wide display area (Fodd, Feven) portion (26a 26a), the propagation delay due to the S electrode is reduced, and the address discharge between the S electrode and the address electrode is likely to occur (that is, the discharge start voltage is lowered). .

  FIG. 30 is a plan view schematically showing a fourth embodiment of the electrode structure of the image display device according to the present invention.

  As apparent from the comparison between FIG. 30 and FIG. 27, the fourth embodiment of the present electrode structure is the same as the second embodiment of the electrode structure described with reference to FIG. And 24 are provided with T-shaped portions 22a and 24a to lower the discharge start voltage.

  FIG. 31 is a plan view schematically showing a fifth embodiment of the electrode structure of the image display device according to the present invention.

  As shown in FIG. 31, in the fifth embodiment of the present electrode structure, partition walls 30 and 30 are provided on the back substrate 16 at positions corresponding to the X electrodes and the Y electrodes, and the back substrate 16 has grid-like ribs. A structure is formed.

  FIG. 32 is a sectional view schematically showing a sixth embodiment of the electrode structure of the image display device according to the present invention.

As shown in FIG. 32, in the sixth embodiment of the present electrode structure, the front substrate 21 includes an X electrode (22, 23) and a Y electrode (24, 25) from the front substrate side, and a dielectric layer 28. The S electrode (26) and the protective layer 29 are formed in this order. Here, the dielectric layer 28 can be driven at a lower voltage than the conventional one by making the relative dielectric constant as low as 5 or less by using, for example, a SiO ₂ layer formed by a CVD method. It becomes.

  Each example of the electrode structure described with reference to FIGS. 25 to 32 is merely an example, and it goes without saying that various modifications can be made.

  In the above description, the plasma display device is described as the image display device according to the present invention. However, the application of the present invention is not limited to the plasma display device.

  (Appendix 1) A display panel having a first electrode for applying a scan pulse for scanning, a second electrode and a third electrode for applying an AC voltage pulse for performing display, and an address electrode for applying an address pulse An image display device comprising: the two first electrodes electrically connected across the second electrode or the third electrode in a vertical direction.

  (Supplementary note 2) In the image display device according to supplementary note 1, the first electrode, the second electrode, and the third electrode are provided on a front substrate, the address electrode is provided on a rear substrate, An image display device, wherein the back substrate is disposed opposite to each other with a discharge space formed therebetween.

  (Additional remark 3) The image display apparatus of Additional remark 2 WHEREIN: This image display apparatus is a plasma display apparatus, The image display apparatus characterized by the above-mentioned.

  (Supplementary Note 4) In the image display device according to supplementary note 2, the first electrode, the second electrode, and the third electrode are all formed on the same plane of the front substrate, and on the electrodes, An image display device, wherein a dielectric layer and a protective layer are sequentially formed.

  (Additional remark 5) The image display apparatus of Additional remark 4 WHEREIN: Said 1st electrode is shared between the adjacent 2nd electrode and 3rd electrode, The image display apparatus characterized by the above-mentioned.

  (Appendix 6) In the image display device according to Appendix 2, the front substrate includes a second electrode and a third electrode, a dielectric layer, the first electrode, and a protective layer formed in this order from the front substrate side. An image display device.

  (Additional remark 7) The image display apparatus of Additional remark 1 WHEREIN: Each connection part to which said two 1st electrodes are electrically connected is provided in the said display panel, The image display apparatus characterized by the above-mentioned.

  (Additional remark 8) The image display apparatus of Additional remark 1 WHEREIN: Said 1st electrode is comprised with a transparent electrode, The image display apparatus characterized by the above-mentioned.

  (Additional remark 9) The image display apparatus of Additional remark 1 WHEREIN: Said 1st electrode is comprised with a transparent electrode and a bus electrode, The image display apparatus characterized by the above-mentioned.

(Supplementary note 10) In the image display device according to supplementary note 1, the first electrode is a scanning electrode, the second electrode is an X electrode, and the third electrode is a Y electrode. In addition,
A scan driver for applying the scan pulse to the scan electrode;
An image display apparatus comprising: an X electrode common driver and a Y electrode common driver that apply an AC voltage pulse for performing the display to the X electrode and the Y electrode.

  (Additional remark 11) The image display apparatus of Additional remark 10 WHEREIN: The said X electrode common driver and the said Y electrode common driver are arrange | positioned at the both sides of the said display panel, The image display apparatus characterized by the above-mentioned.

  (Supplementary note 12) The image display device according to supplementary note 10, further comprising an address-side driver that sequentially applies data pulses to the address electrodes, wherein the address-side driver includes a delay circuit for performing delayed transfer of pixel data. And an image is set such that when the data pulse corresponding to the pixel data is output to the address electrode, the delay time becomes longer as the distance from the scan driver in the scan electrode becomes longer. Display device.

  (Additional remark 13) The image display apparatus of Additional remark 12 WHEREIN: The said delay circuit sets delay time collectively for every said several address electrode, The image display apparatus characterized by the above-mentioned.

(Supplementary note 14) A method of driving the image display device according to any one of supplementary notes 1 to 13,
An initialization process for making the charged state of all the cells constituting the screen uniform, and applying a scan pulse to the first electrode and forming data on the address electrode in order to form a wall charge on the cell to be lit An address process for applying a pulse and a display process for applying an AC voltage pulse between the second electrode and the third electrode, which serve as display electrodes, in order to maintain the wall charge of the lighting cell in which the wall charges are formed are repeated. An image display apparatus driving method comprising: executing the image display apparatus;

  (Additional remark 15) The drive method of the image display apparatus of Additional remark 14 WHEREIN: The reset pulse for making the said charging state uniform is applied to said 1st electrode.

  (Supplementary Note 16) In the method for driving an image display device according to Supplementary Note 14, a reset pulse for making the charged state uniform is applied to the first electrode and the second electrode. Driving method.

  (Supplementary note 17) The image display device according to supplementary note 14, wherein a reset pulse for making the charged state uniform is applied to the first electrode and the third electrode. Driving method.

  (Supplementary note 18) In the driving method of the image display device according to supplementary note 14, a reset pulse for making the charged state uniform is applied to the first electrode, the second electrode, and the third electrode. A driving method of the image display apparatus.

  (Supplementary note 19) In the method for driving an image display device according to supplementary note 14, after the address discharge in the addressing process is caused to occur between the first electrode and the address electrode, the second in succession in time. A drive method for an image display device, wherein the image display device is caused to occur between an electrode and the third electrode.

  (Additional remark 20) The drive method of the image display apparatus of Additional remark 14 WHEREIN: The electric potential of said 1st electrode is made floating in the said display process, The drive method of the image display apparatus characterized by the above-mentioned.

  (Supplementary note 21) The method for driving an image display device according to supplementary note 14, wherein the potential of the first electrode is clamped to a fixed potential in the display process.

  (Supplementary note 22) The method for driving an image display device according to supplementary note 21, wherein the fixed potential applied to the first electrode is applied in the first period of the display process.

  The present invention can be applied to an image display device such as a plasma display device. For example, a display device such as a personal computer or a workstation, a flat wall-mounted television, or an advertisement or information is displayed. The present invention can be applied to an image display device used as the device.

It is a figure which shows an example of the conventional plasma display panel typically. It is a figure which shows an example of the gradation drive sequence in the conventional plasma display apparatus. It is a figure for demonstrating the driving method of the conventional plasma display apparatus. It is a block diagram which shows roughly the whole structure of an example of the conventional plasma display apparatus. FIG. 5 is a block circuit diagram showing an example of a Y-side driver in the plasma display device shown in FIG. 4. FIG. 6 is a circuit diagram illustrating an example of a scan driver LSI in the Y-side driver illustrated in FIG. 5. It is a figure for demonstrating the display electrode structure of the image display apparatus which concerns on this invention. 1 is a block diagram schematically showing an overall configuration of a first embodiment of an image display apparatus according to the present invention. It is a block diagram which shows an example of the Y side driver in the image display apparatus shown in FIG. It is a block circuit diagram which shows an example of the S side driver in the image display apparatus shown in FIG. FIG. 9 is a block circuit diagram illustrating another example of the S-side driver in the image display device illustrated in FIG. 8. It is a figure which shows notionally the lighting cell in the image display apparatus which concerns on this invention. It is a figure which shows the drive waveform of the odd field in 1st Example of the drive method of the image display apparatus which concerns on this invention. It is a figure which shows the drive waveform of the even field in 1st Example of the drive method of the image display apparatus which concerns on this invention. It is a figure which shows the drive waveform of the odd field in 2nd Example of the drive method of the image display apparatus which concerns on this invention. It is a figure which shows the drive waveform of the odd field in the 3rd Example of the drive method of the image display apparatus which concerns on this invention. It is a figure which shows the drive waveform of the odd field in 4th Example of the drive method of the image display apparatus which concerns on this invention. It is a figure which shows the drive waveform of the odd field in 5th Example of the drive method of the image display apparatus which concerns on this invention. It is a figure which shows the drive waveform of the odd field in the 6th Example of the drive method of the image display apparatus which concerns on this invention. It is a figure which shows the drive waveform of the odd field in the 7th Example of the drive method of the image display apparatus which concerns on this invention. It is a figure which shows the drive waveform of the odd field in the 8th Example of the drive method of the image display apparatus which concerns on this invention. It is a block diagram which shows roughly the whole structure of 2nd Example of the image display apparatus based on this invention. It is a block diagram which shows roughly the whole structure of 3rd Example of the image display apparatus based on this invention. It is a block diagram which shows roughly the whole structure of 4th Example of the image display apparatus based on this invention. It is a top view which shows roughly the 1st Example of the electrode structure of the image display apparatus which concerns on this invention. It is sectional drawing which cut | disconnected the electrode structure shown in FIG. 25 along L1-L1. It is a top view which shows roughly 2nd Example of the electrode structure of the image display apparatus which concerns on this invention. It is sectional drawing which cut | disconnected the electrode structure shown in FIG. 27 along L2-L2. It is a top view which shows roughly the 3rd Example of the electrode structure of the image display apparatus which concerns on this invention. It is a top view which shows roughly the 4th Example of the electrode structure of the image display apparatus which concerns on this invention. It is a top view which shows roughly the 5th Example of the electrode structure of the image display apparatus which concerns on this invention. It is sectional drawing which shows schematically the 6th Example of the electrode structure of the image display apparatus which concerns on this invention.

Explanation of symbols

10, 20 ... PDP (Plasma Display Panel)
11, 21 ... Front side board (front side board)
12, 22 ... X electrode transparent electrode 13, 23 ... X electrode bus electrode 14, 24 ... Y electrode transparent electrode 15, 25 ... Y electrode bus electrode 16 ... Back side substrate (back side substrate)
17 ... Address electrodes 18, 30 ... Partition walls (ribs)
19R, 19G, 19B ... phosphor layer 26 ... transparent electrode 27 for S electrode ... bus electrode 28 for S electrode ... dielectric layer 29 ... protective film 31, 41 ... control circuit 32, 42 ... X side drivers 33, 43 ... Y-side driver 34, 44 ... Address-side driver 45 ... S-side driver 100, 200 ... Plasma display device 320 ... X-side driver common driver 331 ... Y-side driver scan driver 332 ... Y-side driver common driver 421 ... X Side driver odd common driver 422 ... X side driver even common driver 431 ... Y side driver odd common driver 432 ... Y side driver even common driver 450 ... S side driver scan driver

Claims (10)

  An image display comprising a display panel having a first electrode for applying a scan pulse for scanning, a second electrode and a third electrode for applying an AC voltage pulse for performing display, and an address electrode for applying an address pulse An image display apparatus, wherein the two first electrodes are electrically connected across the second electrode or the third electrode in the vertical direction.   The image display device according to claim 1, wherein the first electrode, the second electrode, and the third electrode are provided on a front substrate, the address electrode is provided on a rear substrate, and the front substrate and the rear substrate. An image display device characterized in that a discharge space is formed between the two and facing each other.   The image display device according to claim 1, wherein each connection portion to which the two first electrodes are electrically connected is provided inside the display panel. 2. The image display device according to claim 1, wherein the first electrode is a scanning electrode, the second electrode is an X electrode, and the third electrode is a Y electrode, and the image display device further includes: ,
A scan driver for applying the scan pulse to the scan electrode;
An image display apparatus comprising: an X electrode common driver and a Y electrode common driver that apply an AC voltage pulse for performing the display to the X electrode and the Y electrode.   5. The image display device according to claim 4, wherein the X electrode common driver and the Y electrode common driver are disposed on both sides of the display panel.   The image display device according to claim 4, further comprising an address-side driver that sequentially applies data pulses to the address electrodes, the address-side driver having a delay circuit for performing delayed transfer of pixel data, In outputting the data pulse corresponding to the pixel data to the address electrode, an image display device is set so that a delay time becomes longer as a distance of the scan electrode from the scan driver becomes longer. A method for driving the image display device according to claim 1,
An initialization process for making the charged state of all the cells constituting the screen uniform, and applying a scan pulse to the first electrode and forming data on the address electrode in order to form a wall charge on the cell to be lit An address process for applying a pulse and a display process for applying an AC voltage pulse between the second electrode and the third electrode, which serve as display electrodes, in order to maintain the wall charge of the lighting cell in which the wall charges are formed are repeated. An image display apparatus driving method comprising: executing the image display apparatus;   8. The method for driving an image display device according to claim 7, wherein a reset pulse for making the charged state uniform is applied to the first electrode.   8. The method of driving an image display device according to claim 7, wherein the potential of the first electrode is made floating in the display process.   8. The method for driving an image display device according to claim 7, wherein the potential of the first electrode is clamped to a fixed potential in the display process.

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