JP2005266971A - Switch circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a switch circuit for suppressing inrush currents to be generated when currents are supplied from a power source part to a load component by simple configuration. <P>SOLUTION: A resistance value R<SB>16</SB>of a resistance 16 is set to be larger than a resistance value R<SB>17</SB>of a resistance 17, and a potential V<SB>GS1</SB>to be generated between the gate/source of an MOS-FET 12 when an ON signal is inputted to a transistor 13 is controlled to be sufficiently smaller than a potential V<SB>GS2</SB>to be generated between the gate/source of the MOS-FET 12 when an ON signal is inputted to a transistor 14. It is therefore possible to suppress inrush currents to be generated when a power is supplied from a power source part 10, that is, the quantity of current for charging the input side capacitor of a power source stabilizing part 11. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a switch circuit having a function of suppressing, for example, an inrush current from a DC power supply to a load component having a capacitor on the input side.

  FIG. 2 is a circuit diagram showing a conventional switch circuit. 2 shows a conventional switch circuit. The switch circuit 2 includes a power supply unit 20 that applies a predetermined voltage, a power supply stabilization unit 21 that stabilizes the voltage applied by the power supply unit 20, and a power supply stabilization unit 21. Both ends are connected to a MOS-FET (Metal Oxide Semiconductor-Field Effect Transistor) 22 having a drain 22D connected to the power source unit 20 and a source 22S to the power supply unit 20, and a source 22S and a gate 22G of the MOS-FET 22. And a resistor 25 having one end connected to the gate 22G of the MOS-FET 22 and a MOS-transistor (hereinafter referred to as a transistor) 23 having a collector connected to the other end of the resistor 25. The emitter of the transistor 23 is grounded, and an ON signal is input to the base of the transistor 23 from an input control unit (not shown) via the resistor 23a.

In the switch circuit 2 configured as described above, when an ON signal is input from the input control unit to the base of the transistor 23, a current flows through the resistors 24 and 25, and a potential V _GS is generated between the gate and source of the MOS-FET 22. Thus, the MOS-FET 22 becomes conductive. As a result, the current from the power supply unit 20 is input to the power supply stabilization unit 21 via the MOS-FET 22. When various electronic devices are provided with the switch circuit 2 having the above-described configuration, the voltage (current) smoothed by the power supply stabilization unit 21 is applied (applied) to each hardware unit mounted on the electronic device. And stable power can be supplied to each part of the hardware.
Japanese Patent Laid-Open No. 7-5937

  However, in the switch circuit 2 having the above-described configuration, the power supply stabilization unit 21 has a capacitor (not shown) on the input side, and the MOS-FET 22 is turned on so that the current from the power supply unit 20 is supplied to the power supply stabilization unit 21. Inrush current occurs when input. When the generated inrush current exceeds the rated current of the MOS-FET 22, there is a problem that the MOS-FET 22 may be damaged. Moreover, although the above-mentioned problem can be solved to some extent by using a MOS-FET having a large rated current, there is a problem in that the cost increases by using an expensive MOS-FET.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a switch circuit that can suppress an inrush current generated when a current from a power supply unit is supplied to a load component with a simple configuration. And

  The switch circuit according to the present invention is a switch circuit having a semiconductor element that supplies power from a DC power source to a load component, and the semiconductor element has a characteristic that an internal resistance value changes according to a signal from the outside. A first input unit for inputting a first signal to the semiconductor element, and a second input unit for inputting a second signal to the semiconductor element after a predetermined time has elapsed from the input of the first signal by the first input unit. The semiconductor element is configured such that the internal resistance value when the first signal is input is larger than the internal resistance value when the second signal is input. It is characterized by being.

  In the case of the present invention, the semiconductor element connected in series between the DC power supply and the load component has a characteristic that the internal resistance value changes in accordance with a signal from the outside. The internal resistance value when one signal is input is configured to be larger than the internal resistance value when the second signal is input by the second input unit. Further, the second input unit is configured to input the second signal to the semiconductor element after a predetermined time has elapsed from the input of the first signal. Therefore, when the current from the DC power source is turned on, the amount of inrush current generated can be suppressed by largely controlling the resistance value inside the semiconductor element.

  In the switch circuit according to the present invention, a field effect transistor having a source and a drain connected to each of a DC power supply and a load component controls the amount of current from the DC power supply to the load component according to a voltage applied to the gate. A first switch and a second switch for applying a voltage to the gate of the field effect transistor according to an external control signal; and a source and a gate of the field effect transistor through a predetermined resistor. Are connected, and each of the other ends includes a first resistor connected to each of the first switch and the second switch, and a second resistor having a resistance value smaller than the resistance value of the first resistor. The switch is configured to acquire the control signal from the outside after a predetermined time has elapsed since the first switch acquired the control signal from the outside. It is characterized in.

  According to the present invention, a field effect transistor having a source and a drain connected to each of a DC power supply and a load component, and a first resistor having one end connected to the source and gate of the field effect transistor via a predetermined resistor And a second resistor having a resistance value smaller than the resistance value of the first resistor, a first switch connected to the other end of the first resistor, and a second switch connected to the other end of the second resistor Is provided. The first switch and the second switch are configured to apply a voltage to the gate of the field effect transistor in accordance with an external control signal.

  The second switch is configured to acquire the control signal from the outside after a predetermined time has elapsed since the first switch has acquired the control signal from the outside. When a voltage is applied from the first switch connected to the field effect transistor to the gate of the field effect transistor through the first resistor having a resistance value larger than the resistance value of the resistor, the second switch acquires the control signal. As compared with the above, it becomes possible to apply a large voltage to the gate of the field effect transistor. Further, since the gate of the field effect transistor is connected to the DC power source, the potential between the gate and source of the field effect transistor when the current from the DC power source is turned on is compared with the case where the second switch acquires the control signal. Thus, the current value of the inrush current supplied from the DC power source to the load component via the field effect transistor can be suppressed.

  According to the present invention, when a current is supplied from a DC power source to a load component, a first signal is first input to a semiconductor element connected in series between the DC power source and the load component by a first input unit, After the elapse of time, the second signal is input from the second input unit. The internal resistance value of the semiconductor element when the first signal is input is configured to be larger than that when the second signal is input. The amount of inrush current can be suppressed, thereby avoiding damage to various electronic components constituting the power supply circuit.

  According to the present invention, when a current is supplied from a DC power supply to a load component, the gate of the field effect transistor having a source and a drain connected to each of the DC power supply and the load component is larger than the resistance value of the second resistor. By applying a voltage through the first resistor having a resistance value, a voltage larger than the voltage applied through the second resistor can be applied to the gate of the field effect transistor. In this case, the potential between the gate and the source of the field effect transistor can be reduced, and the amount of inrush current input from the DC power supply to the load component via the field effect transistor can be suppressed. Thereby, it is possible to avoid breakage of various electronic components constituting the power supply circuit.

  Hereinafter, a switch circuit according to the present invention will be described in detail with reference to the drawings showing embodiments thereof. FIG. 1 is a circuit diagram showing a switch circuit according to the present invention. 1 shows a switch circuit according to the present invention. The switch circuit 1 includes a power supply unit (DC power supply) 10 that applies a predetermined voltage Vcc, and a power supply stabilization unit that stabilizes the voltage applied by the power supply unit 10. (Load component) 11. The power supply stabilizing unit 11 includes an input smoothing capacitor (not shown) on the connection side with the power supply unit 10, and thereby, hardware components (loads) mounted on the electronic device including the switch circuit 1. A stable voltage smoothed by the power supply stabilizing unit 11 can be applied to the component.

The switch circuit 1 includes a drain 12D connected to the power supply stabilization unit 11, a source 12S connected to the power supply unit 10, and a MOS-FET (semiconductor element) 12 connected in series between the power supply unit 10 and the power supply stabilization unit 11. I have. MOS-FET 12 has a characteristic that the resistance value of the internal changes in accordance with the potential V _GS that occurs between the gate and the source, as the potential V _GS that occurs between the gate and source becomes small, the internal resistance The current increases from the source 12S to the drain 12D.

  Further, the switch circuit 1 includes a resistor (predetermined resistor) 15 having both ends connected to the source 12S and the gate 12G of the MOS-FET 12, and a resistor (first resistor) having one end connected to the gate 12G of the MOS-FET 12. 1 resistor, second resistor) 16, 17; a MOS-transistor (hereinafter referred to as a transistor) 13 as a first switch having a collector connected to the other end of the resistor 16; and a collector connected to the other end of the resistor 17. And a transistor 14 as a second switch. Accordingly, the transistors 13 and 14 that are two switches and the two resistors 16 and 17 connected to the transistors 13 and 14 are connected in parallel to the gate 12G of the MOS-FET 12.

The emitters of the transistors 13 and 14 are grounded. An ON signal (control signal) is input to the bases of the transistors 13 and 14 from an input control unit (not shown) via the resistors 13a and 14a, respectively. Here, the resistance value R ₁₆ of the resistor ₁₆ is set to a sufficiently large value as compared with the resistance value R ₁₇ of the resistor 17. Also, the ON signal input to the bases of the transistors 13 and 14 is such that the ON signal is input to the transistor 14 after a predetermined time has elapsed after the ON signal to the transistor 13 is input first. Is set.

With the configuration described above, in the switch circuit 1, when an ON signal is input from the input control unit to the base of the transistor 13, the current from the power supply unit 10 is input to the resistors 15 and 16. In this case, a voltage V _{1 of} Vcc · R ₁₆ / (R ₁₅ + R ₁₆ ) is applied to the gate 12 G of the MOS-FET 12, and the transistor 13 and the resistor 16 are connected to the gate 12 G of the MOS-FET 12. It operates as a first input section for inputting (applying) one signal (voltage V ₁ ). R ₁₅ and R ₁₆ indicate resistance values of the resistors 15 and ₁₆ , respectively.

As a result, a potential V _GS1 = Vcc · R ₁₅ / (R ₁₅ + R ₁₆ ) is generated between the gate and source of the MOS-FET 12, and a current corresponding to the generated potential V _GS1 is supplied via the MOS-FET 12 to the power supply unit 10. Flows from the power source to the power source stabilization unit 11.

The input control unit has a timer (not shown), and inputs an ON signal to the base of the transistor 14 after a predetermined time has elapsed since the ON signal was input to the base of the transistor 13. When an ON signal is input from the input control unit to the base of the transistor 14, the current from the power supply unit 10 is input not only to the resistors 15 and 16 but also to the resistor 17. In this case, a voltage V _{2 of} Vcc · R ₁₆ / (R ₁₅ + R ₁₆ ) is applied to the gate 12 G of the MOS-FET 12, and the transistor 14 and the resistor 17 are connected to the gate 12 G of the MOS-FET 12. It operates as a second input unit for inputting (applying) two signals (voltage V ₂ ). R ₁₇ represents the resistance value of the resistor 17.

As a result, a potential V _GS2 = Vcc · R ₁₆ R ₁₇ / (R ₁₅ R ₁₆ + R ₁₅ R ₁₇ + R ₁₆ R ₁₇ ) is generated between the gate and source of the MOS-FET 12, and a current corresponding to the generated potential V _GS2 is generated. Flows from the power supply unit 10 to the power supply stabilization unit 11 via the MOS-FET 12. Normally, when an ON signal is input to the base of the transistor 14 and the voltage V ₂ is applied to the gate 12G of the MOS-FET 12, the MOS-FET 12 becomes conductive.

Here, since the resistance value R ₁₆ of the resistor ₁₆ is sufficiently larger than the resistance value R ₁₇ of the resistor 17, the potential generated between the gate and the source of the MOS-FET 12 when an ON signal is input to the transistor 13. V _GS1 can be controlled to be sufficiently smaller than the potential V _GS2 generated between the gate and source of the MOS-FET 12 when an ON signal is input to the transistor 14. Since the MOS-FET 12 has a characteristic that the internal resistance increases as the potential V _GS generated between the gate and the source decreases, and the amount of current flowing from the source 12S to the drain 12D decreases. The amount of charging current for charging the capacitor on the input side of the stabilizing unit 11 can be suppressed. Further, since the amount of inrush current can be suppressed, a MOS-FET with a small rated current can be used, and the MOS-FET can be reduced in size and cost.

  As described above, by inputting an ON signal only to the transistor 13 when power is supplied from the power supply unit 10, an inrush current to the capacitor on the input side of the power supply stabilization unit 11 can be suppressed. Damage can be avoided. In addition, after a period of time that the capacitor is sufficiently charged has elapsed, an ON signal is input to the transistor 14 to turn on the MOS-FET 12, thereby preventing the inrush current from occurring again. Note that the predetermined time from when the transistor 13 acquires the on signal to when the transistor 14 acquires the on signal is the rating of the MOS-FET 12 when the MOS-FET 12 is turned on (when the transistor 14 acquires the on signal). It is sufficient if the capacitor on the input side of the power stabilizing unit 11 is charged to such an extent that a current amount that does not exceed the current flows in the MOS-FET 12, and it may not be a time that the capacitor charging is sufficiently completed. .

  Therefore, by appropriately configuring the switch circuit 1 so that the inrush current that may occur does not exceed the rated current of the MOS-FET 12, it is possible to prevent damage to other electronic components including the MOS-FET 12. . In the embodiment described above, a MOS-transistor is used as a switch (semiconductor switch). However, the present invention is not limited to this, and a bipolar transistor, a diode, or the like can also be used.

It is a circuit diagram which shows the switch circuit based on this invention. It is a circuit diagram which shows the conventional switch circuit.

Explanation of symbols

1 Switch circuit 10 Power supply (DC power supply)
11 Power supply stabilizer (load component)
12 MOS-FET (semiconductor element)
13 MOS-transistor (first switch)
14 MOS-transistor (second switch)
16 Resistance (first resistance)
17 Resistance (second resistance)

Claims (2)

In a switch circuit having a semiconductor element for supplying power from a DC power source to a load component,
The semiconductor element has a characteristic that an internal resistance value changes according to an external signal,
A first input unit for inputting a first signal to the semiconductor element;
A second input unit for inputting a second signal to the semiconductor element after a predetermined time has elapsed from the input of the first signal by the first input unit;
The semiconductor element is configured such that the internal resistance value when the first signal is input is larger than the internal resistance value when the second signal is input. Switch circuit. In a switch circuit in which a field effect transistor having a source and a drain connected to each of a DC power supply and a load component controls the amount of current from the DC power supply to the load component according to a voltage applied to a gate,
A first switch and a second switch for applying a voltage to the gate of the field effect transistor in response to an external control signal;
A first resistor having one end connected to the source and gate of the field effect transistor via a predetermined resistor and the other end connected to each of the first switch and the second switch, and the resistance of the first resistor A second resistor having a resistance value smaller than the value,
The switch circuit, wherein the second switch is configured to acquire a control signal from the outside after a predetermined time has elapsed since the first switch acquired the control signal from the outside.

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