JP2005260264A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having an MT-MOS structure with a small leakage current and an excellent current driving capability, and a manufacturing method thereof.
SOLUTION: On a substrate region 1a of a semiconductor substrate 1, first and second nMOSFETs having a gate insulating film 7, a gate electrode 8, a sidewall 13, a source / drain region 14, an LDD region 11, and a pocket region 9 are provided. Is provided. Only the first nMOSFET further includes a p-type channel region 4 having a higher concentration than the substrate region 1a. The inversion voltage of the first nMOSFET is determined by the impurity concentration of the channel region 4 and the pocket region 9. Since the inversion voltage of the second nMOSFET is determined by the impurity concentration of the substrate region 1a and the pocket region 9, by using the low concentration substrate region 1a as the channel region, the depletion layer capacitance is reduced, the subthreshold characteristic is improved, Leakage current can be reduced.
[Selection] Figure 1

Description

  The present invention provides a semiconductor device and a method for manufacturing the same, which are equipped with two types of MISFETs having different inversion voltages, are suitable for high speed and low power consumption, and are low in manufacturing cost.

  In recent years, when developing semiconductor devices so-called LSIs with MISFETs mounted at high density, high speed and low power consumption are major goals, but it is extremely difficult to achieve these two factors at the same time. In other words, there is a close relationship between the operating speed of the MOS device, the inversion voltage, and the power consumption. If the inversion voltage is lowered to increase the speed, the diffusion current increases and the power consumption during OFF increases. An off relationship exists.

  Therefore, as one of the methods proposed to solve this trade-off, there is a Multithreshold Voltage CMOS device (hereinafter abbreviated as MT-CMOS device). This means that a MOSFET with a low inversion voltage is used for a portion that requires high speed in terms of circuit, and that a leakage current path is cut off with a MOSFET with a high inversion voltage. To realize this circuit configuration, Both the nMOS device and the pMOS device need to be composed of MOSFETs having at least two types of inversion voltages.

  Hereinafter, an example of a conventional method for manufacturing an MT-CMOS device will be described with reference to the drawings.

  30A to 30D show an example of a conventional manufacturing method of an nMOS device on which an nMOSFET having two types of inversion voltages is mounted.

In the step shown in FIG. 30A, after forming the element isolation 3 that partitions the semiconductor substrate 1 pre-doped with p-type impurities into a number of MOSFET formation regions, an nMOSFET having a high inversion voltage (hereinafter referred to as a first nMOSFET). ) Is formed on the first nMOSFET formation region Rn1, and the resist film 16a having an opening above the second nMOSFET formation region Rn2 which is a region for forming an nMOSFET having a low inversion voltage (hereinafter referred to as a second nMOSFET). Then, using this resist film 16a as a mask, boron ions (B +) are implanted into the semiconductor substrate 1 in the second nMOSFET formation region Rn2, thereby forming the channel region 5 of the second MOSFET. The implantation conditions are, for example, 20-60 KeV, 1-2 × 10 ¹² cm ⁻² .

Next, in the step shown in FIG. 30B, a resist film 16b having an opening above the first MOSFET formation region Rn1 is formed, and the first nMOSFET formation region Rn1 is higher than the channel region 5 of the second nMOSFET formation region Rn2. A concentration of boron ions (B +) is implanted to form the channel region 4 of the high inversion voltage MOSFET. The implantation conditions are, for example, 20-60 KeV, 4-6 × 10 ¹² cm ⁻² .

  Next, in the step shown in FIG. 30C, the surface of the semiconductor substrate 1 is oxidized to form a gate insulating film 7 having a thickness of 8-12 nm, and a polysilicon film having a thickness of 200-300 nm is deposited on the entire surface. Thereafter, the gate electrode 8 is formed through a normal photolithography process and an etching process. Next, by using the gate electrode 8 as a mask, low concentration phosphorus ions (P +) are implanted to form an n− type LDD region 11.

  Next, in the step shown in FIG. 30D, sidewalls 13 are formed on each side surface of the gate electrode 8, and high-concentration arsenic ions (As +) are implanted using the gate electrode 8 and the sidewalls 13 as a mask. , N + -type source / drain regions 14 are formed. Next, in order to activate the arsenic ions in the source / drain regions 14 and recover crystal defects, a heat treatment at 900 ° C. for 30 minutes is introduced.

  The operation of the nMOS device formed by the above manufacturing process will be described below.

  In the structure of the nMOS device formed by such a manufacturing process, the inversion voltages of the first MOSFET and the second MOSFET are determined by the impurity concentration in the channel regions 4 and 5, and are 0.5-0.6V, 0.2-0. It is about 3V. In general, the second MOSFET has a large current driving capability and is suitable for speeding up, but has a large leakage current at the time of off. On the other hand, the first MOSFET has a small current driving capability but a small off leakage current and is suitable for low power consumption. Therefore, by properly using these two types of MOSFETs depending on the circuit configuration, a high-speed and low-power consumption LSI can be configured.

  Further, a normal conventional complementary MOS (CMOS) device is basically formed by the manufacturing process shown in FIGS.

  First, in the step shown in FIG. 31A, a p-type substrate region 22a (a region having the same impurity concentration as that of the p-type semiconductor substrate 21 in this conventional example) is formed in the nMOSFET formation region Rn, and n in the pMOSFET formation region Rp. A type substrate region 22b (n-well) is provided, and an element isolation 23 for separating the p-type substrate region 22a and the n-type substrate region 22b is provided. Next, a gate oxide film 24 having a thickness of 4 to 8 nm and a gate electrode 35 having a thickness of 100 to 200 nm are formed on the p-type semiconductor substrate 21.

Next, in the step shown in FIG. 31B, arsenic ions (As +) are implanted into the gate electrode 35 of the nMOSFET and the regions 38 located on both sides of the gate electrode 35 in the p-type substrate region 22a. The injection conditions are, for example, an acceleration energy of 30 to 60 keV and an injection amount of 6 to 8 × 10 ¹⁵ cm ⁻² . On the other hand, boron fluoride ions (BF2 +) are implanted into the gate electrode 35 of the pMOSFET and the regions 39 located on both sides of the gate electrode 35 in the n-type substrate region 22b. The implantation conditions are, for example, an acceleration energy of 10 to 30 keV and an implantation amount of 3 to 6 × 10 ¹⁵ cm ⁻² .

  Finally, in the step shown in FIG. 31C, heat treatment (RTA) is performed at 1000 ° C. for 10 seconds to activate the impurity ions. By this heat treatment, in the nMOSFET formation region Rn, the resistance of the gate electrode 35 is reduced to form the n-type gate electrode 35a, and the n-type source / drain region 38a is formed in the p-type substrate region 22a, while in the pMOSFET formation region Rp Reduces the resistance of the gate electrode 35 to a p-type gate electrode 35b, and forms a p-type source / drain region 39a in the n-type substrate region 22b.

  However, the MT-MOS device as shown in FIGS. 30A to 30D and the manufacturing method thereof have the following problems.

  1. The number of processes increases as compared with a normal MOS device. In particular, two types of photomasks are required to control the inversion voltage, which increases the cost.

  2. Since the impurity concentration of the channel region functioning as the channel region of the low inversion voltage MOSFET is smaller than that of the high inversion voltage MOSFET, the breakdown voltage is degraded, and the short channel effect is increased. Here, the short channel effect is a phenomenon in which various characteristics of the MOSFET are deteriorated in the short channel region as compared with the long channel region. For example, the inversion voltage in the short channel region is lowered and the leakage current is increased. There is a problem of doing.

  Further, the MOSFET and its manufacturing method shown in FIGS. 31A to 31C have the following problems.

  3. In the drain region 38a of the nMOSFET, a leakage current at the junction is large due to a crystal defect formed by arsenic ion implantation.

  4). In the drain region 38a of the nMOSFET, the electric field is relatively large and a GIDL (Gate Induced Drain Leakage) current is large.

  5). Since the profile is steep in the drain region 38a of the nMOSFET, the parasitic capacitance of the junction increases.

  6). The electric field in the vicinity of the drain region 38a of the nMOSFET is large, and carriers are likely to cause impact ionization. For this reason, deterioration with the passage of time such as a decrease in the drain current of the MOSFET or a change in the threshold value of the MOSFET is large. That is, the reliability is low.

  Further, the following problems 7 and 8 occur in the CMOS device.

  7). Due to the difference between the diffusion coefficient of arsenic and the diffusion coefficient of boron, the effective channel length of the p-type MOSFET becomes too shorter than the effective channel length of the nMOSFET, and the balance of both transistors deteriorates in terms of performance.

  8). The depletion of the gate electrode 35a of the nMOSFET and the boron ion penetration of the pMOSFE gate electrode 35b cannot be suppressed at the same time. That is, if heat treatment is performed for a short time such as RTA (for example, 1000 ° C., 10 seconds), the activation of arsenic ions in the gate electrode 35a of the nMOSFET is insufficient and depletion occurs, and the driving force may be reduced. There is. On the other hand, if heat treatment is performed for a long time (for example, 900 ° C., 30 minutes), boron ions in the gate electrode 35b of the pMOSFET may diffuse into the channel region and deteriorate the device characteristics.

  The first object of the present invention is to mount two types of MOSFETs, a high inversion voltage FET and a low inversion voltage FET, on the same semiconductor substrate, and also in the low inversion voltage MOSFET, the characteristics in the short channel region are good, and It is an object of the present invention to provide a semiconductor device having a structure that does not increase the number of steps and a method for manufacturing the same. That is, the above problems 1 and 2 are to be solved.

  The second object of the present invention is to improve the operation speed by reducing the parasitic capacitance, reduce the leakage current, and improve the reliability in the MIS transistor formed by simultaneously implanting impurity ions into the gate electrode and the source / drain regions. It is to improve. In other words, the above problems 3 to 8 are to be solved.

  The semiconductor device according to the present invention is a semiconductor device having at least an nMISFET formed on a part of a semiconductor substrate, wherein the nMISFET is formed on the gate insulating film formed on the semiconductor substrate and on the gate insulating film. A gate electrode into which at least fluorine-containing impurities and phosphorus are introduced, and an n-type semiconductor device formed in regions located on both sides of the gate electrode of the semiconductor substrate and into which at least fluorine-containing impurities and phosphorus are introduced. Source / drain regions.

  The method for manufacturing a semiconductor device according to the present invention includes a first step of forming a gate insulating film on an nMISFET formation region in a semiconductor substrate, and a second step of forming a gate electrode on the gate insulating film. A third step of introducing an impurity containing at least fluorine into the gate electrode and regions located on both sides of the gate electrode in the semiconductor substrate in the nMISFET formation region; and the third step. After or before, in the nMISFET formation region, a fourth step of introducing phosphorus into the gate electrode and regions located on both sides of the gate electrode in the semiconductor substrate; and the third and fourth steps After the step, the phosphorus is diffused and activated by heat treatment to make the gate electrode a low-resistance n-type gate electrode and on both sides of the gate electrode in the semiconductor substrate. And a fifth step of forming a n-type source and drain regions in the regions located.

  In each of the following embodiments, a typical case where the gate insulating film is an oxide film, that is, an embodiment of a semiconductor device having a MOSFET will be described. However, the present invention is not limited to the MOSFET, and the gate insulating film However, it can also be applied to oxynitride films and nitride films.

(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS. 1, 2, and 3 (a) to 3 (d).

  FIG. 1 is a cross-sectional view of the MT-nMOS device according to the first embodiment. As shown in FIG. 1, a region in the vicinity of the surface of a semiconductor substrate 1 made of a silicon single crystal doped with a p-type impurity is partitioned into a large number of active regions by element isolation 3 made of an oxide film. Each active region is provided with a first nMOSFET formation region Rn1 for forming a high inversion voltage type first nMOSFET and a second nMOSFET formation region Rn2 for forming a low inversion voltage type second nMOSFET. In the first and second nMOSFET formation regions Rn1 and Rn2, a gate insulating film 7 made of a silicon oxide film, a gate electrode 8 made of a polysilicon film provided on the gate insulating film 7, and a gate electrode 8 An insulator sidewall 13 made of a silicon oxide film formed on each side surface is provided. In the first nMOSFET formation region Rn1, a channel region 4 is formed by injecting a p-type impurity for VT control having a concentration higher than the impurity concentration in the semiconductor substrate 1 below the gate electrode 8. In addition, each active region and a region below the element isolation form a substrate region 1a. In the second nMOSFET formation region Rn2, the substrate region 1a immediately below the gate insulating film 7 functions as a channel region.

  In each of the nMOSFET formation regions Rn1 and Rn2, n + type regions formed by implanting a pair of high-concentration n-type impurities into regions located on both sides of the gate electrode 8 in the semiconductor substrate 1. A source / drain region 14, an n − -type LDD region 11 including a low-concentration n-type impurity formed between the channel region and each source / drain region 14, and formed so as to surround the LDD region 11 and the source / drain region 14. A p-type pocket region 9 serving as a punch-through stopper is formed. As described above, the first nMOSFET formed in the first nMOSFET formation region Rn1 has a high inversion voltage because the impurity concentration in the channel region 4 is high, and the MOSFET formed in the second nMOSFET formation region Rn2 serves as a channel region. Since the impurity concentration in the substrate 1 is low, the inversion voltage is low.

  In the structure shown in FIG. 1, in this embodiment, the channel region of the second nMOSFET is configured by the semiconductor substrate 1 itself, that is, the substrate region 1a, but may be configured by a p-type well. In this embodiment, the substrate region 1a in the first and second nMOSFET formation regions Rn1 and Rn2 is a common region, but the substrate regions of the first and second nMOSFET formation regions Rn1 and Rn2 have different impurity concentrations. You may partition so that it may become an area | region.

  Therefore, in the structure of the MT-nMOS device according to this embodiment, the inversion voltage of the n1MOSFET is determined by the concentration of the p-type impurity in the channel region 4 and the pocket region 9, and the inversion voltage of the second nMOSFET is the substrate region that becomes the channel region. 1a and the concentration of p-type impurities in the pocket region 9 are determined. In that case, in the nMOSFET provided with the pocket region 9, even if the impurity concentration of the channel region is lower than that of a normal nMOSFET, the punch through and the short channel effect can be suppressed due to the presence of the pocket region 9, so that no problem occurs. By reducing the impurity concentration of the channel region, the extension of the depletion layer immediately below the gate insulating film 7 is increased, and the depletion layer capacitance is reduced. Therefore, the subthreshold characteristic is improved and the leakage current can be reduced. This effect is more remarkable in the second nMOSFET.

  FIG. 2 is a cross-sectional view showing a state in which a substrate bias of −2 V is applied to the substrate region 1a of the MT-nMOS device having the structure of FIG. In the case of an MT-pMOS device, a positive substrate bias (for example, about 2 V) is applied. In general, when a negative substrate bias is applied to an nMOSFET or a positive substrate bias is applied to a pMOSFET, the inversion voltage increases. A proportional constant indicating the increase rate of the inversion voltage with respect to the increase in the substrate bias is called a substrate effect constant. Since this substrate effect constant is substantially proportional to the impurity concentration of the channel region of the MOSFET, in this embodiment, the first nMOSFET has a larger substrate effect constant than the second nMOSFET. That is, when the same substrate bias is applied, the first nMOSFET has a larger inversion voltage and shifts in the positive direction. This means that applying a substrate bias further increases the difference in inversion voltage between the first nMOSFET and the second nMOSFET, and characteristics such as high speed and low power consumption, which are advantages of the MT-MOS device, are further improved. .

  In addition, applying a substrate bias makes it more resistant to external noise and improves the reliability of memory and the like.

  In particular, as in the present embodiment, when the channel region of the second nMOSFET is configured by the substrate region 1a (or well) of the semiconductor substrate 1, the substrate effect constant is extremely higher than the structure of the conventional MT-nMOS device shown in FIG. The remarkable effect of being small is obtained. For example, in the structure of a conventional MT-nMOS device, the increase amount of the inversion voltage when a substrate bias of −2 V is applied is about 0.3 V for the first nMOSFET and about 0.2 V for the second nMOSFET. On the other hand, in the structure of the MT-nMOS device according to the present embodiment, if the increase amount of the inversion voltage of the first nMOSFET is 0.2V, the increase amount of the inversion voltage of the second nMOSFET is about 0.03V. That is, since the inversion voltage value of the second nMOSFET hardly increases, it can be seen that the enlargement ratio of the difference from the inversion voltage with respect to the first nMOSFE is remarkably increased by applying the substrate bias.

  Next, a manufacturing process of the MT-nMOS device according to the present embodiment will be described with reference to FIGS.

First, in the step shown in FIG. 3A, a LOCOS method, a trench is formed on a substrate region 1a of a semiconductor substrate 1 made of a silicon single crystal doped with a p-type impurity having a threshold control level concentration of the second nMOSFET. An element isolation 3 made of a silicon oxide film having a thickness of about 400 nm is formed using an isolation method or the like, and the first nMOSFET formation region Rn1 and the second nMOSFET formation region Rn2 are partitioned by the element isolation 3. Then, a resist film 16c having an opening in the first nMOSFET formation region Rn1 is formed by a normal photolithography process, and boron ions (B +) are implanted into the first nMOSFET formation region Rn1 using the resist film 16c as a mask. Thereby, the channel region 4 of the first nMOSFET is formed. The ion implantation conditions at this time are 20-60 KeV, 2-4 × 10 ¹² cm ⁻² .

Next, in the step shown in FIG. 3B, a silicon oxide film having a thickness of 8-12 nm is deposited on the entire surface of the substrate, and a polysilicon film having a thickness of 250-300 nm is further deposited thereon. The gate electrode 8 and the gate insulating film 7 are patterned by a photolithography process and an etching process. Next, boron ions (B +) (however, BF 2 + may be used in the following) with this gate electrode 8 as a mask are implanted under the conditions of 20-30 KeV, 5-10 × 10 ¹² cm ^−2. A p-type pocket region 9 is formed in each of the nMOSFET formation regions Rn1 and Rn2.

Next, in the step shown in FIG. 3C, phosphorus ions (P +) are implanted under the conditions of 30-40 KeV, 2-8 × 10 ¹³ cm ^{−2 using} the gate electrode 8 as a mask, thereby forming the LDD region 11. To do.

Next, in the step shown in FIG. 3 (d), sidewalls 13 are formed on each side surface of the gate electrode 8, and arsenic ions are used at 4-6 × 10 ¹⁴ cm ⁻ at 40 KeV using the gate electrode 8 and the sidewalls 13 as a mask. ^The source / drain region 14 is formed by implantation under the conditions of ² .

  It can be seen that the MT-nMOS device having the structure shown in FIG. In particular, in the manufacturing process shown in FIGS. 3A to 3D, only one photomask is required for implantation of impurity ions for controlling the inversion voltage of the nMOSFET. Therefore, the manufacturing process can be simplified compared with the conventional method (see FIGS. 30A and 30B) that requires two photomasks 16a and 16b for impurity ion implantation for controlling the inversion voltage. There is an advantage that the cost can be reduced.

(Second Embodiment)
Next, an MT-nMOS device according to the second embodiment will be described with reference to FIG.

  As shown in FIG. 4, in this embodiment as well, as in the MT-nMOS device according to the first embodiment, the region near the surface of the semiconductor substrate 1 doped with p-type impurities is separated by the element isolation 3. The first nMOSFET formation region Rn1 and the second nMOSFET formation region Rn2 are partitioned. A first nMOSFET is formed in the first nMOSFET formation region Rn1, and a second nMOSFET is formed in the second nMOSFET formation region Rn2. Here, in this embodiment, the structure of the first nMOSFET is the same as that of the first embodiment, and the gate insulating film 7, the gate electrode 8, the sidewall 13, the channel region 4, the source / drain region 14, and the LDD region. 11 and a pocket region 9 are provided. However, in the second nMOSFET, although the gate insulating film 7, the gate electrode 8, the sidewall 13, the source / drain region 14 and the LDD region 11 are provided, the pocket region is not provided. A channel region 5 formed by implanting p-type impurities into the semiconductor substrate 1 is formed immediately below the gate insulating film 7 of the second nMOSFET. In other words, in this embodiment, the channel regions 4 and 5 are formed on the substrate region 1a in both the first and second nMOSFETs, and the impurity concentration in both is the same. The pocket region is provided only in the first nMOSFET.

  In the MT-nMOS device according to the present embodiment, the inversion voltage of the first nMOSFET is determined by the impurity concentration of the channel region 4 and the pocket region 9, and the inversion voltage of the second nMOSFET is determined by the impurity concentration of the channel region 5. In this case, since the first nMOSFET is provided with the pocket region 9, the impurity concentration in the channel region can be lowered, so that the gate depletion layer capacitance is small and the subthreshold characteristic is excellent as in the first embodiment. It has the characteristics. On the other hand, the second nMOSFET has substantially the same configuration as a normal nMOSFET, but sufficient characteristics can be obtained even with such a structure in a region of about 0.5 μm where the gate length is relatively large. In particular, the nMOSFET having the structure and the long channel region (gate length) as in this embodiment has an advantage that the design can be facilitated because there is little variation in characteristics in the manufacturing process.

  Although detailed description and illustration of the manufacturing process of the MT-nMOS device according to the present embodiment are omitted, in the manufacturing process of the conventional MT-nMOS device shown in FIGS. Since the ion implantation for forming the channel region can be simultaneously performed on the second nMOSFET without using a mask, the number of steps can be reduced as compared with the conventional manufacturing method. However, a process for forming the pocket region 9 in the first nMOSFET formation region Rn1 is separately required.

(Third embodiment)
Next, an MT-CMOS device according to a third embodiment will be described with reference to FIGS. 5, 6 and 7A to 7D.

  As shown in FIG. 5, in this embodiment, a p-type well 2a containing a p-type impurity and an n-type well 2b containing an n-type impurity are formed in a semiconductor substrate. A region near the surface of the p-type well 2a is an nMOSFET formation region Rn for forming an nMOSFET, and a region near the surface of the n-type well 2b is a pMOSFET formation region Rp for forming a pMOSFET. Furthermore, due to the element isolation 3, the nMOSFET formation region Rn is partitioned into a first nMOSFET formation region Rn1 and a second nMOSFET formation region Rn2, and the pMOSFET formation region Rp is partitioned into a first pMOSFET formation region Rp1 and a second pMOSFET formation region Rp2. . The first and second nMOSFETs formed in the first and second nMOSFET formation regions Rn1 and Rn2 have the same structure as that shown in FIG. 1 in the first embodiment. In addition, the structure of the first and second pMOSFETs is merely the reverse of the conductivity type of the impurity in the structure of the first and second nMOSFETs in the first embodiment. That is, the first pMOSFET includes a gate electrode 8, a gate insulating film 7, a sidewall 13, an n-type channel region 6, a p + -type source / drain region 15, a p − -type LDD region 12, and an n-type pocket region 10. On the other hand, in the second pMOSFET, the n-type well 2b corresponding to the substrate region 1a in the first embodiment functions as a channel region in the region below the gate electrode 8.

  The same effect as that of the first embodiment can be obtained by the structure of the MT-nMOS device among the MT-CMOS devices according to the present embodiment. Also in the structure of the MT-pMOS device, the inversion voltage of the first pMOSFET is determined by the concentration of n-type impurities in the channel region 6 and the pocket region 10, and the inversion voltage of the second pMOSFET is n-type in the n-type well 2b and the pocket region 10. It is determined by the concentration of impurities. Therefore, similar to the first embodiment, the subthreshold characteristic is good and the leakage current can be reduced.

  FIG. 6 shows a state in which a substrate bias of −2V is applied to the p-type well 2a of the MT-nMOS device according to the present embodiment, and a substrate bias of 2V is applied to the n-type well 2b of the MT-pMOS device. Thus, in the case of an MT-CMOS device, a negative bias is applied to the p-type well 2a of the MT-nMOS device, and a positive bias is applied to the n-type well 2b of the MT-pMOS device. The difference in inversion voltage between the first and second MOSFETs is increased, and the effect of adopting the MT-CMOS device structure is increased. In addition, it is resistant to external noise, and the reliability of the memory and the like is increased.

  Moreover, since the p-type well 2a and the n-type well 2b also function as channel regions of the second nMOSFET and the second pMOSFET, respectively, the substrate effect between the first and second MOSFETs is the same as described in the first embodiment. The difference in constants becomes remarkable, and an MT-CMOS device having extremely excellent characteristics can be constructed.

  Next, the manufacturing process of the MT-CMOS device according to this embodiment will be described with reference to FIGS.

First, in the step shown in FIG. 7A, a p-type well 2a and an n-type well 2b are formed on a semiconductor substrate made of single crystal silicon, and an element isolation comprising a silicon oxide film having a thickness of about 400 nm is formed. 3 is divided into a first nMOSFET formation region Rn1, a second nMOSFET formation region Rn2, a second pMOSFET formation region Rp2, and a first pMOSFET formation region Rp1. Then, by a normal photolithography process, a resist film 16d that opens only the first nMOSFET formation region Rn1 and covers the other regions Rn2, Rp2, and Rp1 is formed, and this resist film 16d is used as a mask in the first nMOSFET formation region Rn1. Boron ions (B +) are implanted to form the channel region 4 of the first nMOSFET. Impurity ion implantation conditions are 20-60 KeV, 2-4 × 10 ¹² cm ⁻² .

Next, in the process shown in FIG. 7B, a resist film 16e having an opening only in the first pMOSFET formation region Rp1 is formed by a normal photolithography process, and this resist film 16e is used as a mask in the first pMOSFET formation region Rp1. Phosphorus ions (P +) are implanted to form the channel region 6 of the first pMOSFET. The ion implantation conditions at this time are 30-80 KeV, 2-4 × 10 ¹² cm ⁻² .

Next, in the step shown in FIG. 7C, a silicon oxide film having a thickness of 8-12 nm is formed, and a polysilicon film having a thickness of 250-300 nm is further deposited thereon, and a normal lithography process and etching process are performed. Thus, the gate insulating film 7 and the gate electrode 8 are patterned. Next, using the resist film (not shown) covering the pMOSFET formation region Rp and the gate electrode 8 as a mask, boron ions (B + or BF2 +) are added to the nMOSFET formation Rn by 20-30 KeV, 5-10 × 10 5. Implantation is performed under the condition of ¹² cm ⁻² to form a p-type pocket region 9. Next, using a resist film (not shown) covering the nMOSFET formation region Rn and the gate electrode 8 as a mask, phosphorus ions (P +) are added to the pMOSFET formation region Rp at 80-120 KeV, 5-10 × 10 ¹² cm ^−. Implantation is performed under the conditions of ² to form an n-type pocket region 10.

Next, in the step shown in FIG. 7D, a resist film (not shown) having an opening above the nMOSFET formation region Rn and the gate electrode 8 are used as masks to add phosphorus ions (P +) to the nMOSFET formation region Rn. Implantation is performed under conditions of 40 KeV and 2-8 × 10 ¹³ cm ⁻² to form LDD regions 11 of the respective nMOSFETs. Further, using a resist film (not shown) opened above the pMOSFET forming region Rp and the gate electrode 8 as a mask, boron ions (B +) are 10-20 KeV, 2-8 × 10 ¹³ cm ^{−2 in the} pMOSFET forming region Rp. Then, the LDD region 12 of each pMOSFET is formed. However, in this step, the same resist film as that used for forming the pocket regions 9 and 10 is used, and the conductivity type of the impurities is changed to thereby form the pocket regions 9 and 10 in the regions Rn and Rp. Done continuously.

Next, after forming the sidewalls 13 on the respective side surfaces of the gate electrode 8, a resist film (not shown) in which each region Rn or Rp is opened, and the nMOSFET forming region Rn using the gate electrode 8 and the sidewall 13 as a mask. Arsenic ions (As +) are implanted under the conditions of 40 KeV and 4-6 × 10 ¹⁴ cm ⁻² , and boron ions (B +) are implanted into the pMOSFET formation region Rp at 10-20 KeV, 4-6 × 10 ¹⁴ cm 2. Implantation is performed under the condition of ^-2 , and source / drain regions 14 and 15 of each nMOSFET and each pMOSFET are formed.

  Through the above steps, the structure of the MT-CMOS device shown in FIG. 5 can be easily obtained. In particular, in the manufacturing method of the present embodiment, two photomasks for inversion voltage control are sufficient in the steps shown in FIGS. 7 (a) and 7 (b). On the other hand, when the conventional process shown in FIGS. 30A to 30D is applied to an MT-CMOS device as it is, in order to form a channel region in the first nMOSFET, the second nMOSFET, the first pMOSFET, and the second pMOSFET, It is easily understood that it is necessary to form four types of resist films having openings only in the MOSFET formation regions Rn1, Rn2, Rp1, and Rp2. Therefore, in the method for manufacturing the semiconductor device according to the present embodiment, two photomask forming steps can be reduced as compared with the conventional method, and the steps can be simplified.

(Fourth embodiment)
Next, an MT-CMOS device manufacturing process according to the fourth embodiment will be described with reference to FIGS.

  Also in this embodiment, the same processes as those in FIGS. 7A and 7B described in the third embodiment are performed until the middle of the manufacturing process. About this process, illustration and description are abbreviate | omitted.

8A, a resist film 16f that covers the pMOSFET formation region Rp is formed, and boron ions (B +) 20 are added to the nMOSFET formation region Rn using the resist film 16f and the gate electrode 8 as a mask. Implantation is performed under the conditions of −30 KeV and 5-10 × 10 ¹² cm ⁻² to form the pocket region 9 of each nMOSFET.

Next, in the step shown in FIG. 8 (b), each region of each gate electrode 8 as a mask Rn1, Rn2, Rp2, Rp1 phosphorus ions (P +) the 30-40KeV, 0.5-2 × 10 ¹³ cm ^The implantation is performed under the condition ^-2 , and the LDD region 11 is formed in the first and second nMOSFET formation regions Rn1 and Rn2, and the pocket region 10 is simultaneously formed in the first and second pMOSFET formation regions Rp1 and Rp2.

  Next, in the step shown in FIG. 8C, the same step as the step shown in FIG. 7D in the third embodiment is performed, and the sidewall 13 on the side surface of the gate electrode 8 and the first, A source / drain region 14 of the second nMOSFET and a source / drain region 15 of the first and second pMOSFETs are formed. However, the conditions for forming the source / drain regions are the same as in the third embodiment.

  In the MT-CMOS device formed in the above process, the inversion voltage of the first nMOSFET is determined by the impurity concentration of the channel region 4 and the pocket region 9, and the inversion voltage of the second nMOSFET is determined between the p-type well 2a and the pocket region 9. The inversion voltage of the first pMOSFET is determined by the impurity concentration of the channel region 6 and the pocket region 10, and the inversion voltage of the second pMOSFET is determined by the impurity concentration of the n-type well 2b and the pocket region 10. That is, an MT-CMOS device composed of an MT-nMOS device and an MT-pMOS device on which two MOSFETs having different inversion voltages are mounted.

  The manufacturing process of this embodiment is the same as that of the third embodiment in that only two photomasks for inversion voltage control are required. In addition, in the manufacturing process of this embodiment, the LDD region 11 of the nMOSFET and the pocket region 10 of the pMOSFET are simultaneously formed in a self-aligned manner, so that a photomask (resist film) covering the other region becomes unnecessary, and Compared with the process shown in FIG. 7C in the third embodiment, two more photomasks can be omitted, and the process can be simplified.

  In the MT-CMOS device according to the present embodiment, the first and second pMOSFETs have a single drain structure instead of an LDD structure. Usually, a pMOSFET has a lower electric field strength near the drain than an nMOSFET, and a hot carrier generation probability. Therefore, there is no possibility that the reliability is lowered. Also in the MT-CMOS device according to the present embodiment, both the nMOSFET and the pMOSFET include the first and second nMOSFETs having the different inversion voltages and the first and second pMOSFETs. The same effect as the form can be exhibited.

(Fifth embodiment)
Next, an MT-CMOS device according to the fifth embodiment will be described with reference to FIGS.

  Also in this embodiment, the same processes as those in FIGS. 7A and 7B described in the third embodiment are performed until the middle of the manufacturing process. About this process, illustration and description are abbreviate | omitted.

9A, a resist film 16g that covers the nMOSFET formation region Rn is formed, and phosphorus ions (P +) 80 are added to the pMOSFET formation region Rp using the resist film 16g and the gate electrode 8 as a mask. Implantation is performed under the conditions of −120 KeV, 5-10 × 10 ¹² cm ⁻² to form the pocket region 10 of each pMOSFET.

Next, in the step shown in FIG. 9B, boron ions (B +) are 10-20 KeV, 2-8 × 10 ¹³ cm ^{-2 in} each region Rn1, Rn2, Rp2, Rp1 using each gate electrode 8 as a mask. Then, the LDD region 12 is formed in the first and first pMOSFET formation regions Rp1 and Rp2, and the pocket region 9 is simultaneously formed in the first and second nMOSFET formation regions Rn1 and Rn2.

  Next, in the step shown in FIG. 9C, the same process as the step shown in FIG. 7D in the third embodiment is performed, and the side wall 13 on the side surface of the gate electrode 8 and the first, A source / drain region 14 of the second nMOSFET and a source / drain region 15 of the first and second pMOSFETs are formed. However, the conditions such as ion implantation at the time of forming the source / drain regions are the same as those in the third embodiment.

  In the MT-CMOS device formed by the above process, the inversion voltage of the first nMOSFET is determined by the impurity concentration of the channel region 4 and the pocket region 9, and the inversion voltage of the second nMOSFET is determined between the p-type well 2 a and the pocket region 9. The inversion voltage of the first pMOSFET is determined by the impurity concentration of the channel region 6 and the pocket region 10, and the inversion voltage of the second pMOSFET is determined by the impurity concentration of the n-type well 2b and the pocket region 10. That is, an MT-CMOS device composed of an MT-nMOS device and an MT-pMOS device on which two MOSFETs having different inversion voltages are mounted.

  The manufacturing process of this embodiment is the same as that of the third embodiment in that only two photomasks for inversion voltage control are required. In addition, in the manufacturing process of the present embodiment, the LDD region 12 of the pMOSFET and the pocket region 9 of the nMOSFET are simultaneously formed in a self-aligned manner, so that a photomask (resist film) covering the other region becomes unnecessary, and Compared with the process shown in FIG. 7C in the third embodiment, two more photomasks can be omitted, and the process can be simplified.

  In the MT-CMOS device according to the present embodiment, the first and second nMOSFETs have a single drain structure instead of an LDD structure, but use phosphorus ions as impurity ions for forming the source / drain regions 14. Compared with the case where arsenic ions are used, the electric field strength in the vicinity of the drain is low and the probability of occurrence of hot carriers is low, so there is no possibility that the reliability will deteriorate. In the MT-CMOS device according to the present embodiment, both the nMOSFET and the pMOSFET include the first and second nMOSFETs having different inversion voltages and the first and second pMOSFETs having different inversion voltages. The same effects as those of the third embodiment can be exhibited.

  Depending on the minimum gate length and power supply voltage, a single drain structure using arsenic may be adopted.

(Sixth embodiment)
Next, an MT-nMOS device according to the sixth embodiment will be described with reference to FIGS.

  In the present embodiment, the same steps as those in FIG. 3A described in the first embodiment are performed up to the step shown in FIG. About this process, illustration and description are abbreviate | omitted.

10A, a silicon oxide film having a thickness of 8-12 nm is deposited on the entire surface of the semiconductor substrate 1, and a polysilicon film having a thickness of 250-300 nm is further deposited thereon. The gate electrode 8 and the gate insulating film 7 are patterned by the photolithography process and the etching process. Next, after forming the sidewall 13 on the side surface of the gate electrode 8, arsenic ions (As +) are implanted under the conditions of 40 KeV, 4-6 × 10 ¹⁴ cm ^{−2 using} the gate electrode 8 and the sidewall 13 as a mask. , N + -type source / drain regions 14 are formed. Further, after depositing a titanium film with a thickness of about 50 nm, a heat treatment is performed to react titanium with silicon constituting the source / drain region 14 and the gate electrode 8, and to form a contact between the gate electrode 8 and the source / drain region 14. Titanium silicide films 17a and 17b having a thickness of about 100 nm are formed on the surface, respectively. Thereafter, the sidewall 13 is removed by selective etching.

Next, in the step shown in FIG. 10 (b), the titanium silicide films 17a, and 17b as a mask, implanted BF2 ions (BF2 +) 100-150KeV, under conditions of 2-8 × 10 ¹² cm ^-2, the A p-type pocket region 9 is formed below the region where the sidewall 13 of the pMOSFET has been removed.

Next, in the step shown in FIG. 10C, phosphorus ions (P +) are implanted under the conditions of 30-40 KeV, 2-8 × 10 ¹³ cm ^{-2 using} the titanium silicide films 17a, 17b as masks. An n − type LDD region 11 surrounded by the pocket region 9 is formed.

  In the above manufacturing process, similarly to the first embodiment, only one photomask is required for controlling the inversion voltage of each nMOSFET in the MT-nMOS device, and the process is simplified compared to the conventional method. Can be

  Further, in the MT-nMOSFET formed in the manufacturing process of this embodiment, the inversion voltage of the first nMOSFET is determined by the p-type impurity concentration of the channel region 4 and the pocket region 9, and the inversion voltage of the second nMOSFET is the substrate region 1a and the pocket. It is determined by the p-type impurity concentration in region 9. Therefore, as described in the first embodiment, the effect that the subthreshold characteristic is good and the leakage current can be reduced can be exhibited. This effect is more remarkable in the second nMOSFET. Moreover, punch-through and short channel effects can be suppressed by the pocket region 9.

  Furthermore, in this embodiment, the pocket region 9 is formed by ion implantation using the titanium silicide films 17a and 17b on the gate electrode 8 and the source / drain regions 14 as a mask, so that the pocket region 9 is formed extremely locally. . That is, in the structure shown in FIG. 10C, the pocket region 9 does not extend below the source / drain region 14 as compared with the structure shown in FIG. 1 in the first embodiment. Therefore, a pn junction is formed between the source / drain region 14 and the substrate region 1a, and a pn junction is formed between the source / drain region 14 and the pocket region 9. As compared with the above, since the impurity concentration in the p-side region of the pn junction can be reduced, the parasitic capacitance can be reduced. Normally, since the MT-MOS device is operated with a low power supply voltage of 1.0 to 2.0 V, it has the disadvantage that the depletion layer of the pn junction is small and the parasitic capacitance is large. Since the parasitic capacitance can be reduced as described above, the effect is extremely great, and an LSI that operates at high speed and consumes very little power can be realized.

(Deformation regarding the first to sixth embodiments)
The structure of the MT-nMOS device described in the first and second embodiments can be similarly applied to the MT-pMOS device and can exhibit the same effect.

  Also, the first and second nMOSFETs having the structure of the second embodiment, and the first and second pMOSFETs having the structure in which only the impurity conductivity type of the first and second nMOSFETs is reversed are provided, and the MT-CMOS is provided. A device may be configured.

  Furthermore, in the sixth embodiment, the MT-nMOS device in which the substrate region 1a functions as a channel region in the second nMOSFET as shown in FIG. 1 of the first embodiment has been described. In the sixth embodiment, A channel region having an impurity concentration lower than the impurity concentration in the channel region 4 of the first nMOSFET may be provided in the second nMOSFET.

(Seventh embodiment)
Hereinafter, the seventh embodiment will be described with reference to FIGS. 11, 12, and 13A to 13D.

  FIG. 11 is a cross-sectional view of an MT-nMOS device according to the seventh embodiment. As shown in FIG. 11, a region near the surface of the semiconductor substrate 1 made of a silicon single crystal doped with a p-type impurity is partitioned into a large number of active regions by element isolation 3 made of a silicon oxide film. Each active region is provided with a first nMOSFET formation region Rn1 for forming a high inversion voltage type first nMOSFET and a second nMOSFET formation region Rn2 for forming a low inversion voltage type second nMOSFET. In the first and second nMOSFET forming regions Rn1, Rn2, each of the gate insulating film 7 made of a silicon oxide film, the gate electrode 8 made of a polysilicon film provided on the gate insulating film 7, and each of the gate electrodes 8 A sidewall 13 made of a silicon oxide film formed on the side surface is provided. In both the first nMOSFET formation region Rn1 and the second nMOSFET formation region Rn2, the substrate region 1a immediately below the gate insulating film 7 functions as a channel region.

  In each of the nMOSFET formation regions Rn1 and Rn2, n + type source / drain regions 14 that are formed in regions located on both sides of the gate electrode 8 in the semiconductor substrate 1 and contain high-concentration n-type impurities, and a channel region N-type LDD region 11 including a low-concentration n-type impurity formed between each source / drain region 14 and p-type impurities formed so as to surround LDD region 11 and source / drain region 14. P-type pocket regions 9a and 9b serving as punch-through stoppers are provided.

  12 (a) and 12 (b) show effective impurity concentration distributions, that is, carrier concentration distributions excluding the amount offset by two types of impurities of opposite conductivity types in the first and second nMOSFETs. Show. In the present embodiment, the solid line indicates the concentration distribution of the n-type carrier that is the first conductivity type carrier, and the broken line indicates the concentration distribution of the p-type carrier that is the second conductivity type carrier. 12A and 12B, the channel direction of each nMOSFET is on the horizontal axis. As can be seen from FIGS. 12A and 12B, when the nMOSFETs are compared, the n-type carrier concentrations in the LDD region 11 and the source / drain regions 14 are the same. However, the p-type carrier concentration p1 in the pocket region 9a of the first nMOSFET is higher than the p-type carrier concentration p2 in the pocket region 9b of the second nMOSFET. As a result, the inversion voltage (threshold voltage) of the first nMOSFET is higher than the inversion voltage of the second nMOSFET. Therefore, an MT-MOS device having a high operating speed and low power consumption can be obtained, similar to a conventional MT-MOS device equipped with a MOSFET having two types of inversion voltages.

  In addition, in this embodiment, in order to mount two types of nMOSFETs having different inversion voltages on the same semiconductor substrate 1, the following advantages can be obtained by controlling the impurity concentration in the pocket regions 9a and 9b. That is, a transistor in which a pocket region is provided between a source / drain region (LDD region 11 in this embodiment) and a channel region can suppress punch-through and short channel effects. For this reason, the structure is advantageous for miniaturization as compared with a conventional semiconductor device in which impurity ions for threshold control are implanted at two different concentrations into the channel region of each MOSFET. Further, since the pocket region 9a or 9b is formed in any nMOSFET, punch-through and the short channel effect can be sufficiently suppressed even if the impurity concentration of the substrate region 1a functioning as the channel region is lowered. Thus, since the impurity concentration in the channel region can be made lower than that of a normal MOSFET, the gate depletion layer capacitance is reduced, the subthreshold characteristics are good, and the leakage current is small.

  In particular, in the present embodiment, unlike the first embodiment, both the first and second nMOSFETs use the substrate region 1a as a channel region as it is without implanting threshold control impurities into the channel region. As a result, the impurity concentration of the channel region becomes extremely low, and the above-described effects can be exhibited remarkably.

  Next, the manufacturing process of the MT-nMOS device according to this embodiment will be described with reference to FIGS.

First, in the step shown in FIG. 13A, a silicon oxide film having a thickness of about 400 nm is formed on a semiconductor substrate 1 composed of a silicon single crystal doped with a p-type impurity by using a LOCOS method, a trench isolation method or the like. The element isolation 3 is formed, and the first nMOSFET formation region Rn1 and the second nMOSFET formation region Rn2 are partitioned by the element isolation 3. Then, a silicon oxide film having a thickness of 8-12 nm is deposited on the entire surface of the substrate, and a polysilicon film having a thickness of 250-300 nm is further deposited thereon, and the gate electrode 8 is formed by a normal photolithography process and etching process. Then, the gate insulating film 7 is formed. Further, using this gate electrode 8 as a mask, phosphorus ions (P +) are implanted under the conditions of 30-40 KeV, 2-8 × 10 ¹³ cm ⁻² to form the LDD region 11.

Next, in the step shown in FIG. 13B, using the gate electrode 8 as a mask, boron ions (B +) are 20-30 KeV, 5-10 × 10 ¹² cm ^{−2 in} the nMOSFET formation regions Rn1, Rn2. To form p-type pocket regions 9a and 9b in the nMOSFET formation regions Rn1 and Rn2.

Next, in the step shown in FIG. 13C, after forming a resist film 16h covering the second nMOSFET formation region Pn2 and opening the first nMOSFET formation region Rn1, the resist film 16h and the gate electrode 8 are used as a mask. Then, boron ions (B +) are implanted into the first nMOSFET formation region Rn1 under the conditions of 20-30 KeV and 2-5 × 10 ¹² cm ⁻² , and only the impurity concentration of the pocket region 9a of the first nMOSFET, that is, the carrier concentration, is increased. To do.

Next, in the step shown in FIG. 13D, sidewalls 13 are formed on each side surface of the gate electrode 8, and arsenic ions are 40 KeV, 4-6 × 10 ¹⁴ using the gate electrode 8 and the sidewalls 13 as a mask. The source / drain region 14 is formed by implanting under the condition of cm ⁻² .

  It can be seen that the MT-nMOS device having the structure shown in FIG. In particular, in the manufacturing steps shown in FIGS. 13A to 13D, impurity ions for controlling the inversion voltage of the nMOSFET can be implanted with only one resist film 16h serving as a photomask. Therefore, the process is simplified as compared with the conventional method that requires two photomasks (resist films 16a and 16b shown in FIGS. 30A and 30B) for impurity ion implantation for controlling the inversion voltage. There is an advantage that the manufacturing cost can be reduced.

(Eighth embodiment)
Next, an MT-nMOS device according to the eighth embodiment will be described with reference to FIG.

  As shown in FIG. 14, also in the present embodiment, as in the MT-nMOS device according to the seventh embodiment, the region near the surface of the semiconductor substrate 1 doped with the p-type impurity is separated by the element isolation 3. The first nMOSFET formation region Rn1 and the second nMOSFET formation region Rn2 are partitioned. The structures of the first nMOSFET formed in the first nMOSFET formation region Rn1 and the second nMOSFET formed in the second nMOSFET formation region Rn2 are basically the same as the structure of each nMOSFET in the seventh embodiment. The gate insulating film 7, the gate electrode 8, the sidewall 13, the source / drain region 14, the LDD region 11, and the pocket regions 9a and 9b are provided.

  Here, as a feature of the present embodiment, the width Wp1 of the pocket region 9a of the first nMOSFET is larger than the width Wp2 of the pocket region of the second nMOSFET. However, the impurity concentrations in the pocket regions 9a and 9b are the same. Such a structure is obtained when, for example, the first conductivity type impurity (boron) is implanted again into the pocket region 9a of the first nMOSFET in the process shown in FIG. 13C in the manufacturing process of the first embodiment. This can be realized by performing ion implantation from a direction that is largely inclined toward the side facing the gate electrode 8 with respect to the direction perpendicular to the main surface of the semiconductor substrate 1. Alternatively, ion implantation for forming the pocket regions 9a and 9b of each nMOSFET may be performed while changing the tilt angle.

  In this embodiment, since the width Wp1 of the pocket region 9a of the first nMOSFET is wider than the width Wp2 of the pocket region 9b of the second nMOSFET, the inversion voltage of the first nMOSFET is higher than the inversion voltage of the second nMOSFET. As described above, since the nMOSFETs having two types of inversion voltages can be formed on the same semiconductor substrate only by changing the width of the pocket region, the configuration shown in FIG. 14 can be realized by a simple process. The same effect as that of the manufacturing method of the form can be exhibited.

(Ninth embodiment)
Next, an MT-CMOS device according to a ninth embodiment will be described with reference to FIGS. 15 and 16 (a)-(f).

  As shown in FIG. 15, in this embodiment, a p-type well 2a containing a p-type impurity and an n-type well 2b containing an n-type impurity are formed in a semiconductor substrate. An nMOSFET formation region Rn and a pMOSFET formation region Rp exist in the semiconductor substrate. Furthermore, due to the element isolation 3, the nMOSFET formation region Rn is partitioned into a first nMOSFET formation region Rn1 and a second nMOSFET formation region Rn2, and the pMOSFET formation region Rp is partitioned into a first pMOSFET formation region Rp1 and a second pMOSFET formation region Rp2. . The structures of the first and second nMOSFETs formed in the first and second nMOSFET formation regions Rn1 and Rn2 are the same as the structure shown in FIG. 11 in the seventh embodiment. In addition, the structure of the first and second pMOSFETs is merely the reverse of the conductivity type of the impurity in the structure of the first and second nMOSFETs shown in FIG. That is, the first and second pMOSFETs include the gate electrode 8, the gate insulating film 7, the sidewall 13, the p + type source / drain region 15, the p− type LDD region 12, and the n type pocket, respectively. Regions 10a and 10b.

  The same effects as those of the seventh embodiment can be obtained by the structure of the MT-nMOS device among the MT-CMOS devices according to the present embodiment. Also in the structure of the MT-pMOS device, the concentration of n-type impurities (concentration of n-type carriers) in the pocket region 10a of the first pMOSFET is set to be higher than the concentration of n-type impurities in the pocket region 10b of the second pMOSFET. Thus, the inversion voltage of the first pMOSFET is set higher than the inversion voltage of the second pMOSFET. Therefore, as in the seventh embodiment, the subthreshold characteristic is improved and the leakage current can be reduced. Since most semiconductor devices actually used have a CMOS device structure, the MT-CMOS device according to the present embodiment is extremely useful.

  Next, the manufacturing process of the MT-CMOS device according to this embodiment will be described with reference to FIGS.

First, in the step shown in FIG. 16A, a p-type well 2a and an n-type well 2b are formed on a semiconductor substrate 1 made of single crystal silicon, and then a silicon oxide film having a thickness of about 400 nm is formed. The element isolation 3 is formed, and the first nMOSFET formation region Rn1, the second nMOSFET formation region Rn2, the second pMOSFET formation region Rp2, and the first pMOSFET formation region Rp1 are partitioned. Then, a silicon oxide film having a thickness of 8-12 nm is formed on the semiconductor substrate 1, and a polysilicon film having a thickness of 250-300 nm is further deposited thereon, and the gate insulating film 7 is formed by a normal lithography process and etching process. And the gate electrode 8 is formed. Then, a resist film 16i having an opening only on the nMOSFET formation region Rn is formed by a normal photolithography process, and phosphorus ions are formed in the first and second nMOSFET formation regions Rn1 and Rn2 using the resist film 16i and the gate electrode 8 as a mask. (P +) is implanted under the conditions of 30-40 KeV, 2-8 × 10 ¹³ cm ⁻² to form the LDD region 11 of each nMOSFET. Next, using the same resist film 16i and gate electrode 8 as a mask, boron ions (B +) are applied to the first and second nMOSFET formation regions Rn1 and Rn2 under conditions of 20-30 KeV and 2-5 × 10 ¹² cm ⁻² . Implantation is performed to form p-type pocket regions 9a and 9b.

Next, in the step shown in FIG. 16B, a resist film 16j opened only on the first nMOSFET formation region Rn1 is formed, and boron ions (B) are formed in the first nMOSFET formation region Rn1 using the resist film 16j as a mask. +) Is implanted under the conditions of 20-30 KeV, 2-5 × 10 ¹² cm ⁻² to increase only the impurity concentration of the pocket region 9a of the first nMOSFET.

Next, in the step shown in FIG. 16C, after a resist film 16k having an opening only on the pMOSFET formation region Rp is formed, boron ions (in the pMOSFET formation region Rp are masked using the resist film 16k and the gate electrode 8 as a mask. B +) is implanted under the conditions of 30-40 KeV, 2-8 × 10 ¹³ cm ⁻² to form the LDD region 12 of each pMOSFET. Further, using the same resist film 16k and gate electrode 8 as a mask, phosphorus ions (P +) are implanted into the pMOSFET formation region Rp under the conditions of 80-120 KeV, 5-10 × 10 ¹² cm ⁻² . Pocket regions 10a and 10b are formed.

Next, in the step shown in FIG. 16D, a resist film 16l having an opening only on the first pMOSFET formation region Rp1 is formed, and the resist film 161 and the gate electrode 8 are used as a mask in the first pMOSFET formation region Rp1. Phosphorus ions (P +) are implanted under the conditions of 80-120 KeV, 2-5 × 10 ¹² cm ⁻² to increase the impurity concentration only in the pocket region 10a of the first pMOSFET.

Next, in the step shown in FIG. 16 (e), a sidewall 13 is formed on each side surface of the gate electrode 8 of each MOSFET, and then a resist film 16m having an opening above the nMOSFET formation region Rn is formed. Arsenic ions (As +) are implanted into the nMOSFET formation region Rn under the conditions of 40 KeV and 4-6 × 10 ¹⁴ cm ^{−2 using} the film 16m, the gate electrode 8 and the sidewalls 13 as a mask, and the source / drain regions 14 of the nMOSFET. Form.

Next, in the step shown in FIG. 16F, a resist film 16n having an opening above the pMOSFET formation region Rp is formed, and then the pMOSFET formation region Rp with the resist film 16n, the gate electrode 8 and the sidewalls 13 as masks. Then, boron ions (B +) are implanted under the conditions of 10-20 KeV, 4-6 × 10 ¹⁴ cm ⁻² to form source / drain regions 15 of each pMOSFET.

  Through the above steps, the MT-CMOS device having the structure shown in FIG. 15 is easily formed.

  In the manufacturing process of the MT-CMOS device of this embodiment, since only two resist films for controlling the inversion voltage are required (resist films 16j and 16l), the process can be simplified as compared with the conventional method.

(Tenth embodiment)
Next, a tenth embodiment will be described with reference to FIGS. FIGS. 17A to 17D are cross-sectional views showing a manufacturing process of an MT-pMOS device having two types of inversion voltages.

First, in the step shown in FIG. 17A, a silicon oxide film having a thickness of about 400 nm is formed on the n-type well 2b in the semiconductor substrate 1 made of silicon single crystal by using the LOCOS method, the trench isolation method or the like. The element isolation 3 is formed, and the first pMOSFET formation region Rp1 and the second pMOSFET formation region Rp2 are partitioned by the element isolation 3. Then, a silicon oxide film having a thickness of 8-12 nm is deposited on the entire surface of the substrate, and a polysilicon film having a thickness of 250-300 nm is further deposited thereon, and the gate electrode 8 is formed by a normal photolithography process and etching process. Then, the gate insulating film 7 is formed. Thereafter, BF2 ions (BF2 +) are implanted under the conditions of 30-40 KeV, 2-8 × 10 ¹³ cm ^{-2 using} the gate electrode 8 as a mask, and the p-type LDD layer 12 of each pMOSFET is formed.

Next, in the step shown in FIG. 17B, phosphorus ions (P +) are implanted into the pMOSFET formation region Rp using the gate electrode 8 as a mask under the conditions of 80-120 KeV, 5-10 × 10 ¹² cm ⁻² . N-type pocket regions 10a and 10b of each pMOSFET are formed.

Next, although illustration is omitted, after forming the sidewall 13 on each side surface of the gate electrode 8 of each pMOSFET, boron ions are implanted at a high concentration using the gate electrode and the sidewall 13 as a mask to form each pMOSMOSFET formation region. A p + type source / drain region 15 is formed in Rp1 and Rp2. Thereafter, a resist film 16o having an opening only on the first pMOSFET formation region Rp1 is formed in the step shown in FIG. 17C, and the first pMOSFET formation region Rp1 is formed using the resist film 16o, the gate electrode 8 and the sidewall 13 as a mask. Nitrogen ions (N +) are implanted into the inside under the conditions of 10-20 KeV, 4-6 × 10 ¹⁴ cm ⁻² .

  Next, in the step shown in FIG. 17D, the semiconductor substrate 1 is subjected to a heat treatment at 850 ° C. for 30 minutes to form the gates of the first and second pMOSFETs when the p + -type source / drain regions 15 are formed. High concentration boron ions introduced into the electrode 8 are diffused into the semiconductor substrate 1. At this time, since nitrogen is introduced into the gate electrode 8 of the first pMOSFET, diffusion of boron into the pocket region 10a is prevented or suppressed by an action such as formation of an oxynitride film in the gate insulating film 7. Is done. On the other hand, since nitrogen is not introduced into the gate electrode 8 of the second pMOSFET, boron in the gate electrode 8 diffuses to the pocket region 10b. As a result, the pocket region 10b of the second pMOSFET is more diffused than the pocket region 10a of the first pMOSFET. However, since the effective concentration of n-type impurities, that is, the concentration of n-type carriers, is lower, the inversion voltage of the second pMOSFET is smaller than that of the first pMOSFET.

  Through the above steps, an MT-pMOS device composed of pMOSFETs having two types of inversion voltages is formed.

  As in the seventh to ninth embodiments, the MT-pMOS device according to the present embodiment can suppress punch-through and the short channel effect, and has a structure advantageous for miniaturization. In addition, the gate depletion layer capacitance is small, the subthreshold characteristic is good, and the leakage current is small.

  The manufacturing method of this embodiment has an advantage that the process can be simplified as compared with the conventional method because only one resist film for controlling the inversion voltage is required (resist film 16o).

(Eleventh embodiment)
Next, an eleventh embodiment will be described with reference to FIGS. 18 (a) to 18 (d) are cross-sectional views showing a manufacturing process of an MT-pMOS device having two types of inversion voltages.

First, in the step shown in FIG. 18A, a silicon oxide film having a thickness of about 400 nm is formed on the n-type well 2b in the semiconductor substrate 1 made of silicon single crystal by using the LOCOS method, the trench isolation method, or the like. The element isolation 3 is formed, and the first pMOSFET formation region Rp1 and the second pMOSFET formation region Rp2 are partitioned by the element isolation 3. Then, a silicon oxide film having a thickness of 8-12 nm is deposited on the entire surface of the substrate, and a polysilicon film having a thickness of 250-300 nm is further deposited thereon, and the gate electrode 8 is formed by a normal photolithography process and etching process. Then, the gate insulating film 7 is formed. Thereafter, boron ions (B +) are implanted under the conditions of 30-40 KeV, 2-8 × 10 ¹³ cm ^{−2 using} the gate electrode 8 as a mask, and the p-type LDD layer 12 of each pMOSFET is formed.

Next, in the step shown in FIG. 18B, phosphorus ions (P +) are implanted into the pMOSFET formation region Rp using the gate electrode 8 as a mask under the conditions of 80-120 KeV, 5-10 × 10 ¹² cm ⁻² . N-type pocket regions 10a and 10b are formed in each pMOSFET.

Next, although illustration is omitted, after sidewalls 13 are formed on each side surface of the gate electrode 8 of each pMOSFET, boron ions are implanted at a high concentration using the gate electrode 8 and the sidewall 13 as a mask to form each pMOSMOSFET. A p + type source / drain region 15 is formed in the regions Rp1 and Rp2. 18C, a resist film 16p having an opening above the second pMOSFET formation region Rp2 is formed, and the second pMOSFET formation region Rp2 is formed using the resist film 16p, the gate electrode 8 and the sidewall 13 as a mask. Fluorine ions (F +) are implanted into the inside under the conditions of 10-20 KeV, 4-6 × 10 ¹⁴ cm ⁻² .

  Next, in the step shown in FIG. 18D, the semiconductor substrate 1 is heat-treated at 850 ° C. for 30 minutes to diffuse boron ions in each pMOSFET into the semiconductor substrate 1. At this time, since fluorine is introduced into the gate electrode 8 of the second pMOSFET formation region Rp2, diffusion of boron into the pocket region 10b is promoted. On the other hand, since fluorine is not introduced into the gate electrode 8 of the first pMOSFET, boron in the gate electrode 8 diffuses to the pocket region 10a, but the diffusion amount is smaller than the diffusion amount to the pocket region 10b of the second pMOSFET. . As a result, since the effective concentration of the n-type impurity, that is, the concentration of n-type carriers, is lower in the pocket region 10b of the second pMOSFET than in the pocket region 10a of the first pMOSFET, the inversion voltage of the second pMOSFET is smaller than that of the first pMOSFET. .

  Through the above steps, an MT-pMOS device composed of pMOSFETs having two types of inversion voltages is formed.

  As in the above embodiments, the MT-pMOS device according to this embodiment can suppress punch-through and the short channel effect, and has a structure advantageous for miniaturization. In addition, the gate depletion layer capacitance is small, the subthreshold characteristic is good, and the leakage current is small.

  The manufacturing method of this embodiment has an advantage that the process can be simplified as compared with the conventional method because only one resist film for controlling the inversion voltage is required (resist film 16p).

(Twelfth embodiment)
Next, a twelfth embodiment will be described with reference to FIGS. FIGS. 19A to 19D are cross-sectional views showing a manufacturing process of an MT-pMOS device having two types of inversion voltages.

First, in the step shown in FIG. 19A, a silicon oxide film having a thickness of about 400 nm is formed on the n-type well 2b in the semiconductor substrate 1 made of silicon single crystal by using the LOCOS method, the trench isolation method, or the like. The element isolation 3 is formed, and the first pMOSFET formation region Rp1 and the second pMOSFET formation region Rp2 are partitioned by the element isolation 3. Then, a silicon oxide film having a thickness of 8-12 nm is deposited on the entire surface of the substrate, and a polysilicon film having a thickness of 250-300 nm is further deposited thereon, and the gate electrode 8 is formed by a normal photolithography process and etching process. Then, the gate insulating film 7 is patterned. Thereafter, boron ions (B +) are implanted under the conditions of 30-40 KeV, 2-8 × 10 ¹³ cm ^{−2 using} the gate electrode 8 as a mask, and the p-type LDD layer 12 of each pMOSFET is formed.

Next, in the step shown in FIG. 19B, phosphorus ions (P +) are implanted into the pMOSFET formation region Rp using the gate electrode 8 as a mask under the conditions of 80-120 KeV, 5-10 × 10 ¹² cm ⁻² . N-type pocket regions 10a and 10b are formed in each pMOSFET.

Next, although illustration is omitted, after forming the sidewall 13 on each side surface of the gate electrode 8 of each pMOSFET, boron ions are implanted at a high concentration using the gate electrode 8 and the sidewall 13 as a mask to form each pMOSFET. A p + type source / drain region 15 is formed in the regions Rp1 and Rp2. 19C, a resist film 16q having an opening above the second pMOSFET formation region Rp2 is formed, and the second pMOSFET formation region Rp2 is formed using the resist film 16q, the gate electrode 8 and the sidewall 13 as a mask. Boron ions (B +) are implanted into the inside under conditions of 10-20 KeV, 4-6 × 10 ¹⁴ cm ⁻² .

  Next, in the step shown in FIG. 19D, the semiconductor substrate 1 is heat treated at 850 ° C. for 30 minutes to diffuse boron ions in each pMOSFET into the semiconductor substrate 1. At this time, since boron is introduced again into the gate electrode 8 of the second pMOSFET formation region Rp2, the concentration of boron is high. Therefore, the diffusion amount of boron into the pocket region 10b of the second pMOSFET is larger than the diffusion amount into the pocket region 10a of the first pMOSFET. Due to the difference in the counter-doping amount due to boron, the effective concentration of n-type impurities, that is, the concentration of n-type carriers is lower in the n-type pocket region 10b of the second pMOSFET than in the n-type pocket region 10a of the first pMOSFET. The inversion voltage of the second pMOSFET is smaller than that of the 1pMOSFET.

  Through the above steps, an MT-pMOS device composed of pMOSFETs having two types of inversion voltages is formed.

  As in the above embodiments, the MT-pMOS device according to this embodiment can suppress punch-through and the short channel effect, and has a structure advantageous for miniaturization. In addition, the gate depletion layer capacitance is small, the subthreshold characteristic is good, and the leakage current is small.

  The manufacturing method according to the present embodiment has an advantage that the process can be simplified as compared with the conventional method because only one resist film for controlling the inversion voltage is required (resist film 16q).

(13th Embodiment)
Next, an MT-nMOS device according to the thirteenth embodiment will be described with reference to FIGS.

  In the present embodiment, steps similar to those in FIG. 13A described in the seventh embodiment are performed up to the step shown in FIG. About this process, illustration and description are abbreviate | omitted.

Then, in the step shown in FIG. 20A, a silicon oxide film having a thickness of 8-12 nm is deposited on the entire surface of the substrate in each of the nMOSFET formation regions Rn1, Rn2, and a polycrystal having a thickness of 250-300 nm is further formed thereon. A silicon film is deposited, and a gate electrode 8 and a gate insulating film 7 are formed by a normal photolithography process and etching process. Next, after forming the side wall 13 on the side surface of the gate electrode 8, arsenic ions (As +) are used under the conditions of 40 KeV and 4-6 × 10 ¹⁴ cm ^{−2 using} the gate electrode 8 and the side wall 13 as a mask. Implantation is performed to form n + -type source / drain regions 14. Further, after depositing a titanium film with a thickness of about 50 nm, titanium is reacted with silicon constituting the source / drain regions 14 and the gate electrode 8 by heat treatment to form on the surfaces of the gate electrode 8 and the source / drain regions 14. Titanium silicide films 17a and 17b having a thickness of about 100 nm are formed. Thereafter, the sidewall 13 is removed by selective etching.

Next, in the step shown in FIG. 20B, phosphorus ions (P +) are implanted under the conditions of 30-40 KeV, 2-8 × 10 ¹³ cm ^{-2 using} the titanium silicide films 17a, 17b as masks. An n − type LDD region 11 is formed below the region where the sidewall 13 of each nMOSFET has been removed.

Next, in the step shown in FIG. 20 (c), BF2 ions (BF2 +) are implanted under the conditions of 100-150 KeV, 1-5 × 10 ¹² cm ^{-2 using} the titanium silicide films 17a, 17b as masks. P-type pocket regions 9a and 9b are formed at the back of the LDD region 11 of the nMOSFET.

Next, in the step shown in FIG. 20 (d), a resist film 16r having an opening above the first nMOSFET formation region Rn1 is formed, and BF2 ions (BF2 +) are 100-- using the resist film 16r and the gate electrode 8 as a mask. Implantation is performed under the conditions of 150 KeV and 1-5 × 10 ¹² cm ⁻² to increase only the impurity concentration of the pocket region 9a of the first nMOSFET. As a result, the inversion voltage of the first nMOSFET becomes higher than the inversion voltage of the second nMOSFET.

  In the manufacturing process of this embodiment, as in the seventh embodiment, only one photomask is necessary for controlling the inversion voltage of each nMOSFET in the MT-nMOS device, which is a process compared to the conventional method. Can be simplified.

  Further, in the MT-nMOSFET formed in the manufacturing process of the present embodiment, the inversion voltages of the first nMOSFET and the second nMOSFET are different because the impurity concentrations of the pocket regions 9a and 9b of the first and second nMOSFETs are different. Therefore, similarly to the first embodiment, while mounting two MOSFETs having different inversion voltages, punch-through and short channel effects can be suppressed by the pocket regions 9a and 9b of each nMOSFET. Further, similarly to the first embodiment, since the depletion layer capacitance of each nMOSFET is small, the effect that the subthreshold characteristic is good and the leakage current can be reduced can be exhibited.

  Furthermore, in the manufacturing process of this embodiment, the pocket regions 9a and 9b are formed by ion implantation using the titanium silicide films 17a and 17b on the gate electrode 8 and the source / drain regions 14 as masks. Formed very locally. That is, in the structure shown in FIG. 20D, the pocket regions 9a and 9b do not extend below the source / drain regions 14 as compared with the structure shown in FIG. 11 in the seventh embodiment. Therefore, a pn junction is formed between the source / drain region 14 and the substrate region 1a, and a pn junction is formed between the source / drain region 14 and the pocket regions 9a and 9b. Compared to the embodiment and the like, since the impurity concentration in the p-side region of the pn junction can be reduced, the parasitic capacitance is not increased. Normally, since the MT-MOS device is operated with a low power supply voltage of 1.0 to 2.0 V, it has the disadvantage that the depletion layer of the pn junction is small and the parasitic capacitance is large. Since the parasitic capacitance can be reduced as described above, the effect is extremely great, and an LSI that operates at high speed and consumes very little power can be realized.

(Modifications regarding the seventh to thirteenth embodiments)
The structure of the MT-nMOS device described in the thirteenth embodiment can be similarly applied to the MT-pMOS device and can exhibit the same effect. Needless to say, the present invention can also be applied to an MT-CMO device equipped with nMOSFETs and pMOSFETs having two different inversion voltages.

  In the seventh to thirteenth embodiments, a threshold control impurity may be introduced into a channel region below the gate electrode 8 of each MOSFET to provide a VT control impurity diffusion region. However, even in this case, it is not necessary to change the impurity concentration in each MOSFET, and even if the concentration of the impurity diffusion region for VT control is the same, the MOSFET having two types of inversion voltages can be formed because the impurity concentration in the pocket region is different. .

  In the thirteenth embodiment, the width of the pocket region 9a of the first nMOSFET is made larger than the width of the pocket region 9b of the second nMOSFET by largely tilting the BF2 ion implantation direction in the step shown in FIG. Thus, a MOSFET having two types of inversion voltages may be formed. Even in that case, the same effect as the above-mentioned thirteenth embodiment can be exhibited.

(Fourteenth embodiment)
FIG. 21A to FIG. 21R> 1 (d) are cross-sectional views showing the manufacturing process of the n-channel MOSFET in the fourteenth embodiment.

  First, in the step shown in FIG. 21A, a gate oxide film 24 made of a silicon oxide film having a thickness of 4 to 8 nm and a gate electrode 25 made of a polysilicon film having a thickness of 100 to 200 nm are formed on the p-type semiconductor substrate 21. And form.

  Next, in the step shown in FIG. 21B, arsenic ions (As +) are implanted into the gate electrode 25 and the regions 30 located on both sides of the gate electrode 25 in the semiconductor substrate 21.

Next, in the step shown in FIG. 21C, after a silicon oxide film (not shown) is deposited on the gate electrode 25 and the p-type semiconductor substrate 21 by the CVD method, this is etched back to obtain the gate electrode. Side walls 27 are formed on both side surfaces of 25. Then, using this sidewall 27 as a mask, fluorine ions (F +) are implanted into the gate electrode 25 and the region Rf located on the side of each sidewall 7 in the p-type semiconductor substrate 21. The implantation conditions at this time are an acceleration energy of 40 to 60 keV and an implantation amount of 1 to 5 × 10 ¹⁵ cm ⁻² .

Next, in the step shown in FIG. 21D, phosphorus ions (P +) are implanted using the sidewall 27 as a mask, and both sides of the gate electrode 25 and the gate electrode 25 in the p-type semiconductor substrate 21 are implanted. Phosphorus is introduced into the region located at. The implantation conditions at this time are an acceleration energy of 5 to 20 keV and an implantation amount of 1 to 4 × 10 ¹⁵ cm ⁻² . Further, in the state shown in FIG. 21 (d), a heat treatment is performed under the condition of 975 to 1050 ° C. for 10 seconds or 850 ° C. for 20 to 30 minutes to activate the impurity ions (P +), and the gate electrode 25 is an n-type gate electrode 25 a having a reduced resistance, and an n-type LDD region 30 a and n-type source / drain regions 32 a are formed in the p-type semiconductor substrate 21.

  Although the following steps are omitted, a MOSFET is formed by forming several layers of metal wiring through an interlayer insulating film.

  The nMOSFET formed by the manufacturing process of this embodiment can exhibit the following characteristics.

  First, in the source / drain region 32a, the source / drain region 32a is formed by introducing phosphorus, so that the impurity concentration of the source / drain region 32a is higher than that of the source / drain region formed by introducing arsenic. Change will be gradual. Therefore, it is possible to suppress the deterioration of the characteristics of the nMOSFET due to the impact ionization action of carriers and the increase in parasitic capacitance and leakage current.

  Second, in the step shown in FIG. 21 (d), if fluorine is introduced into the same region where phosphorus is implanted during the heat treatment, phosphorus diffusion is suppressed. The reason why this action occurs has not yet been elucidated, but it can be assumed that, for example, the following phenomenon occurs. In general, it is considered that when heat treatment for activation is performed, phosphorus diffuses in the silicon substrate while forming dangling bonds with interstitial silicon. However, when fluorine is present at the same site as phosphorus, fluorine has a stronger affinity for interstitial silicon than phosphorus, so interstitial silicon is taken in by fluorine and forms a dangling bond between phosphorus and interstitial silicon. As a result, it is presumed that the diffusion of phosphorus is suppressed. Therefore, compared with the source / drain region formed by implantation of only phosphorus ions, the diffusion layer depth of the source / drain region 32a can be suppressed, and the short channel effect can be suppressed. In other words, the reason why the source / drain regions of the nMOSFET are conventionally formed by implanting arsenic ions is that the short channel effect may become prominent if the source / drain regions are formed only by implanting phosphorus ions. . On the other hand, in this embodiment, fluorine is introduced together with phosphorus, so that the short channel effect can be suppressed while forming the source / drain region 32a by introducing phosphorus.

  Third, since the n-type gate electrode 25a is formed by introducing fluorine and phosphorus, phosphorus is sufficiently activated without performing heat treatment for a long time at a high temperature. Therefore, depletion of the gate electrode 25a due to inactivation of arsenic can be suppressed, and the driving power of the nMOSFET is increased.

  In this embodiment, fluorine and phosphorus are introduced by ion implantation. However, the present invention is not necessarily limited to such an embodiment. For example, fluorine or phosphorus can be introduced into a gate electrode or a semiconductor substrate using a vapor phase diffusion method or a plasma treatment method. Alternatively, fluorine or phosphorus can be introduced into the polysilicon film when the polysilicon film constituting the gate electrode is deposited by the CVD method.

  In the fourteenth embodiment, the sidewall 27 and the LDD region 30a are not necessarily formed. However, by forming the sidewall 27 and forming the LDD region 30a, a remarkable effect that a MOSFET suitable for miniaturization can be formed can be exhibited.

  In the present embodiment, fluorine ions are implanted after the sidewall 27 is formed. However, fluorine can be introduced before the sidewall 27 is formed. However, if CVD is performed at a high temperature when depositing the silicon oxide film for the sidewall, the fluorine function of suppressing the diffusion of phosphorus may be lost. It is preferable to use a low-temperature film formation method such as a plasma CVD method.

  Further, it is not necessary to introduce fluorine before introducing phosphorus as in the present embodiment, and even if phosphorus is introduced after introduction of phosphorus before heat treatment, diffusion of phosphorus is performed as in this embodiment. The function to suppress can be exhibited.

  Before forming the sidewall 27, for example, a channel length adjusting sidewall is formed in the state shown in FIG. 21B, and an LDD region is formed on this sidewall. Good. In particular, in that case, an appropriate channel length can be ensured even if the LDD region is formed by implantation of phosphorus ions.

(Fifteenth embodiment)
22A to 22E are cross-sectional views showing the manufacturing steps of the CMOSFET according to the fifteenth embodiment.

  First, in the step shown in FIG. 22A, a p-type semiconductor region 22a (p-type well or substrate region) is formed on the p-type semiconductor substrate 21 made of single crystal silicon in the nMOSFET formation region Rn. In the formation region Rp, an n-type semiconductor region 22b (n-type well or substrate region) is formed, and an element isolation 23 made of a silicon oxide film having a thickness of about 400 nm is formed, and the p-type semiconductor region 22a and the n-type semiconductor are formed. The area 22b is partitioned. However, in the present embodiment, the p-type semiconductor region 22 a is a region having the same impurity concentration as that of the p-type semiconductor substrate 21. A gate oxide film 24 made of a silicon oxide film having a thickness of 4 to 8 nm and a gate electrode 25 made of a polysilicon film having a thickness of 100 to 200 nm are formed on the p-type semiconductor region 22a and the n-type semiconductor region 22b. .

  Next, in the step shown in FIG. 22B, arsenic ions (As +) are implanted into the nMOSFET formation region Rn, and on both sides of the gate electrode 25 and the gate electrode 25 in the p-type semiconductor region 22a. Arsenic is introduced into the located region 30. Although not shown, the n-type semiconductor region 22b is covered with a resist mask while impurity ions are implanted into the p-type semiconductor region 22a. In the n-type semiconductor region 22b, boron ions (B +) are implanted to introduce boron into the gate electrode 25 and the regions 31 located on both sides of the gate electrode 25 in the n-type semiconductor region 22b. . Although not shown, the p-type semiconductor region 22a is covered with a resist mask while impurity ions are implanted into the n-type semiconductor region 22b.

Next, in the step shown in FIG. 22C, a silicon oxide film is deposited on the entire surface of the substrate by CVD, and then anisotropic dry etching is performed to etch back the silicon oxide film. A sidewall 27 is formed on the top. Thereafter, a resist film Rm1 is formed to cover the n-type semiconductor region 22b, and fluorine ions (F +) are implanted into the p-type semiconductor region 22a using the resist film Rm1 and each sidewall 27 as a mask. Then, fluorine is introduced into the gate electrode 25 and the region Rf located on the side of each sidewall 27 in the p-type semiconductor region 22a. The implantation conditions at this time are an acceleration energy of about 40 to 60 keV and an implantation amount of 1 to 5 × 10 ¹⁵ cm ⁻² . Subsequently, using the same resist film Rm1 and each sidewall 27 as a mask, phosphorus ions (P +) are implanted in the p-type semiconductor region 22a, and the gate electrode 25 and each side in the p-type semiconductor region 22a are implanted. Phosphorus is introduced into the region 32 located on the side of the wall 27. The implantation conditions at this time are an acceleration energy of 5 to 20 keV and an implantation amount of 2 to 4 × 10 ¹⁵ cm ⁻² .

Next, in the step shown in FIG. 22D, a resist film Rm2 is formed to cover the p-type semiconductor region 22a, and the resist film Rm2 and each side wall 27 are used as a mask to form an n-type semiconductor region 22b. Then, boron ions (B +) are implanted to introduce boron into the gate electrode 5 and the region 33 located on the side of each sidewall 27 in the n-type semiconductor region 22b. The implantation conditions at this time are an acceleration energy of 5 to 20 keV and an implantation amount of 1 to 4 × 10 ¹⁵ cm ⁻² .

  Further, in the state shown in FIG. 22E, heat treatment is performed under conditions of 975 to 1050 ° C. for 10 seconds to activate the impurities (P, B). By this process, in the nMOSFET formation region Rn, the gate electrode 25 is changed to the n-type gate electrode 25a whose resistance is reduced, and the n-type LDD region 30a and the n-type source / drain region 32a are formed. In the pMOSFET formation region Rp, the gate electrode 25 is a p-type gate electrode 25b with a reduced resistance, and a p-type LDD region 31a and a p-type source / drain region 33a are formed.

  Although the following steps are omitted, a semiconductor device is formed by forming several layers of metal wiring through an interlayer insulating film.

  The CMOS type semiconductor device according to this embodiment has the following features.

  First, the nMOSFET in the CMOSFET can exhibit the same effect as the first embodiment.

  Second, since the LDD region 30a and the source / drain region 32a of the nMOSFET are formed by introducing phosphorus, the LDD region 30a and the source / drain region 32a of the nMOSFET are changed to the LDD region of the pMOSFET after heat treatment under the same conditions. 31a and the source / drain region 33a can be formed in substantially the same shape, and the balance of the performance of each MOSFET is improved.

  Thirdly, since the n-type gate electrode 25a of the nMOSFET is formed by implantation of phosphorus ions, the n-type gate electrode 25b of the pMOSFET can be formed even in a heat treatment under a short time or low temperature condition so that boron does not penetrate through the p-type gate electrode 25b. The mold gate electrode 25a is sufficiently activated. That is, the nMOSFET can obtain a high driving force.

  In particular, in the pMOSFET formation region Rp, boron ions are implanted into the gate electrode 25 instead of BF2 ions, so that the diffusion promoting action of boron such as fluorine in the polysilicon film does not occur. That is, the reason why BF2 has been used as an impurity to be introduced into the pMOSFET conventionally is that the presence of fluorine suppresses the diffusion of boron in the silicon substrate, and the shape of the source / drain region is the shape of the source / drain region of the nMOSFET. In order to obtain good characteristics by adapting However, since the source / drain regions are formed by self-alignment with respect to the gate electrode, BF2 is inevitably introduced into the gate electrode of the pMOSFET. The fluorine in BF2 has a function of suppressing diffusion of both boron and phosphorus in the silicon single crystal. However, in the polysilicon film, the diffusion of phosphorus is suppressed but the adverse effect of promoting the diffusion of boron. give. Therefore, there is a possibility that penetration of boron in the gate electrode of the pMOSFET is promoted. On the other hand, in the present embodiment, phosphorus is introduced into the source / drain region instead of arsenic in the nMOSFET to weaken the heat treatment condition for activation, so that BF2 is not introduced into the source / drain region of the pMOSFET. However, it is easy to optimize the shape of the source / drain regions. Therefore, the impurity introduced into the gate electrode and the source / drain region of the pMOSFET can be only boron, and the above-described problems can be solved.

(Sixteenth embodiment)
Next, a sixteenth embodiment will be described. FIGS. 23A to 23C are cross-sectional views illustrating the manufacturing process of the CMOS type semiconductor device according to the third embodiment.

  First, in the step shown in FIG. 23A, a p-type semiconductor region 22a is formed in the nMOSFET formation region Rn and an n-type semiconductor is formed in the pMOSFET formation region Rp on the p-type semiconductor substrate 21 made of single crystal silicon. Each region 22b is formed, and an element isolation 23 made of a silicon oxide film having a thickness of about 400 nm is formed to partition the p-type semiconductor region 22a and the n-type semiconductor region 22b. However, in the present embodiment, the p-type semiconductor region 22 a is a region having the same impurity concentration as that of the p-type semiconductor substrate 21. A gate oxide film 24 made of a silicon oxide film having a thickness of 4 to 8 nm and a gate electrode 25 made of a polysilicon film having a thickness of 100 to 200 nm are formed on the p-type semiconductor region 22a and the n-type semiconductor region 22b. .

  Next, in the step shown in FIG. 23B, arsenic ions (As +) are implanted in the nMOSFET formation region Rn, and on both sides of the gate electrode 25 and the gate electrode 25 in the p-type semiconductor region 22a. Arsenic is introduced into the located region 30. Although not shown, the n-type semiconductor region 22b is covered with a resist mask while impurity ions are implanted into the p-type semiconductor region 22a. In the pMOSFET formation region Rp, boron ions (B +) are implanted to introduce boron into the gate electrode 25 and the regions 31 located on both sides of the gate electrode 25 in the n-type semiconductor region 22b. Although not shown, the p-type semiconductor region 22a is covered with a resist mask while impurity ions are implanted into the n-type semiconductor region 22b.

Next, after depositing a silicon oxide film on the entire surface of the substrate by CVD, anisotropic dry etching is performed to etch back the silicon oxide film and form sidewalls 27 on both side surfaces of the gate electrode 25. Thereafter, germanium fluoride ions (GeF4 +) are implanted into the entire surface in both the p-type semiconductor region 22a and the n-type semiconductor region 22b, and the gate electrode 25 and the side walls 27 in the semiconductor regions 22a and 22b are laterally formed. Fluorine and germanium are simultaneously introduced into the region Rfg located in the region. The implantation conditions are an acceleration energy of 20 to 80 keV and an implantation amount of 1 to 4 × 10 ¹⁴ cm ⁻² .

  Thereafter, in the step shown in FIG. 23 (c), the same steps as those shown in FIGS. 22 (c) to 22 (e) in the fifteenth embodiment are performed (however, fluorine ions are not implanted again). In the nMOSFET formation region Rn, the gate electrode 25 is made an n-type gate electrode 25a having a reduced resistance, and an n-type low concentration source / drain region 30a and an n-type high concentration source / drain region 32a are formed. In the pMOSFET formation region Rp, the gate electrode 25 is a p-type gate electrode 25b with a reduced resistance, and a p-type low concentration source / drain region 31a and a p-type high concentration source / drain region 33a are formed. To do.

  Although the following steps are omitted, a semiconductor device is formed by forming several layers of metal wiring through an interlayer insulating film.

  The CMOS type semiconductor device of this embodiment basically has the following characteristics by introducing fluorine and germanium into the gate electrode and the source / drain regions of each MOS transistor.

  First, in the nMOSFET, since fluorine is introduced into the n-type gate electrode 25a and the source / drain regions 32a together with phosphorus, the same effects as those of the fifteenth embodiment can be exhibited. In addition, since germanium is introduced, the regions where the n-type gate electrode 25a and the source / drain regions 32a in the semiconductor substrate are to be formed are made amorphous. Phosphorus ion channeling is suppressed. Therefore, the implantation depth at the time of phosphorus ion implantation can be reduced, and the above-described problems in the nMOSFET can be solved more reliably.

  In the pMOSFET, germanium fluoride ions are implanted into the p-type gate electrode 25b and the source / drain regions 33a before boron ions are implanted. The fluorine in the germanium fluoride promotes the diffusion of boron in the gate electrode 25b as described above. However, since germanium is also implanted at the same time, the polysilicon film is made amorphous, and the boron ion implantation depth becomes shallow. In addition, the amount of germanium fluoride ions need not be increased as much as the amount of BF2 ions used to form the source / drain regions 33a. Therefore, even if fluorine exists in the gate electrode 25b of the pMOSFET as a whole, Can suppress boron penetration. Therefore, in the present embodiment, in addition to the diffusion suppressing function due to the presence of fluorine, it is possible to adjust the shape of the fine source / drain regions 33a due to the presence of germanium. In particular, implantation of germanium fluoride ions has an advantage that introduction of fluorine and introduction of germanium can be performed simultaneously.

  However, in the step shown in FIG. 23B in this embodiment, germanium fluoride ion implantation may be performed only on the p-type semiconductor region 22a side. In that case, since germanium fluoride is not implanted into the pMOSFET, the above-described phosphorous ion implantation depth suppressing effect and phosphorus diffusion suppressing function can be exhibited only in the nMOSFET.

  In the present embodiment, the manufacturing process of the CMOS type semiconductor device has been described. However, even when only the nMOSFET is formed, germanium fluoride ion implantation may be performed instead of the fluorine ion shown in FIG. Good.

  (Seventeenth Embodiment) FIG. 24 is a cross-sectional view of an MT-CMOS device according to this embodiment, and FIGS. 25A to 25C are cross-sectional views showing a manufacturing process of the MT-CMOS device according to this embodiment. It is.

  As shown in FIG. 24, in this embodiment, a p-type well 42a containing a p-type impurity and an n-type well 42b containing an n-type impurity are formed in a semiconductor substrate 41. A region near the p-type well 42a is an nMOSFET formation region Rn for forming an nMOSFET, and a region near the n-type well 42b is a pMOSFET formation region Rp for forming a pMOSFET. Further, due to the element isolation 43, the nMOSFET formation region Rn is partitioned into a first nMOSFET formation region Rn1 and a second nMOSFET formation region Rn2, and the pMOSFET formation region Rp is partitioned into a first pMOSFET formation region Rp1 and a second pMOSFET formation region Rp2. . The first nMOSFET formed in the first nMOSFET formation region Rn1 is a MOSFET having a high inversion voltage, and the second nMOSFET formed in the second nMOSFET formation region Rn2 is a MOSFET having a low inversion voltage. The first pMOSFET formed in the first pMOSFET formation region Rp1 is a MOSFET having a high inversion voltage, and the second pMOSFET formed in the second pMOSFET formation region Rp2 is a MOSFET having a low inversion voltage.

  The first nMOSFET includes a gate electrode 48, a gate insulating film 47, a relatively high concentration p-type channel region 44a, and n + -type source / drain regions 54. The second nMOSFET includes a gate electrode 48, a gate insulating film 47, a relatively low concentration p-type channel region 44b, and n + -type source / drain regions 54. The first pMOSFET includes a gate electrode 48, a gate insulating film 47, a relatively high concentration n-type channel region 46a, and a p + -type source / drain region 55. On the other hand, in the second pMOSFET, in addition to the gate electrode 48, the gate insulating film 47, the relatively low concentration n-type channel region 46b, and the p + -type source / drain region 55, the second pMOSFET is directly below the gate insulating film 47. A boron diffusion region Rbo formed by introducing boron ions on the side is provided.

  The MT-CMOS device of this embodiment has first and second nMOSFETs and first and second pMOSFETs each having different inversion voltages. Then, a p-type impurity (boron) having a higher concentration than that of the channel region 44b of the second nMOSFET is introduced into the channel region 44a of the first nMOSFET, and the difference in level of the inversion voltage with respect to the second nMOSFET is caused by the difference in the impurity concentration. Provided. Further, a boron diffusion region Rbo is provided in the channel region 46b of the second pMOSFET, and a difference in level of the inversion voltage with respect to the first pMOSFET is provided by a difference in n-type carrier concentration resulting from this counter doping.

  In this embodiment, since the boron diffusion region Rbo is provided in the channel region 46b of the second pMOSFET, the concentration of the n-type impurity in the channel region 46b of the second pMOSFET is the same as the concentration of the n-type impurity in the channel region of the first pMOSFET. However, the inversion voltage of the second pMOSFET can be made smaller than the inversion voltage of the first pMOSFET. As a result, it is possible to alleviate the short channel effect that is normally unavoidable for low inversion voltage MOSFETs. Therefore, it is possible to provide an MT-CMOS device having a high breakdown voltage and capable of suppressing the short channel effect of the low inversion voltage MOSFET.

  Next, the manufacturing process of the MT-CMOS device according to this embodiment will be described with reference to FIGS.

First, in the step shown in FIG. 25A, a p-type well 42a and an n-type well 42b are formed on a semiconductor substrate 41 made of single crystal silicon, and an element made of a silicon oxide film having a thickness of about 400 nm. An isolation 43 is formed to partition the first nMOSFET formation region Rn1, the second nMOSFET formation region Rn2, the second pMOSFET formation region Rp2, and the first pMOSFET formation region Rp1. Then, by a normal photolithography process, a resist film (not shown) that opens only the nMOSFET formation region Rn and covers the pMOSFET formation region Rp is formed, and with this resist film as a mask, boron ions ( B +) is implanted to form channel regions 44a and 44b of the first and second nMOSFETs. Boron ion implantation conditions are 10-40 KeV, 4-8 × 10 ¹² cm ⁻² . Further, a resist film (not shown) is formed to open only the pMOSFET forming region Rp and cover the nMOSFET forming region Rn, and using this resist film as a mask, phosphorus ions (P +) are implanted into the pMOSFET forming region Rp. Channel regions 46a and 46b of the first and second pMOSFETs are formed. The implantation conditions of phosphorus ions are 10-40 KeV, 4-8 × 10 ¹² cm ⁻² .

Next, in the step shown in FIG. 25B, a resist film 56a having only the first nMOSFET formation region Rn1 and the second pMOSFET formation region Rp2 is formed by a normal photolithography process, and the resist film 56a is used as a mask. Boron ions (B +) are implanted into the first nMOSFET formation region Rn1 and the second pMOSFET formation region Rp2, and additional implantation is performed in the channel region 44a of the first nMOSFET, while counterdoping is performed in the channel region 46b of the second pMOSFET. The ion implantation conditions at this time are 10-40 KeV, 2-6 × 10 ¹² cm ⁻² .

  Next, in the step shown in FIG. 25C, a silicon oxide film having a thickness of 8-12 nm is formed, and a polysilicon film having a thickness of 150-250 nm is further deposited thereon, and a normal lithography process and etching process are performed. Thus, the gate insulating film 47 and the gate electrode 48 of each MOSFET are patterned. Further, arsenic is implanted into the nMOSFET formation region Rn and boron ions (B + or BF2 +) are implanted into the nFET formation region Rp by the same process as the conditions shown in the above embodiments. A region 54 and a source / drain region 55 of each pMOSFET are formed.

  That is, the concentrations of the p-type impurity and the n-type impurity introduced in the step shown in FIG. 25A are p25a and n25a, respectively, and the concentration of the p-type impurity introduced in the step shown in FIG. Then, the effective impurity concentration (carrier concentration) of each region is as follows. However, the impurity concentration in each well is ignored.

  First nMOSFET channel region 44a p25a + p25b Second nMOSFET channel region 44b p25a First pMOSFET channel region 46a n25a Second pMOSFET channel region 46b n25a -p25b The structure of the MT-CMOS device shown in FIG. can get. In particular, in the manufacturing method of the present embodiment, two photomasks for inversion voltage control are sufficient in the steps shown in FIGS. On the other hand, when the conventional process shown in FIGS. 30A to 30D is applied to an MT-CMOS device as it is, in order to form a channel region in the first nMOSFET, the second nMOSFET, the first pMOSFET, and the second pMOSFET, It is easily understood that it is necessary to form four types of resist films having openings only in the MOSFET formation regions Rn1, Rn2, Rp1, and Rp2. Therefore, in the method for manufacturing the semiconductor device according to the present embodiment, two photomask forming steps can be reduced as compared with the conventional method, and the steps can be simplified.

(Eighteenth embodiment)
FIG. 26 is a cross-sectional view of the MT-CMOS device according to the present embodiment, and FIGS. 27A to 27C are cross-sectional views illustrating manufacturing steps of the MT-CMOS device according to the present embodiment.

  As shown in FIG. 26, the structure of the MT-CMOS device according to this embodiment is basically the same as the structure of the MT-CMOS device according to the seventeenth embodiment. That is, each MOSFET in the present embodiment is the same as the seventeenth embodiment in that it includes a gate insulating film 47, a gate electrode 48, and source / drain regions 54 or 55. Here, the difference from the seventeenth embodiment will be explained. Although the channel region 44a of the first nMOSFET contains a relatively high concentration of boron, the channel region 44b of the second nMOSFET is counter-doped with phosphorus. A phosphorus diffusion region Rph is provided. The presence of the phosphorus diffusion region Rph is configured to reduce the inversion voltage of the second nMOSFET. Further, the n-type impurity (phosphorus) having a higher concentration than that of the channel region 46b of the second pMOSFET is introduced into the channel region 46a of the first pMOSFET, and the difference in the inverted voltage with respect to the second pMOSFET is caused by the difference in the impurity concentration. Provided.

  In the present embodiment, since the phosphorus diffusion region Rph is provided in the channel region 44b of the second nMOSFET, the concentration of the p-type impurity in the channel region 44b of the second nMOSFET is the same as the concentration of the p-type impurity in the channel region of the first nMOSFET. However, the inversion voltage of the second nMOSFET can be made smaller than the inversion voltage of the first nMOSFET. As a result, it is possible to alleviate the short channel effect that is normally unavoidable for low inversion voltage MOSFETs. Therefore, it is possible to provide an MT-CMOS device having a high breakdown voltage and capable of suppressing the short channel effect of the low inversion voltage MOSFET.

  Next, a manufacturing process of the MT-CMOS device according to the present embodiment will be described with reference to FIGS.

  First, in the process shown in FIG. 27A, various processes are performed under the same conditions as in the process shown in FIG. 2525A. The ion implantation conditions for forming the channel regions 44a, 44b and 46a, 46b are the same as those in the seventeenth embodiment.

Next, in the process shown in FIG. 27B, a resist film 56b having openings only in the second nMOSFET formation region Rn2 and the first pMOSFET formation region Rp1 is formed by a normal photolithography process, and the resist film 56b is used as a mask. Phosphorus ions (P +) are implanted into the second nMOSFET formation region Rn2 and the first pMOSFET formation region Rp1, and additional implantation is performed in the channel region 46a of the first pMOSFET, while counterdoping is performed in the channel region 44b of the second nMOSFET. The ion implantation conditions at this time are 20-60 KeV, 2-6 × 10 ¹² cm ⁻² .

  Next, in the step shown in FIG. 27C, a silicon oxide film having a thickness of 8-12 nm is formed, and a polysilicon film having a thickness of 150-250 nm is further deposited thereon, and a normal lithography process and etching process are performed. Thus, the gate insulating film 47 and the gate electrode 48 of each MOSFET are patterned. Further, arsenic is implanted into the nMOSFET formation region Rn and boron ions (B + or BF2 +) are implanted into the nFET formation region Rp by the same process as the conditions shown in the above embodiments. A region 54 and a source / drain region 55 of each pMOSFET are formed.

  That is, the concentrations of the p-type impurity and the n-type impurity introduced in the step shown in FIG. 27A are p27a and n27a, respectively, and the concentration of the p-type impurity introduced in the step shown in FIG. Then, the effective impurity concentration (carrier concentration) of each region is as follows. However, the impurity concentration in each well is ignored.

  26. First nMOSFET channel region 44a p27a Second nMOSFET channel region 44b p27a -n27b First pMOSFET channel region 46a n27a + n27b Second pMOSFET channel region 46b n27a The structure of the MT-CMOS device shown in FIG. can get. In particular, in the manufacturing method of the present embodiment, two photomasks for inversion voltage control are sufficient in the steps shown in FIGS. On the other hand, when the conventional process shown in FIGS. 30A to 30D is applied to an MT-CMOS device as it is, in order to form a channel region in the first nMOSFET, the second nMOSFET, the first pMOSFET, and the second pMOSFET, It is easily understood that it is necessary to form four types of resist films having openings only in the MOSFET formation regions Rn1, Rn2, Rp1, and Rp2. Therefore, in the method for manufacturing the semiconductor device according to the present embodiment, two photomask forming steps can be reduced as compared with the conventional method, and the steps can be simplified.

(Nineteenth embodiment)
FIG. 28 is a cross-sectional view of an MT-CMOS device according to the present embodiment, and FIGS. 29A to 29C are cross-sectional views illustrating manufacturing steps of the MT-CMOS device according to the present embodiment.

  As shown in FIG. 28, in this embodiment, a p-type well 42a and an n-type well 42b are formed, and a high inversion voltage type first nMOSFET and a low inversion voltage are formed in the p-type well 42a (nMOSFET formation region Rn). A second nMOSFET of the type. The p-type well 42b (pMOSFET formation region Rp) is provided with a high inversion voltage type first pMOSFET and a low inversion voltage type second pMOSFET.

  The first nMOSFET includes a gate electrode 48 a made of a polysilicon film, a gate insulating film 47 a made of an oxide film, a p-type channel region 44, and n + -type source / drain regions 54. The second nMOSFET includes a gate electrode 48b made of a polysilicon film into which nitrogen is introduced, a gate insulating film 47b made of an oxide film containing nitrogen, that is, a nitrided oxide film, a p-type channel region 44, an n + type Source / drain regions 54. The first pMOSFET includes a gate electrode 48a made of a polysilicon film, a gate insulating film 47a made of an oxide film, an n-type channel region 46, and a p + -type source / drain region 55. On the other hand, the second pMOSFET includes a gate electrode 48b made of a polysilicon film into which nitrogen is introduced, a gate insulating film 47b made of an oxide film containing nitrogen, that is, a nitrided oxide film, an n-type channel region 46, and a p + -type. Source / drain regions 55 are provided.

  In this embodiment, the inversion voltage is reduced by introducing nitrogen into the silicon oxide film constituting the gate insulating film 47b of the low inversion voltage type second nMOSFET and second pMOSFET, and the inversion voltage with respect to the first nMOSFET and the first pMOSFET, respectively. It is comprised so that the height difference with respect to may be produced. That is, since the dielectric constant of the silicon nitride film is higher than that of the silicon oxide film, the inversion voltage can be lowered even with the same film thickness by using the silicon nitride oxide film as the gate insulating film. Here, since the dielectric constant of the silicon oxide film is about 3.8, whereas the dielectric constant of the silicon nitride film is about 6.7, the inversion voltage of the MOSFET can be adjusted by appropriately adjusting the nitrogen injection amount. The dielectric constant of the silicon oxynitride film can be adjusted so that becomes a desired value. Further, since the nitride oxide film has better characteristics such as withstand voltage than the oxide film, it can be expected to improve the reliability of the semiconductor device.

  Next, the manufacturing process of the MT-CMOS device according to this embodiment will be described.

First, in the process shown in FIG. 29A, various processes are performed under the same conditions as in the process shown in FIG. 2525A. However, the boron ion implantation conditions for forming the channel region 44 of the first and second nMOSFETs are 10-40 KeV, 2-8 × 10 ¹³ cm ⁻² . The conditions for implanting phosphorus ions when forming the channel region 46 of the first and second pMOSFETs are 10-40 KeV, 2-8 × 10 ¹³ cm ⁻² .

Next, in the step shown in FIG. 29B, a silicon oxide film having a thickness of 8-12 nm is formed, and a polysilicon film having a thickness of 150-250 nm is further deposited thereon, and a normal lithography process and etching process are performed. Thus, the gate insulating films 47a and 47b and the gate electrodes 48a and 48b of each MOSFET are patterned. Further, a resist film 56c having openings only in the second nMOSFET formation region Rn2 and the second pMOSFET formation region Rp2 is formed by a normal photolithography process, and the second nMOSFET formation region Rn2 and the second pMOSFET formation region Rp2 are formed using the resist film 56c as a mask. Nitrogen ions (N +) are implanted in The ion implantation conditions at this time are 20-60 KeV, 8 × 10 ¹⁵ -2 × 10 ¹⁶ cm ⁻² 2-6 × 10 ¹² cm ⁻² . By this nitrogen ion implantation, the introduced nitrogen quickly diffuses through a subsequent heat treatment step and reaches the gate insulating film 47b of the second nMOSFET and the second pMOSFET, so that the silicon oxide film is nitrided and the nitrided oxide film Become.

  Next, in the step shown in FIG. 29C, arsenic is formed in the nMOSFET formation region Rn and boron ions (B + or BF2 + in the pFET formation Rp by the same steps as those described in the above embodiments. ) To form source / drain regions 54 of each nMOSFET and source / drain regions 55 of each pMOSFET.

  Through the above steps, the structure of the MT-CMOS device shown in FIG. 28 can be easily obtained. In particular, in the manufacturing method of the present embodiment, two photomasks for controlling the inversion voltage are sufficient in the steps shown in FIGS. On the other hand, when the conventional process shown in FIGS. 30A to 30D is applied to an MT-CMOS device as it is, in order to form a channel region in the first nMOSFET, the second nMOSFET, the first pMOSFET, and the second pMOSFET, It is easily understood that it is necessary to form four types of resist films having openings only in the MOSFET formation regions Rn1, Rn2, Rp1, and Rp2. Therefore, in the method for manufacturing the semiconductor device according to the present embodiment, two photomask forming steps can be reduced as compared with the conventional method, and the steps can be simplified.

(Modifications for the 17th to 19th embodiments)
In the seventeenth to nineteenth embodiments, LDD regions and pocket regions are not formed in each MOSFET, but the same LDD regions and pocket regions as those in the first to sixteenth embodiments are provided, It goes without saying that a structure suitable for further miniaturization can be obtained.

It is sectional drawing which shows the structure of the MT-nMOS device which concerns on 1st Embodiment. It is sectional drawing which shows the state which applied the substrate bias to the MT-MOS device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing process of the MT-nMOS device which concerns on 1st Embodiment. It is sectional drawing which shows the structure of the MT-nMOS device which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the MT-CMOS device which concerns on 3rd Embodiment. It is sectional drawing which shows the state which applied the substrate bias to the MT-CMOS device which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing process of the MT-CMOS device which concerns on 3rd Embodiment. It is sectional drawing which shows the manufacturing process of the MT-CMOS device which concerns on 4th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-CMOS device which concerns on 5th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-nMOS device which concerns on 6th Embodiment which has what is called SPI structure. It is sectional drawing which shows the structure of the MT-nMOS device which concerns on 7th Embodiment. It is a figure which shows the effective impurity density, ie, carrier density, in the semiconductor substrate surface vicinity of the MT-nMOS device which concerns on 7th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-nMOS device which concerns on 7th Embodiment. It is sectional drawing which shows the structure of the MT-nMOS device which concerns on 8th Embodiment. It is sectional drawing which shows the structure of the MT-CMOS device which concerns on 9th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-CMOS device which concerns on 9th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-pMOS device which concerns on 10th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-pMOS device which concerns on 11th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-pMOS device which concerns on 12th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-nMOS device which concerns on 13th Embodiment. It is sectional drawing which shows the manufacturing process of nMOSFET which concerns on 14th Embodiment. It is sectional drawing which shows the manufacturing process of the CMOS device which concerns on 15th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-nMOS device which concerns on 16th Embodiment. It is sectional drawing which shows the structure of the MT-CMOS device which concerns on 17th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-CMOS device which concerns on 17th Embodiment. It is sectional drawing which shows the structure of the MT-CMOS device which concerns on 18th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-CMOS device which concerns on 18th Embodiment. It is sectional drawing which shows the structure of the MT-CMOS device which concerns on 19th Embodiment. It is sectional drawing which shows the manufacturing process of the MT-CMOS device which concerns on 19th Embodiment. It is sectional drawing which shows the manufacturing process of the conventional MT-nMOS device. It is sectional drawing which shows the manufacturing process of the conventional CMOS device.

Explanation of symbols

1 semiconductor substrate 1a substrate region 2a p-type well (p-type substrate region)
2b n-type well (n-type substrate region)
3 Element isolation 4, 6 Channel region 7 Gate insulating film 8 Gate electrode 9, 10 Pocket region 11, 12 LDD region 13 Side wall 14, 15 Source / drain region 16 Resist film 17 Titanium silicide film

Claims (2)

In a semiconductor device having at least an nMISFET formed in a part of a semiconductor substrate,
The nMISFET is
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film and introduced with at least fluorine-containing impurities and phosphorus;
A semiconductor device comprising: an n-type source / drain region formed in regions located on both sides of the gate electrode of the semiconductor substrate, into which impurities containing at least fluorine and phosphorus are introduced. A first step of forming a gate insulating film on the nMISFET formation region in the semiconductor substrate;
A second step of forming a gate electrode on the gate insulating film;
A third step of introducing an impurity containing at least fluorine into the gate electrode and regions located on both sides of the gate electrode in the semiconductor substrate in the nMISFET formation region;
A fourth step of introducing phosphorous into the nMISFET formation region after or before the third step into the gate electrode and regions located on both sides of the gate electrode in the semiconductor substrate;
After the third and fourth steps, the phosphorus is diffused and activated by heat treatment to make the gate electrode a low-resistance n-type gate electrode and positioned on both sides of the gate electrode in the semiconductor substrate. And a fifth step of forming an n-type source / drain region in the region to be manufactured.

Images