JP2005260080A5 - - Google Patents
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- JP2005260080A5 JP2005260080A5 JP2004071295A JP2004071295A JP2005260080A5 JP 2005260080 A5 JP2005260080 A5 JP 2005260080A5 JP 2004071295 A JP2004071295 A JP 2004071295A JP 2004071295 A JP2004071295 A JP 2004071295A JP 2005260080 A5 JP2005260080 A5 JP 2005260080A5
- Authority
- JP
- Japan
- Prior art keywords
- via hole
- forming
- main surface
- wiring layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000010410 layer Substances 0.000 claims 34
- 239000004065 semiconductor Substances 0.000 claims 29
- 230000003014 reinforcing effect Effects 0.000 claims 16
- 239000000758 substrate Substances 0.000 claims 13
- 239000011241 protective layer Substances 0.000 claims 6
- 238000004519 manufacturing process Methods 0.000 claims 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims 2
- 238000000034 method Methods 0.000 claims 1
Claims (9)
前記半導体チップの第１の主面上に接着された支持体と、
前記半導体チップの第２の主面から前記パッド電極に到達するビアホールと、
前記ビアホールを通して、前記パッド電極と電気的に接続され、かつ前記ビアホールから前記半導体チップの第２の主面上に延びる配線層と、
前記配線層上を覆うようにして形成され、かつ当該配線層を補強する補強層と、を有することを特徴とする半導体装置。 A pad electrode formed on the first main surface of the semiconductor chip;
A support bonded on the first main surface of the semiconductor chip;
Via holes reaching the pad electrodes from the second main surface of the semiconductor chip;
A wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor chip;
And a reinforcing layer formed to cover the wiring layer and reinforcing the wiring layer.
前記半導体チップの第２の主面から前記パッド電極に到達するビアホールと、Via holes reaching the pad electrodes from the second main surface of the semiconductor chip;
前記ビアホールを通して、前記パッド電極と電気的に接続され、かつ前記ビアホールから前記半導体チップの第２の主面上に延びる配線層と、A wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor chip;
前記配線層上を覆うようにして形成され、かつ当該配線層を補強する補強層と、を有することを特徴とする半導体装置。And a reinforcing layer formed to cover the wiring layer and reinforcing the wiring layer.
前記補強層上を覆うようにして形成された保護層と、
前記補強層及び前記保護層の一部を開口する開口部と、
前記開口部で露出する前記配線層上に形成された導電端子と、を有し、
前記配線層は、前記ビアホールを通して、前記パッド電極と電気的に接続され、かつ前記ビアホールから前記絶縁膜上を含む前記半導体チップの第２の主面上に延びていることを特徴とする請求項１または請求項２に記載の半導体装置。 An insulating film formed from the second main surface of the semiconductor chip to the sidewall of the via hole;
A protective layer formed so as to cover the reinforcing layer;
An opening for opening a part of the reinforcing layer and the protective layer;
A conductive terminal formed on the wiring layer exposed at the opening,
The wiring layer is electrically connected to the pad electrode through the via hole and extends from the via hole onto a second main surface of the semiconductor chip including on the insulating film. 3. The semiconductor device according to claim 1 or 2.
前記半導体基板の第１の主面上に支持体を接着する工程と、
前記半導体基板の第２の主面から前記パッド電極に到達するビアホールを形成する工程と、
前記ビアホールを通して、前記パッド電極と電気的に接続され、かつ前記ビアホールから前記半導体基板の第２の主面上に延びる配線層を形成する工程と、
前記配線層上を覆うようにして、当該配線層を補強する補強層を形成する工程と、を有することを特徴とする半導体装置の製造方法。 Prepare a semiconductor substrate on which pad electrodes are formed,
Adhering a support on the first main surface of the semiconductor substrate;
Forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate;
Forming a wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor substrate;
And a step of forming a reinforcing layer that reinforces the wiring layer so as to cover the wiring layer .
前記半導体基板の第２の主面から前記パッド電極に到達するビアホールを形成する工程と、
前記ビアホールを通して、前記パッド電極と電気的に接続され、かつ前記ビアホールから前記半導体基板の第２の主面上に延びる配線層を形成する工程と、
前記配線層上を覆うようにして、当該配線層を補強する補強層を形成する工程と、を有することを特徴とする半導体装置の製造方法。 Preparing a semiconductor substrate having a pad electrode formed on the first main surface;
Forming a via hole reaching the pad electrode from the second main surface of the semiconductor substrate;
Forming a wiring layer electrically connected to the pad electrode through the via hole and extending from the via hole onto the second main surface of the semiconductor substrate;
And a step of forming a reinforcing layer that reinforces the wiring layer so as to cover the wiring layer .
前記ビアホールを形成した後、前記ビアホール内を含む前記半導体基板の第２の主面上に第２の絶縁膜を形成する工程と、Forming a second insulating film on a second main surface of the semiconductor substrate including the inside of the via hole after forming the via hole;
前記第２の絶縁膜を異方性エッチングして、前記ビアホールの底部に位置する第２の絶縁膜を除去して、前記ビアホールの側壁に側壁絶縁膜を形成する工程と、Anisotropically etching the second insulating film to remove the second insulating film located at the bottom of the via hole and forming a sidewall insulating film on the side wall of the via hole;
前記配線層及び前記補強層を形成した後、前記補強層上を覆うようにして保護層を形成する工程と、After forming the wiring layer and the reinforcing layer, forming a protective layer so as to cover the reinforcing layer;
前記補強層及び前記保護層の一部をエッチングして、前記配線層の一部を露出する開口部を形成する工程と、Etching the reinforcing layer and part of the protective layer to form an opening exposing a part of the wiring layer;
前記開口部で露出する前記配線層上に導電端子を形成する工程と、Forming a conductive terminal on the wiring layer exposed at the opening;
前記半導体基板を複数の半導体チップに分割する工程と、を有することを特徴とする請求項５または請求項６に記載の半導体装置の製造方法。The method of manufacturing a semiconductor device according to claim 5, further comprising a step of dividing the semiconductor substrate into a plurality of semiconductor chips.
前記ビアホールの底部に位置する前記絶縁膜を除去して、前記ビアホールの側壁に側壁絶縁膜を形成する工程と、Removing the insulating film located at the bottom of the via hole and forming a sidewall insulating film on the sidewall of the via hole;
前記配線層及び前記補強層を形成した後、前記補強層上を覆うようにして保護層を形成する工程と、After forming the wiring layer and the reinforcing layer, forming a protective layer so as to cover the reinforcing layer;
前記補強層及び前記保護層の一部を除去して、前記配線層の一部を露出する開口部を形成する工程と、Removing a part of the reinforcing layer and the protective layer to form an opening exposing a part of the wiring layer;
前記開口部で露出する前記配線層上に導電端子を形成する工程と、Forming a conductive terminal on the wiring layer exposed at the opening;
前記半導体基板を複数の半導体チップに分割する工程と、を有することを特徴とする請求項５、６、７に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 5, further comprising a step of dividing the semiconductor substrate into a plurality of semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004071295A JP2005260080A (en) | 2004-03-12 | 2004-03-12 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004071295A JP2005260080A (en) | 2004-03-12 | 2004-03-12 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2005260080A JP2005260080A (en) | 2005-09-22 |
| JP2005260080A5 true JP2005260080A5 (en) | 2007-04-19 |
Family
ID=35085498
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004071295A Pending JP2005260080A (en) | 2004-03-12 | 2004-03-12 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2005260080A (en) |
-
2004
- 2004-03-12 JP JP2004071295A patent/JP2005260080A/en active Pending
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