JP2005252203A - Insulated gate semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an insulated gate semiconductor device and a method for manufacturing the same, in which a decrease in breakdown voltage due to a seam is suppressed.
A gate trench is formed by dry etching. Next, the oxide film 23 is buried in the gate trench 21. At this time, the film is formed not to completely fill the gate trench 21 but to leave some gaps. Next, the nitride film 231 is buried in the gap. Next, the nitride film 231 and the oxide film 23 are etched back by performing wet etching. At this time, the nitride film 231 is hardly etched and remains in the gate trench 21. Next, an oxide film 24 is formed on the wall surface of the gate trench 21. Next, the gate material 22 is deposited. Finally, the deposited gate material 22 is etched, and then a source electrode and a drain electrode are formed.
[Selection] Figure 1

Description

  The present invention relates to an insulated gate semiconductor device having a trench gate structure and a method for manufacturing the same. More specifically, the present invention relates to an insulated gate semiconductor device that achieves both high breakdown voltage and low on-resistance by relaxing an electric field applied to a semiconductor layer, and a method for manufacturing the same.

  Conventionally, a trench gate type semiconductor device having a trench gate structure has been proposed as an insulated gate type semiconductor device for power devices. In this trench gate type semiconductor device, a high breakdown voltage and a low on-resistance are generally in a trade-off relationship.

The present applicant has proposed an insulated gate semiconductor device 900 as shown in FIG. 10 as a trench gate type semiconductor device that solves this problem (Japanese Patent Application No. 2003-349806). In this insulated gate semiconductor device 900, an N ⁺ source region 31, an N ⁺ drain region 11, a P ⁻ body region 41, and an N ⁻ drift region 12 are provided. Further, the gate trench 21 penetrating the P ⁻ body region 41 is formed by digging a part of the upper surface side of the semiconductor substrate. A deposited insulating layer 23 is formed on the bottom of the gate trench 21 by depositing an insulator. Further, a gate electrode 22 is formed on the deposited insulating layer 23. The gate electrode 22 faces the N ⁺ source region 31 and the P ⁻ body region 41 via the gate insulating film 24 formed on the wall surface of the gate trench 21. Further, a P floating region 51 is formed in the N ⁻ drift region 12. The lower end of the gate trench 21 is located in the P floating region 51.

The insulated gate semiconductor device 900 has the following characteristics as compared with an insulated gate semiconductor device having no P-type floating region 51 because the P floating region 51 is provided in the N ⁻ drift region 12. In other words, when the gate voltage is switched off, a depletion layer is formed in the N ⁻ drift region 12 from the PN junction with the P ⁻ body region 41 due to the drain-source voltage (hereinafter referred to as “between DS”). It is formed. And the vicinity of the PN junction location becomes a peak of electric field strength. When the tip of the depletion layer reaches the P floating region 51, the P floating region 51 enters a punch-through state and its potential is fixed. Further, when the applied voltage between the DSs is high, a depletion layer is also formed from the lower end of the P floating region 51. In addition to the PN junction between the P ⁻ body region 41 and the vicinity of the lower end of the P floating region 51, the electric field strength peaks. That is, the electric field peak can be formed at two locations, and the maximum withstand voltage can be increased by reducing the maximum peak value. Further, since the withstand voltage is high, the on-resistance can be lowered by increasing the impurity concentration of the N ⁻ drift region 12.

In this insulated gate semiconductor device 900, it is necessary to provide a deposited insulating layer 23 having a predetermined thickness in the trench 21. That is, since the P floating region 51 is formed by ion implantation or the like from the bottom of the trench 21, the bottom of the trench 21 is not a little damaged. However, the presence of the deposited insulating layer 23 can avoid the influence of damage to the bottom of the trench 21 and can prevent deterioration of device characteristics and reliability. Further, the deposited insulating layer 23 can alleviate the influence of the facing of the gate electrode 22 and the P floating region 51, and the on resistance in the P ⁻ body region 41 can be reduced. Further, since the deposited insulating layer 23 under the gate electrode 22 is thick, the gate-drain capacitance is small and the switching speed is fast.

As this insulated gate semiconductor device 900, as a trench gate type semiconductor device in which a deposited insulating layer having a large thickness is formed at the bottom of the gate trench, there is one described in Patent Document 1, for example.
JP 2000-353805 A

  However, the conventional insulated gate semiconductor device 900 has the following problems. That is, the deposited insulating layer 23 in the gate trench 21 is formed by temporarily filling the inside of the gate trench 21 with an insulator (such as silicon oxide) by the CVD method and performing etch back on the insulator. Therefore, when the gate trench 21 is filled with an insulator, a seam is generated in the deposited insulating layer 23. When the insulating film in this state is etched back by wet etching, the etching proceeds rapidly at the seam portion. Then, as shown in FIG. 11, a wedge-shaped groove 233 is formed in the central portion of the deposited insulating layer 23. When the gate electrode 22 is formed on the deposited insulating layer 23 in this state, the gate material (polysilicon or the like) enters the wedge-shaped groove 233. Since the shape of the wedge-shaped groove 233 is not reproducible, it becomes difficult to form the gate electrode 22 having a stable shape.

  Furthermore, when the gate material enters the wedge-shaped groove 233, the depletion layer extends differently from the design when the gate voltage is switched off. As a result, a desired electric field distribution is not formed, and the breakdown voltage between the DSs is reduced. FIG. 12 shows the relationship between the depth of the wedge-shaped groove 233 and the breakdown voltage between the DSs. This simulation result also shows that the withstand voltage decreases as the depth of the wedge-shaped groove 233 increases.

  On the other hand, when etching back is performed by dry etching, etching can be performed uniformly in the thickness direction regardless of the presence or absence of seams. However, the wall surface of the gate trench 21 is damaged, and an insulating residue is generated in the gate trench 21. Even if the gate oxide film 24 is formed on such a wall surface, a high-quality oxide film and a clean interface cannot be obtained. Therefore, the device characteristics cannot be fully exhibited. As a result, it is necessary to perform wet etching in order to remove residues generated during dry etching.

  The present invention has been made to solve the problems of the conventional insulated gate semiconductor device described above. That is, an object of the present invention is to provide an insulated gate semiconductor device that suppresses a decrease in breakdown voltage due to the effect of seams and a method for manufacturing the same.

  An insulated gate semiconductor device made to solve this problem includes a trench portion, a first deposited insulating layer that is located in the trench portion and is formed by depositing a first type of insulator, and is formed in the trench portion. A conductive layer located above the first deposited insulating layer; and a second deposited insulating layer located at the center in the width direction of the trench portion and deposited with a second kind of insulating material. The lower end is surrounded by the first deposited insulating layer and the upper end is located above the upper end of the first deposited insulating layer.

  That is, in the insulated gate semiconductor device of the present invention, the second deposited insulating layer is provided in the center of the trench portion in the width direction within the trench portion. The second deposited insulating layer has a lower end surrounded by the first deposited insulating layer and an upper end located above the upper end of the first deposited insulating layer. That is, it is provided so as to straddle the first deposited insulating layer and the conductor layer. The presence of the second deposited insulating layer suppresses the generation of seams in the first deposited insulating layer. Therefore, a wedge-shaped groove is not generated when forming the first deposited insulating layer, and the shape of the conductor layer is stabilized. Therefore, a high breakdown voltage can be reliably achieved. Further, since the second deposited insulating layer is provided at the center in the width direction of the trench portion, the width for embedding the gate material is short. As a result, the flatness after the formation of the conductor layer is higher than that of the conventional insulated gate semiconductor device.

  Another insulated gate semiconductor device of the present invention includes a body region that is a first conductivity type semiconductor located on an upper surface side in a semiconductor substrate, a drift region that is in contact with the lower surface of the body region and is a second conductivity type semiconductor, , An insulated gate semiconductor device having a trench portion penetrating the body region from the upper surface of the semiconductor substrate, having a floating region surrounded by the drift region and being a first conductivity type semiconductor, A first deposited insulating layer formed by depositing a first type of insulator in the floating region; a conductor layer positioned above the first deposited insulating layer and facing the body region; And a second deposited insulating layer formed by depositing a second kind of insulator and being located at the center of the trench in the width direction, the upper end of the first deposited insulating layer being the upper end of the floating region Located in remote upward, second deposited dielectric layer has a lower end is surrounded by a first deposited insulating layer, an upper end is to be located above the upper end of the first deposited insulating layer.

  That is, in the insulated gate semiconductor device of this embodiment, a floating region that is a conductive semiconductor region different from the drift region is provided in the drift region. By this floating region, the maximum peak value of the electric field can be reduced. Further, since the second deposited insulating layer is provided, no seam is generated in the first deposited insulating layer. As a result, a high breakdown voltage can be achieved. In addition, since the withstand voltage is high, the on-resistance can be lowered by increasing the impurity concentration in the drift region.

  Further, it is better that the second type of insulator constituting the second deposited insulating layer has a lower etching rate than the first type of insulator constituting the first deposited insulating layer. That is, the first deposited insulating layer can be processed into a desired shape before the second deposited insulating layer is etched at the time of etching back the first type insulator when forming the first deposited insulating layer. Therefore, it is possible to reliably prevent the gate material from entering the first deposited insulating layer. Further, even if a seam exists in the second deposited insulating layer, the second type of insulator is hardly etched, so that the seam does not affect the shapes of the second deposited insulating layer and the first deposited insulating layer.

  The method for manufacturing an insulated gate semiconductor device according to the present invention includes a trench portion, a first deposited insulating layer that is located in the trench portion and deposits a first kind of insulator, and a first deposition layer in the trench portion. A method for manufacturing an insulated gate semiconductor device having a conductor layer located above an insulating layer, wherein a trench portion is formed from an upper surface of a semiconductor substrate, and the trench portion is formed in the trench portion forming step. Then, a first deposited insulating layer is formed on the surface of the trench portion by depositing a first type insulator so as to have a film thickness that is thinner than half the width of the trench portion. After forming the first deposited insulating layer in the insulator depositing step and the first insulator depositing step, the second deposited insulating layer is formed by depositing a second type of insulator on the first deposited insulating layer. Second insulator deposition step and second insulator After the second deposited insulating layer is formed in the product process, an etch back process is performed so that the layer thickness of the first deposited insulating layer in the trench becomes a predetermined thickness, and the first deposition is performed in the etch back process. And a conductor layer forming step of forming a conductor layer on the first deposited insulating layer after adjusting the thickness of the insulating layer.

  That is, after the trench portion is formed from the upper surface of the semiconductor substrate in the trench portion forming step, the first type insulator is deposited in the trench portion in the first insulator deposition step. When depositing the first type of insulator, the film thickness of the first deposited insulating layer is made thinner than half the width of the trench portion. That is, the opposing films of the first deposited insulating layer formed in the trench are prevented from contacting each other. Therefore, a gap remains in the trench after the first insulator deposition step. Then, a second type of insulator is deposited on the first deposited insulating layer in the second insulator deposition step. Thereby, the gap in the trench portion is filled with the second insulator. Then, the first deposited insulating layer and the second deposited insulating layer on the upper surface are removed in the etch back process, and the first deposited insulating layer is adjusted to have a predetermined layer thickness. At this time, since there is no seam in the first deposited insulating layer, no wedge-shaped groove is formed in the first deposited insulating layer. Therefore, the layer thickness of the first deposited insulating layer can be adjusted accurately. Then, a conductor layer is formed in the space after the etch back in the conductor layer forming step. Here, since the first deposited insulating layer does not have a wedge-shaped groove, a conductor layer having a stable shape can be formed. Therefore, a desired electric field distribution can be formed and a high breakdown voltage can be reliably achieved. In the conductor layer forming step, the conductor may be directly deposited in the trench portion, or the impurity may be diffused after a high-resistance semiconductor is once deposited.

  Further, in the method for manufacturing an insulated gate semiconductor device according to the present invention, the second insulator deposition step has a lower etching rate of etching performed in the etch-back step than the first type insulator. It is better to deposit an insulator. That is, since the etching rate of the second type insulator is small, the second deposited insulating layer is hardly etched back in the etch back process. Therefore, the first deposited insulating layer can be processed to a desired thickness before the second deposited insulating layer is removed. Therefore, the gate material does not enter the first deposited insulating layer, and a desired electric field distribution can be formed.

  In the method for manufacturing an insulated gate semiconductor device according to the present invention, the etch back performed in the etch back process is preferably performed by wet etching. That is, since no seam is generated in the first deposited insulating layer, the shape of the conductor layer is not affected even if the etch back is performed by wet etching. As a result, it is not necessary to carry out a process for taking measures against damages and residues necessary for dry etching, for example, a process for removing polysilicon residues. Therefore, the process is simple.

  The method for manufacturing an insulated gate semiconductor device according to the present invention includes an insulating film forming step of forming an insulating film on the surface of the trench portion after the etch back step and before the conductor layer forming step. Better. Thereby, an insulating film is formed on the wall surface of the trench portion where the wet etching is performed. That is, the gate insulating film can be formed on the wall surface with little damage. Therefore, the element characteristics can be fully exhibited.

  According to the present invention, the second deposited insulating layer is provided in the center in the width direction of the trench portion so that no seam is generated in the first deposited insulating layer. Therefore, the shape of the conductor layer, that is, the gate electrode is stabilized. Therefore, a desired electric field distribution can be formed, and a high breakdown voltage can be reliably achieved. Therefore, an insulated gate semiconductor device and a method for manufacturing the same that can suppress a decrease in breakdown voltage due to the effect of seams have been realized.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments embodying the present invention will be described below in detail with reference to the accompanying drawings. In the present embodiment, the present invention is applied to a power MOS that controls conduction between a drain and a source (between DS) by applying a voltage to an insulated gate.

[First embodiment]
An insulated gate semiconductor device 100 according to the first embodiment (hereinafter referred to as “semiconductor device 100”) has a structure shown in a sectional view of FIG. Note that in this specification, the whole of the starting substrate and the single crystal silicon portion formed by epitaxial growth on the starting substrate is referred to as a semiconductor substrate.

In the semiconductor device 100, an N ⁺ source region 31 is provided on the upper surface side in FIG. On the other hand, an N ⁺ drain region 11 is provided on the lower surface side. Between these, a P ⁻ body region 41 and an N ⁻ drift region 12 are provided in this order from the upper surface side. The total thickness of the P ⁻ body region 41 and the N ⁻ drift region 12 (hereinafter referred to as “epitaxial layer”) is approximately 5.5 μm (of which the thickness of the P ⁻ body region 41 is approximately 1.2 μm).

In addition, a gate trench 21 is formed by digging a part of the upper surface side of the semiconductor substrate. Gate trench 21 has a depth of approximately 2.3 μm and penetrates P ⁻ body region 41. A deposited insulating layer 23 is formed on the bottom of the gate trench 21 by depositing an insulator. Specifically, in the deposited insulating layer 23 of this embodiment, silicon oxide is deposited from the bottom of the gate trench 21 to a height of about 1.1 μm. Further, a gate electrode 22 is formed on the deposited insulating layer 23 by depositing polysilicon. The lower end of gate electrode 22 is located below the lower surface of P ⁻ body region 41. The gate electrode 22 faces the N ⁺ source region 31 and the P ⁻ body region 41 of the semiconductor substrate through a gate insulating film 24 formed on the wall surface of the gate trench 21. That is, the gate electrode 22 is insulated from the N ⁺ source region 31 and the P ⁻ body region 41 by the gate insulating film 24.

  A deposited insulating film 231 is formed in the gate trench 21 at the center in the width direction in FIG. The deposited insulating film 231 is made of an insulator different from the insulator constituting the deposited insulating layer 23. Specifically, the deposited insulating film 231 of this embodiment is formed by depositing silicon nitride. The deposited insulating film 231 has an upper end located in the gate electrode 22 and a lower end located in the deposited insulating layer 23. That is, it is provided so as to straddle the deposited insulating layer 23 and the gate electrode 22.

In the semiconductor device 100 having such a structure, a channel effect is generated in the P ⁻ body region 41 by applying a voltage to the gate electrode 22, thereby controlling conduction between the N ⁺ source region 31 and the N ⁺ drain region 11. doing.

Next, a manufacturing process of the semiconductor device 100 shown in FIG. 1 will be described with reference to FIGS. First, an N ⁻ type silicon layer is formed on the N ⁺ substrate to be the N ⁺ drain region 11 by epitaxial growth. This N ⁻ -type silicon layer (epitaxial layer) is a portion that becomes each of the N ⁻ drift region 12, the P ⁻ body region 41, and the N ⁺ source region 31. Then, a P ⁻ body region 41 and an N ⁺ source region 31 are formed by subsequent ion implantation or the like. Thus, a semiconductor substrate (see FIG. 2) having an epitaxial layer on the N ⁺ drain region 11 is produced.

Next, as shown in FIG. 3, a gate trench 21 is formed which penetrates the P ⁻ body region 41 and reaches the N ⁻ drift region 12 by dry etching. Note that sacrificial oxidation treatment and CDE (chemical dry etching) are performed on the side wall of the gate trench 21 for the purpose of removing damage caused by dry etching. The width of the gate trench 21 after these processes is about 0.52 μm.

  Next, as shown in FIG. 4, the insulating film 23 is embedded in the gate trench 21 by the CVD method. In this embodiment, a silicon oxide film (hereinafter referred to as “oxide film 23”) is embedded. The thickness of the buried oxide film 23 is thinner than half the width of the gate trench 21. Therefore, the oxide films facing each other in the gate trench 21 are not in contact with each other. That is, the film is formed not to completely fill the gate trench 21 but to leave a gap 232. Therefore, the thickness of the oxide film 23 is uniform in each part. Specifically, an appropriate thickness of the oxide film 23 in this embodiment is about 0.15 μm. Accordingly, a gap 232 having a width of about 2.2 μm remains at the center of the gate trench 21. Note that before the oxide film is embedded, an oxidation process before embedding may be performed in order to eliminate the influence of the interface state.

  Next, as shown in FIG. 5, the insulating film 231 is buried in the gap 232 of the oxide film 23 by the CVD method. The insulating film 231 is an insulator having an etching rate lower than that of the oxide film 23. In this embodiment, a silicon nitride film (hereinafter referred to as “nitride film 231”) is embedded. As a result, the gap 232 in the gate trench 21 is filled with the nitride film 231. Further, in this step, the film is formed until the upper surface is covered with the nitride film 231. Specifically, the appropriate thickness of the nitride film 231 formed on the upper surface in this embodiment is about 0.15 μm.

  Next, as shown in FIG. 6, wet etching with BHF (buffered hydrofluoric acid) is performed on the semiconductor substrate on which the nitride film 231 is deposited. Thereby, a part of the nitride film 231 and the oxide film 23 is removed (etched back), and a space for forming the gate electrode 22 is secured. The remaining oxide film 23 becomes the insulating deposition layer 23 of the semiconductor device 100 shown in FIG. Since the depth of the gate electrode 22 is required to be about 1.2 μm, the oxide film 23 of about 1.35 μm is removed from the upper surface by this process. Here, the nitride film 231 has an etching rate by BHF of only about 1/60 as compared with the oxide film 23. Therefore, the nitride film 231 is removed only by about 23 nm before the oxide film 23 is removed by about 1.35 μm. That is, since the etching rate of the nitride film 231 is considerably smaller than the etching rate of the oxide film 23, the nitride film 231 exists in the gate trench 21 in a shape protruding from the deposited insulating layer 23 after wet etching. It becomes.

  Strictly speaking, a seam is generated at the center of the nitride film 231. However, even if the surface of the nitride film 231 is etched to a thickness of about 23 nm, its shape is hardly affected. On the other hand, since the oxide film 23 has no seam, the etching proceeds uniformly in the thickness direction. Therefore, etch back can be performed evenly to a desired position.

  Next, as shown in FIG. 7, an oxide film 24 is formed on the upper surface of the semiconductor substrate and the wall surface of the gate trench 21 by thermal oxidation. This becomes the gate oxide film 24. Next, as shown in FIG. 8, a gate material 22 is deposited in a space secured by etch back. Specifically, in this embodiment, polysilicon is deposited, and this becomes the gate electrode 22. As a method for forming the gate electrode 22, there is a method in which a conductor is directly deposited in the gate trench 21, and a method in which impurities are diffused after a high-resistance semiconductor is once deposited. Finally, the deposited gate material 22 is etched, and then the source electrode and the drain electrode are formed, whereby the insulated gate semiconductor device as shown in FIG. 1, that is, the semiconductor device 100 is manufactured.

  The semiconductor device 100 of this embodiment has the following characteristics compared to the insulated gate semiconductor device 900 (see FIG. 10) that does not include the nitride film 231 provided in the gate trench 21. Have. That is, in the semiconductor device 100 of this embodiment, the gate trench 21 is not completely filled with the oxide film 23, so that no seam is generated in the oxide film 23. Therefore, even if wet etching is performed on the oxide film 23, a wedge-shaped groove is not formed. Therefore, a gate electrode having a stable shape can be formed. Further, a nitride film 231 having an etching rate lower than that of the oxide film 23 is used in a portion where the seam is generated. Therefore, even if wet etching is performed, the nitride film 231 is hardly removed, and remains in the central portion of the gate trench 21 in the width direction. Therefore, the gate material does not enter the deposited insulating layer 23. Therefore, a desired electric field distribution is obtained when the gate voltage is switched off, and a high breakdown voltage can be achieved. Note that although the nitride film 231 remains in the central portion of the gate electrode 22, it is not involved in the portion that causes the channel effect and does not affect the gate characteristics of the gate electrode 22.

  As another advantage, in the manufacturing process of this embodiment, etch back can be performed only by wet etching. In a conventional semiconductor device manufacturing process, etch back is sometimes performed by dry etching as a countermeasure against a wedge-shaped groove. However, when dry etching is performed, processes such as damage countermeasures and deposition countermeasures are required. On the other hand, in the manufacturing process of this embodiment, since no seam is generated in the oxide film 23, it is possible to perform etch back only by wet etching. Therefore, the manufacturing process is simple.

  In the semiconductor device 100 of this embodiment, the nitride film 231 is in the center of the gate trench 21. Therefore, the film thickness necessary for embedding the gate material 22 is thinner than that in the case where the nitride film 231 is not provided. Thereby, the thickness of the gate material 22 deposited on the upper surface of the semiconductor substrate is also thin, and the etching time of the dry etching process for patterning the gate material 22 can be shortened. As a result, damage due to dry etching can be reduced, and polysilicon residues can be reduced. Further, since the gate material 22 deposited on the upper surface of the semiconductor substrate is thin, it is advantageous for fine processing as compared with the conventional semiconductor device.

  Further, in the semiconductor device 100 of this embodiment, since the nitride film 231 is at the center in the width direction in the gate trench 21, the width for embedding the gate material 22 can be shorter than that of the conventional semiconductor device. Specifically, in the conventional structure, it is 0.52 μm, which is equal to the trench width, but in the structure of this embodiment, it may be about 0.20 μm because the nitride film 231 exists. Therefore, the flatness after the conductor is deposited is higher than that of the conventional semiconductor device.

  Further, in the step of diffusing impurities into the gate electrode 22, the nitride film 231 is present in the central portion of the gate trench 21, so that it is not diffused in the central portion where impurity diffusion is unnecessary. That is, it can be reliably diffused to the vicinity of the interface with the gate oxide film 24 where impurity diffusion is required. As a result, the impurity diffusion time can be shortened. In addition, since the semiconductor device 100 of this embodiment has a thin epitaxial layer and a high impurity concentration, it is necessary to reduce the thermal load, and the impurity diffusion time can be shortened.

  Further, since the flatness is improved, the interlayer insulating film can be made thin. Further, since it is flat, it is not necessary to perform etching for a long time to etch the interlayer insulating film that has entered the groove portion by dry etching of the interlayer insulating film. Further, since the interlayer insulating film is a thin film, the time for dry etching of the contact can be shortened. Further, since the interlayer insulating film is a thin film, contact resistance can be suppressed. In addition, since the interlayer insulating film is a thin film, the embedding property of the upper aluminum layer is improved. For this reason, in the conventional process, the shoulder portion of the contact hole is cut to improve the burying property of the aluminum, but this process becomes unnecessary. As described above, the number of processes can be reduced and the reliability can be improved.

[Second form]
An insulated gate semiconductor device 200 according to the second embodiment (hereinafter referred to as “semiconductor device 200”) has a structure shown in a sectional view of FIG. A feature of the semiconductor device 200 of this embodiment is that a P floating region 51 is provided in the N ⁻ drift region 12. In FIG. 9, components having the same symbols as those of the semiconductor device 100 shown in FIG. 1 have the same functions as those components.

In the semiconductor device 200 of this embodiment, a P floating region 51 surrounded by the N ⁻ drift region 12 is formed. The cross section of the P floating region 51 has a substantially circular shape with a radius of 0.6 μm centered slightly below (approximately 0.2 μm) from the bottom of the gate trench 21 as shown in the cross sectional view of FIG. Each gate trench 21 is formed at a pitch of about 3.0 μm. Therefore, there is a sufficient space between the adjacent P floating regions 51 and 51. Therefore, in the ON state, the presence of the P floating region 51 does not hinder the drain current. Further, the radius (approximately 0.6 μm) of the P floating region 51 is equal to or less than ½ of the thickness (approximately 1.1 μm) of the deposited insulating layer 23. Therefore, the upper end of the deposited insulating layer 23 is located above the upper end of the P floating region 51. Therefore, the gate electrode 22 deposited on the deposited insulating layer 23 and the P floating region 51 do not face each other.

  A deposited insulating film 231, which is an insulator different from the deposited insulating layer 23, is formed in the gate trench 21. Specifically, the deposited insulating film 231 is formed by depositing silicon nitride at the center position of the gate trench 21 as in the first embodiment. That is, also in the semiconductor device 200 of this embodiment, an insulator having a low etching rate is used in the seam-producing portion, as in the semiconductor device 100 of the first embodiment. Therefore, formation of a wedge-shaped groove can be suppressed and the shape of the gate electrode 22 can be stabilized.

In the semiconductor device 200 of this embodiment, when the gate voltage is switched off, a depletion layer spreads from the PN junction portion between the P body region 41 and the N ⁻ drift region 12 toward the N ⁺ drain region 11. A depletion layer also spreads from the lower end of the P floating region 51 toward the N ⁺ drain region 11. Thereby, the peak value of the electric field can be relaxed, and a high breakdown voltage between the DSs can be achieved.

Next, a manufacturing procedure of the semiconductor device 200 will be described. First, an N ⁻ type silicon layer is formed on the N ⁺ substrate to be the N ⁺ drain region 11 by epitaxial growth. Then, the P ⁻ body region 41 and the N ⁺ source region 31 are formed by subsequent ion implantation or the like.

Next, a gate trench 21 that penetrates through the P ⁻ body region 41 and reaches the bottom of the N ⁻ drift region 12 is formed. Thereafter, an oxide film having a thickness of about 50 nm is formed on the wall surface of the gate trench 21 by performing thermal oxidation treatment. Next, ion implantation is performed from the bottom surface of the gate trench 21. The reason why the ion implantation is performed after the oxide film is formed is to prevent the influence of the ion implantation from remaining on the side wall of each trench. After the ion implantation, the oxide film in the gate trench 21 is removed.

  Next, an insulator (silicon oxide or the like) 23 is deposited in the gate trench 21 by the CVD method. At this time, deposition is performed up to a predetermined position so as to leave a gap 232 as in the semiconductor device 100 of the first embodiment. Further, an insulator (silicon nitride or the like) 231 filling the gap 232 is deposited by the CVD method. Thereafter, a thermal diffusion process is performed in combination with the baking of the insulator 23 and the formation of the P floating region 51. Thereby, the P floating region 51 is formed.

  Next, a part of the insulator 23 and a part of the insulating film 231 are removed by etching the semiconductor substrate on which the insulator is deposited. That is, the insulator 23 and the insulating film 231 are etched back. Thereby, a space for forming the gate electrode 22 is secured. At this time, the insulator 23 can be etched to a desired position while the insulating layer 231 in the gate trench 21 is hardly etched. Next, an oxide film 24 is formed on the upper surface of the semiconductor substrate and the wall surface of the gate trench 21 by thermal oxidation. This becomes the gate oxide film 24. Then, a gate electrode 22 is formed by depositing a conductor (polysilicon or the like) in the space secured in the previous step. Finally, by forming a source electrode and a drain electrode, an insulated gate semiconductor device as shown in FIG. 9, that is, a semiconductor device 200 is manufactured.

  As described above in detail, in the semiconductor device 100 of the first embodiment, after the gate trench 21 is provided, the oxide film 23 is deposited on the surface thereof by the CVD method. At this time, the thickness of the oxide film 23 is made thinner than half the width of the gate trench 21. That is, the gate trench 21 is not completely filled with the oxide film 23 but is deposited with a predetermined thickness so as to leave a gap 232. Thereafter, the gap 232 is filled with the nitride film 231. That is, insulators having different etching rates are deposited in the gate trenches 21, respectively. At this time, the oxide film 23 has no seam and the nitride film 231 has a seam. Thereafter, the oxide film 23 and the nitride film 231 are etched back. Since the oxide film 23 is etched back without a seam, no wedge-shaped groove is formed. Therefore, the oxide film 23 can be uniformly etched in the thickness direction. Therefore, the shape of the gate electrode 22 is stabilized. Therefore, an insulated gate semiconductor device and a method for manufacturing the same that can suppress a decrease in breakdown voltage due to the effect of seams have been realized.

  The etching rate of silicon nitride by BHF is about 1/60 of that of silicon oxide. Therefore, the etching of the oxide film 23 proceeds first, and the oxide film 23 can be processed into a desired shape while the nitride film 231 is hardly etched. Therefore, the nitride film 231 protrudes from the silicon oxide 23 and remains in the gate trench 21. The gate trench 21 in this state is filled with polysilicon. Therefore, the gate material does not enter the deposited insulating layer 23, and a desired electric field distribution can be formed. Further, the nitride film 231 remaining in the gate trench 21 reduces the thickness of the gate material 22 deposited on the upper surface of the semiconductor substrate. Further, since no seam is generated in the oxide film 23, the etch back can be performed only by wet etching. Therefore, damage to the side wall of the gate trench 21 is small, and the manufacturing process can be simplified.

In the semiconductor device 200 of the second embodiment, the P floating region 51 is formed below the gate trench 21. By this P floating region 51, the maximum peak value of the electric field can be relaxed and a high breakdown voltage can be achieved. Further, since the withstand voltage is high, the on-resistance can be lowered by increasing the impurity concentration of the N ⁻ drift region 12.

  Note that this embodiment is merely an example and does not limit the present invention. Therefore, the present invention can naturally be improved and modified in various ways without departing from the gist thereof. For example, for each semiconductor region, P-type and N-type may be interchanged. Further, the gate insulating film 24 is not limited to an oxide film, and may be another type of insulating film such as a nitride film or a composite film. Also, the semiconductor is not limited to silicon, but may be other types of semiconductors (SiC, GaN, GaAs, etc.). The insulated gate semiconductor device of the embodiment can also be applied to a conductivity modulation type power MOS using a P type substrate.

It is sectional drawing which shows the structure of the insulated gate semiconductor device which concerns on a 1st form. It is a figure (semiconductor substrate) which shows the manufacturing process of an insulated gate semiconductor device. It is a figure (trench formation) which shows the manufacturing process of an insulated gate semiconductor device. It is a figure (oxide film CVD) which shows the manufacturing process of an insulated gate semiconductor device. It is a figure (nitride film CVD) which shows the manufacturing process of an insulated gate semiconductor device. It is a figure (etch-back) which shows the manufacturing process of an insulated gate semiconductor device. It is a figure (gate oxide film formation) which shows the manufacturing process of an insulated gate semiconductor device. It is a figure (conductor filling) which shows the manufacturing process of an insulated gate semiconductor device. It is sectional drawing which shows the structure of the insulated gate semiconductor device which concerns on a 2nd form. It is sectional drawing which shows the structure of the conventional insulated gate semiconductor device. It is sectional drawing which shows the deposited insulating layer etched in the wedge shape. It is a graph which shows the relationship between the depth of a wedge-shaped groove | channel, and the withstand pressure | voltage between drain-sources.

Explanation of symbols

11 N ⁺ drain region 12 N ⁻ drift region (drift region)
21 trench (trench part)
22 Gate electrode (conductor layer)
23 Deposited insulating layer (first deposited insulating layer)
231 Deposited insulating film (second deposited insulating layer)
232 oxide film gap 233 oxide film wedge-shaped groove 24 gate insulating film 31 N ⁺ source region 41 P ⁻ body region (body region)
51 P floating area (floating area)
100 Insulated gate semiconductor device

Claims (8)

A trench,
A first deposited insulating layer located in the trench and formed by depositing a first type of insulator;
A conductor layer located in the trench and above the first deposited insulating layer;
A second deposited insulating layer that is located at the center in the width direction of the trench and is formed by depositing a second type of insulator;
2. The insulated gate semiconductor device according to claim 1, wherein the second deposited insulating layer has a lower end surrounded by the first deposited insulating layer and an upper end located above the upper end of the first deposited insulating layer. A body region that is a first conductivity type semiconductor located on the upper surface side in the semiconductor substrate, a drift region that is in contact with the lower surface of the body region and is a second conductivity type semiconductor, and a trench that penetrates the body region from the upper surface of the semiconductor substrate In an insulated gate semiconductor device having a portion,
A floating region surrounded by the drift region and being a first conductivity type semiconductor;
The bottom of the trench is located in the floating region;
In the trench part,
A first deposited insulating layer formed by depositing a first type of insulator;
A conductor layer located above the first deposited insulating layer and facing the body region;
A second deposited insulating layer formed at the center of the trench in the width direction and having a second type of insulator deposited thereon;
An upper end of the first deposited insulating layer is located above an upper end of the floating region;
2. The insulated gate semiconductor device according to claim 1, wherein the second deposited insulating layer has a lower end surrounded by the first deposited insulating layer and an upper end located above the upper end of the first deposited insulating layer. In the insulated gate semiconductor device according to claim 1 or 2,
An insulated gate semiconductor device characterized in that the second kind of insulator constituting the second deposited insulating layer has a lower etching rate than the first kind of insulator constituting the first deposited insulating layer. . A trench portion; a first deposited insulating layer that is located in the trench portion and deposits a first type of insulator; and a conductor layer that is located in the trench portion and above the first deposited insulating layer. In a method of manufacturing an insulated gate semiconductor device,
Forming a trench portion from the upper surface of the semiconductor substrate;
After forming the trench part in the trench part forming step, depositing a first type insulator on the surface of the trench part so that the film thickness is thinner than half the width of the trench part. A first insulator deposition step of forming a first deposited insulating layer in
A second insulator forming a second deposited insulating layer by depositing a second type of insulator on the first deposited insulating layer after forming the first deposited insulating layer in the first insulator depositing step. A deposition process;
An etch back step of performing etch back so that the thickness of the first deposited insulating layer in the trench portion becomes a predetermined thickness after forming the second deposited insulating layer in the second insulator depositing step;
And a conductor layer forming step of forming a conductor layer on the first deposited insulating layer after adjusting the thickness of the first deposited insulating layer in the etch back step. Production method. In the manufacturing method of the insulated gate semiconductor device according to claim 4,
In the second insulator deposition step, the second type insulator having a lower etching rate in the etching performed in the etch back step than that of the first type insulator is deposited. Device manufacturing method. In the manufacturing method of the insulated gate semiconductor device according to claim 4 or 5,
The method of manufacturing an insulated gate semiconductor device, wherein the etch back performed in the etch back process is performed by wet etching. In the manufacturing method of the insulated gate semiconductor device according to claim 6,
A method of manufacturing an insulated gate semiconductor device, comprising: an insulating film forming step of forming an insulating film on a surface of the trench portion after the etch back step and before the conductor layer forming step. In the manufacturing method of the insulated gate semiconductor device as described in any one of Claims 4-7,
Floating region formation for forming a floating region by implanting impurities from the bottom of the trench portion formed in the trench portion forming step after the trench portion forming step and before the first insulator deposition step A method of manufacturing an insulated gate semiconductor device.

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