JP2005250736A - Power control device - Google Patents

Abstract

A power control apparatus capable of shortening a transition time when switching a power supply voltage is provided.
Switching between power supply voltages V _DDL (1, 2 V) and V _DDH (2.0 V) to be supplied to an internal circuit 12 in a processor chip 11 is performed by a PMOS transistor 13 provided in the processor chip 11, 14 for each chip. The transition times of the power supply voltages V _DDL and V _DDH are proportional to the capacity of the power supply line 15 instead of the external decoupling capacitors C _DL and _CDH . Since the capacitance of the power supply line 15 is significantly smaller than the external decoupling capacitances C _DL and C _DH , the transition time of the power supply voltages V _DDL and V _DDH can be greatly shortened.
[Selection] Figure 2

Description

  The present invention relates to a power control apparatus that performs power control of a device such as a mobile phone or a personal computer.

As such power control, for example, a DVS (Dynamic Voltage Scaling) technique (for example, see Non-Patent Document 1) and a V _DD -Hopping technique (for example, see Patent Document 1) have been proposed.

  DVS technology is a technology that adaptively changes the power supply voltage and operating frequency according to the processor load, Intel Pentium (registered trademark) III Speed Step technology, Transmeta Crusoe Long Run technology, AMD K6 Power Now technology Etc. are adopted.

In the DVS technique, as shown in FIG. 1A, a power supply voltage V _DD of an internal circuit (not shown) of the processor chip 1 is changed by a DC / DC converter 2 outside the processor chip 1 (in this case, 1.2V V _DDL or V _{DDH of} 2.0 V), and at the same time, the operating frequency f of the internal circuit (not shown) is changed by a clock circuit (not shown) in the processor chip 1.

On the other hand, according to the V _DD -Hopping technology, for example, two kinds of power supply voltages V _DDL (1.2 V) and V _DDH (2.0 V) can be switched by PMOS transistors 3 and 4 as shown in FIG. 1B. . In this case, the voltage of the ground line GND can be switched by the NMOS switch.
Japanese Patent No. 3138737 (Claim 1) Trevor Pering et al. “The simulation and evaluating of dynamic voltage scaling algorithms”, Proceeding of the 1998 international Symposium on low power electronics and design, pp.76-81, Aug., 1998

However, when the power supply voltage V _DD is changed from the outside of the processor chips 1 and 5 as in the conventional DVS technology and V _DD -Hopping technology, it is about several tens μF connected to the power supply pins of the processor chips 1 and 5 due to the relatively large external decoupling capacitor C _D, (specifically several hundreds .mu.s about several tens .mu.s) power transition time of the voltage V _DD is relatively long is disadvantageously.

While the power supply voltage V _DD processor chip 1, 5 accompanied by fluctuations in the power supply voltage V _DD during the transition can also be operated, in the case of industrial products are also guaranteed operation during the transition of the power supply voltage V _DD Because it is necessary, it is necessary to conduct a shipping test on this separately. However, in this case, the product unit price increases because the test process increases. In fact without such testing, but during the transition of the power supply voltage V _DD is best to stop the processor chip 1, 5, because during the transition of the power supply voltage V _DD is a processor chip 1, 5 is stopped, Performance is degraded. As a result, it is desired to shorten the transition time of the power supply voltage V _DD .

  Further, in the conventional power control, since the voltage of the entire processor chips 1 and 5 is changed at a time, it is very difficult to reduce the power consumption spatially and finely inside the processor chips 1 and 5.

  Furthermore, the circuit scales of the processor chips 1 and 5 are increasing year by year, and it is desired that the power consumption be reduced spatially and finely.

  The objective of this invention is providing the power control apparatus which can shorten the transition time at the time of switching of a power supply voltage.

  Another object of the present invention is to provide a power control device capable of reducing spatially fine power consumption inside a processor chip.

The power control device according to the present invention comprises:
Comprising a processor chip and power supply voltage generating means for generating a variable power supply voltage to be supplied to the processor chip,
The processor chip includes power supply voltage determining means for selecting one of power supply voltages generated by the power supply voltage generating means.

Other power control devices according to the present invention include:
Comprising a processor chip and power supply voltage generating means for generating a variable power supply voltage to be supplied to the processor chip,
The processor chip has power supply voltage determining means for selecting one of the power supply voltages generated by the power supply voltage generating means for each block of the processor chip.

Other power control devices according to the present invention include:
Comprising a programmable chip and power supply voltage generating means for generating a variable power supply voltage to be supplied to the programmable chip,
The programmable chip has power supply voltage determining means for selecting one of the power supply voltages generated by the power supply voltage generating means for each configurable logic block of the programmable chip.

  According to the power control device of the present invention, the transition time of the power supply voltage is not proportional to the external decoupling capacitance connected to the power supply pin of the processor chip, and the capacitance of the wiring between the power supply voltage generating means and the processor chip Is proportional to Since the capacity of this wiring is significantly smaller than the external decoupling capacity, the transition time of the power supply voltage can be greatly shortened.

  In order to achieve better power control, the power supply voltage is generated based on a variable clock frequency that controls the operation of the processor chip, and / or the power supply voltage is in standby during operation of the processor chip. It is preferable to change with time.

  According to another power control apparatus according to the present invention, since the power supply voltage is set in units of blocks, it is possible to achieve a spatially fine power consumption reduction in the processor chip. By setting the power supply voltage in units of blocks, the capacity of the wiring between the power supply voltage generating means and the block can be subdivided, and the transition time of the power supply voltage can be further shortened. Note that when the power supply voltage is set in units of blocks, the configuration can be simplified by using a voltage dropper type power supply voltage conversion circuit.

  In order to perform power control more satisfactorily, the signal amplitude between the blocks is selected to be the maximum or the minimum of the power supply voltage supplied for each block, and each of the blocks has a level converter, Preferably, the power supply voltage is generated based on a variable clock frequency that controls the operation of each of the blocks, and / or the power supply voltage varies between the operation of each block and the standby time.

  The present invention can be applied not only to the case of providing a processor chip but also to the case of providing a programmable chip such as an FPGA (Field Programmable Gate Array). In this case, the power supply voltage can be changed for each of several collectible configurable logic blocks (CLB: Configurable Logic Block), and a level converter is not required in the collective configurable logic block.

Embodiments of a power control apparatus according to the present invention will be described in detail with reference to the drawings.
FIG. 2 is a diagram showing a first embodiment of a power control apparatus according to the present invention. In the present embodiment, switching of the power supply voltages V _DDL (1, 2 V) and V _DDH (2.0 V) to be supplied to the internal circuit 12 in the processor chip 11 is performed by the PMOS transistor 13 provided in the processor chip 11. , 14 for each chip.

According to the present embodiment, the transition times of the power supply voltages V _DDL and V _DDH are proportional to the capacity of the power supply line 15 instead of the external decoupling capacitors _CDL and _CDH . Since the capacitance of the power supply line 15 is significantly smaller than the external decoupling capacitances C _DL and C _DH , the transition time of the power supply voltages V _DDL and V _DDH can be greatly shortened. The power supply voltage _{V DDL,} in order to avoid a rapid drop in the power supply voltage at the start transition of _{V DDH} supply voltage _{V DDL,} control as PMOS transistors 13 and 14 both at the transition beginning of the _{V DDH} is not turned off at the same time I do. Further, both PMOS transistors 13 and 14 may be turned off when the internal circuit 12 is on standby.

FIG. 3 is a diagram showing a second embodiment of the power control apparatus according to the present invention. In the present embodiment, switching of the power supply voltages V _DDL (1, 2 V) and V _DDH (2.0 V) to be supplied to the internal circuit blocks 22-1 to 22-n in the processor chip 21 is performed in the processor chip 21. PMOS transistors 23-3-1, 23-3-2,. . . , 23-n-1, 23-n-2 are performed in units of internal circuit blocks.

According to the present embodiment, since the power supply voltage is set in units of internal circuit blocks, spatially fine power consumption can be reduced within the processor chip. That is, the power supply voltages V _DDL and V _DDH of the processor elements and function blocks in the processor chip 21 can be arbitrarily changed. Further, by blocking the internal circuit, the capacity of the power supply line can be subdivided, and the transition time of the power supply voltages V _DDL and V _DDH can be further shortened. The power supply voltage _{V DDL,} in order to avoid a rapid drop in the power supply voltage at the start transition of _{V DDH} supply voltage _{V DDL,} both PMOS transistor when the transition start of _{V DDH} 23-3-1,23-3- 2,. . . , 23-n-1, 23-n-2 are controlled so as not to be turned off simultaneously. When the internal circuit blocks 22-1 to 22-n are on standby, both PMOS transistors 23-3-1, 23-3-2,. . . , 23-n-1, 23-n-2 may be turned off.

  Alternatively, a plurality of power supply lines of three or more may be prepared and switching may be performed using a PMOS transistor. When the power supply voltage is set for each internal circuit block as in this embodiment, the power supply wiring can be simplified by using a voltage dropper type power supply voltage conversion circuit as described later. An inductance type DC-DC converter can also be used from the viewpoint of efficiency.

  FIG. 4 is a diagram showing a third embodiment of the power control apparatus according to the present invention. This embodiment uses a voltage dropper type power supply voltage conversion circuit, and the switching of the power supply voltage to be supplied to the internal circuit blocks 32-1 to 32-n in the processor chip 31 is performed in the processor chip 31. PMOS transistors 33-3, 33-4,. . . , 33-n-1, 33-n are performed in units of internal circuit blocks.

According to the present embodiment, the structure is the same as that of MTCMOS with only one type of power supply line, and PMOS transistors 33-3, 33-4,. . . , 33-n-1, 33-n gate voltages V _G3 , V _G4 ,. . . , V _Gn−1 , V _Gn can be supplied to the internal circuit blocks 32-1 to 32-n, respectively. In the present embodiment, since a plurality of PMOS transistors are not required per a plurality of voltage sources and internal circuit blocks, the area of the processor chip 31 can be reduced.

  In the present embodiment, PMOS transistors 33-3, 33-4,. . . , 33-n-1, 33-n are not used as switches, but the power supply voltages of the internal circuit blocks 32-1 to 32-n are adjusted by controlling the gate voltages thereof. The mechanism is shown in FIG. 5A. In this case, the local power supply line 43 is constantly monitored, and the gate voltage of the PMOS transistor 42 is feedback controlled. Similarly, the current flowing through the local power supply line 43 may be monitored.

Further, as shown in FIG. 5B, when there are only two types of power supply voltages and the current consumption at the time of the low power supply voltage is known in advance, the PMOS transistor 51 is configured to supply this current consumption at the time of the low power supply voltage. The gate voltage is controlled to V _GL . On the other hand, when the power supply voltage is high, the PMOS transistor 51 is completely turned on by setting the gate voltage of the PMOS transistor 51 to GND.

  Since the power supply voltages are different for each internal circuit block, the signal amplitude between the internal circuit blocks needs to be unified in advance. FIG. 6A shows a form in which the signal amplitude is not unified. In this case, if the internal circuit block a outputs a signal to the internal circuit block b with an arbitrary amplitude, a problem of signal integrity such as coupling with other wiring is likely to occur.

  In FIG. 6B, a signal is output with the minimum amplitude among the plurality of power supply voltages. In this case, the amplitudes of all signals are unified with a minimum amplitude. A level down converter is required for signal output, and a level up converter is required for signal input. In a programmable chip such as an FPGA described later that has many regular wirings, it is easy to separate the wiring in the internal circuit block and the wiring between the internal circuit blocks, and signal integrity problems such as coupling noise are unlikely to occur. ,It is valid. The configuration shown in FIG. 6B is effective in reducing power consumption due to signal wiring.

  In FIG. 6C, a signal is output with the maximum amplitude among the plurality of power supply voltages. In this case, a level up converter is required for signal output. The configuration shown in FIG. 6C has less signal integrity problems such as coupling noise because the long wiring between the internal circuit blocks has a high amplitude, and is effective for complex wiring such as a processor chip.

Simultaneously with the control of the power supply voltage, the control of the operating frequency becomes important. The operating frequency is different for each internal circuit block. If the maximum operating frequency _{f max} and _{f max} / 2 is required as V _DD -Hopping art, as shown in FIG. 7A, either of _{f max} and _{f max} / 2, which is distributed throughout the chip Is selected for each internal circuit block.

When only f _max is distributed to the entire chip, a frequency divider is required for each internal circuit block as shown in FIG. 7B. For synchronization of the internal circuit blocks between the signals, since there should be no clock skew, a mechanism for adjusting the skew of f _max and f _{max / 2} is required. In this case, the skew is adjusted by making the delay from the clock of the frequency divider to Q the same as the delay of the delay element.

FIG. 8 is a diagram showing a fourth embodiment of the power control apparatus according to the present invention. In the present embodiment, switching of the power supply voltages V _DDL (1, 2 V) and V _DDH (2.0 V) to be supplied to the configurable logic blocks (CLB) 62-1 to 62-n in the programmable chip 61 is performed. , PMOS transistors 63-3-1, 63-3-2,. . . , 63-n-1-1, 63-n-1-2.

  Further, since the configurable logic blocks 62-1 to 62-n have substantially the same configuration, for example, as shown in the present embodiment, configurable logic blocks 62-2, 62-4,. . . 62-n can be controlled using only the PMOS transistors 63-4-1 and 63-4-2.

  FIG. 9 is a diagram showing a fifth embodiment of the power control apparatus according to the present invention. The present embodiment uses a voltage dropper type power supply voltage conversion circuit, and switching of the power supply voltage to be supplied to the configurable logic blocks 72-1 to 72-n in the programmable chip 71 is programmable chips. PMOS transistors 73-3, 73-4,. . . , 73-n-1 is performed in units of logical blocks that can be configured.

According to the present embodiment, the structure is the same as that of MTCMOS with only one type of power supply line, and PMOS transistors 73-3, 73-4,. . . 73-n-1 gate voltages V _G3 , V _G4,. . . , V _Gn−1 , a plurality of types of power supply voltages can be supplied to the configurable logic blocks 72-1 to 72-n, respectively. In the present embodiment, since a plurality of PMOS transistors are not required for each of a plurality of voltage sources and configurable logic blocks, the area of the programmable chip 71 can be reduced.

  Further, since the configurable logic blocks 72-1 to 72-n have substantially the same configuration, for example, as shown in the present embodiment, configurable logic blocks 72-4,. . . 72-n can be controlled using only the PMOS transistor 73-4.

FIG. 10 is a diagram for explaining the effect of the present invention. In FIG. 10, the transition time of the power supply voltage V _DD in the present invention is less than 4 ns. As described above, the transition time of less than 4 ns in the present invention is significantly reduced compared to the conventional transition time of several tens to several hundreds of μs.

The present invention is not limited to the above-described embodiment, and many changes and modifications can be made.
For example, in the above embodiment, a PMOS transistor is used as an active element, but other active elements such as an NMOS transistor can be used.

  Further, the circuit shown in FIG. 6B can be configured as shown in FIG.

Further, the level up converter shown in FIG. 11 may be a bypass level converter as shown in FIG. When the input internal circuit block of FIG. 11 is operated with the low power supply voltage V _DDL , it is not necessary for the low-amplitude input signal IN to pass through the level-up converter unit 81 of FIG. Good. In this case, the delay becomes even faster.

It is a figure which shows the conventional power control apparatus. It is a figure which shows 1st Embodiment of the power control apparatus by this invention. It is a figure which shows 2nd Embodiment of the power control apparatus by this invention. It is a figure which shows 3rd Embodiment of the power control apparatus by this invention. FIG. 5 is a diagram showing a mechanism for adjusting power supply voltage to the internal circuit block of FIG. 4. It is a figure for demonstrating unification of the signal amplitude between blocks. It is a figure which shows the mechanism which controls the operating frequency in an internal circuit block. It is a figure which shows 4th Embodiment of the power control apparatus by this invention. It is a figure which shows 5th Embodiment of the power control apparatus by this invention. It is a figure for demonstrating the effect of this invention. It is a figure which shows the modification of the circuit of FIG. 6B. It is a figure which shows the modification of the level up converter of FIG.

Explanation of symbols

1, 5, 11, 21, 31 Processor chip 2 DC / DC converter 3, 4, 13, 14, 23-3-1, 23-3-2, 23-4-1, 23-4-2,. . . , 23-n-1-1, 23-n-1-2, 23-n-1, 23-n-2, 33-3, 33-4,. . . , 33-n-1, 33-n, 42, 51, 63-3-1, 63-3-2, 63-4-1, 63-4-2,. . . , 63-n-1-1, 63-n-1-2, 73-3, 73-4,. . 73-n-1 PMOS transistor 12 Internal circuit 15 Power supply line 22-1, 22-2, 22-3, 22-4,. . . , 22-n-1,22-n, 32-1, 32-2, 32-3, 32-4,. . . , 32-n-1, 32-n, a, b Internal circuit block 43 Local power supply lines 61, 71 Programmable chips 62-1, 62-2, 62-3, 62-4,. . . , 62-n-1, 62-n, 72-1, 72-2, 72-3, 72-4,. . . , 72-n-1,72-n configurable logic blocks _{C D,} C DH, C _DL external decoupling capacitor GND ground line V _{DDL, V DDH} supply voltage

Claims (15)

Comprising a processor chip and power supply voltage generating means for generating a variable power supply voltage to be supplied to the processor chip,
The power control apparatus, wherein the processor chip has power supply voltage determining means for selecting one of power supply voltages generated by the power supply voltage generating means.   2. The power control apparatus according to claim 1, wherein the power supply voltage is generated based on a variable clock frequency for controlling an operation of the processor chip.   3. The power control apparatus according to claim 1, wherein the power supply voltage changes between when the processor chip is operating and when the processor chip is on standby. Comprising a processor chip and power supply voltage generating means for generating a variable power supply voltage to be supplied to the processor chip,
The power control apparatus, wherein the processor chip has power supply voltage determining means for selecting one of the power supply voltages generated by the power supply voltage generating means for each block of the processor chip.   5. The power control apparatus according to claim 4, wherein the power supply voltage determining means is a voltage dropper type.   The power control apparatus according to claim 4 or 5, wherein a signal amplitude between the blocks is selected to be the maximum or the minimum among the power supply voltages respectively supplied to the blocks.   The power control device according to claim 4, wherein each of the blocks has a bypass level converter.   The power control apparatus according to claim 4, wherein the power supply voltage is generated based on a variable clock frequency that controls an operation of each of the blocks.   The power control apparatus according to any one of claims 4 to 8, wherein the power supply voltage changes between an operation time and a standby time of each of the blocks. Comprising a programmable chip and power supply voltage generating means for generating a variable power supply voltage to be supplied to the programmable chip,
The power control device, wherein the programmable chip has power supply voltage determining means for selecting one of power supply voltages generated by the power supply voltage generating means for each configurable logic block of the programmable chip. .   11. The power control apparatus according to claim 10, wherein the power supply voltage determining means is a voltage dropper type.   12. The power according to claim 10, wherein a signal amplitude between the configurable logic blocks is selected to be a maximum or minimum of power supply voltages respectively supplied to the configurable logic blocks. Control device.   The power control apparatus according to any one of claims 10 to 12, wherein each of the configurable logic blocks includes a bypass level converter.   14. The power control apparatus according to claim 10, wherein the power supply voltage is generated based on a variable clock frequency that controls an operation of each of the configurable logic blocks. 15. .   The power control apparatus according to any one of claims 10 to 14, wherein the power supply voltage changes during operation and standby of each of the configurable logic blocks.

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